JPS5865496A - Digital data setting unit - Google Patents

Abstract

(57) [Abstract] This bulletin contains application data before electronic filing, so abstract data is not recorded.

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention relates to digital data setting processing in a digitally processed electronic musical instrument or other digital equipment.

In digitally processed electronic musical instruments, control amounts for various control elements such as volume, vibrato speed, and vibrato depth are required to be provided in digital amounts. Therefore, in the past, separate digital setting devices were provided for directly setting digital data corresponding to various control elements. However, in order to obtain a sufficient range and resolution of the control amount with a digital setting device, an extremely large number of contacts must be installed, and conventionally, such a digital setting device had to be arranged in multiple stages corresponding to the various control elements. Therefore, the manufacturing cost becomes high, the number of wiring increases, and a large installation space is required. To overcome this problem, it is conceivable to use an analog It ratio setting volume as a data setting device and to obtain digital data by converting the output voltage of this volume into a digital form. However, if an analog/digital converter is provided for each volume,
Manufacturing costs are high and a large C1 circuit space is still required.

This invention has been made in view of the above-mentioned points, and is provided with a plurality of analog signal setting means, and the output signals thereof are time-divisionally converted into digital data by one analog/digital converter, thereby reducing manufacturing costs. Another object of the present invention is to provide a digital data setting device that saves the number of wires, installation space, and circuit space.

By the way, if the setting knob of the analog signal setting means is suddenly operated, the analog/digital converter immediately follows the sudden change in the input analog signal and suddenly changes the value of the output digital data. In some cases, inconvenience may occur. In particular, if such a sudden change in setting data occurs in a digital data setting device for a four-child musical instrument, it may cause various inconveniences. For example, if the control element is volume, it will cause undesirable sudden volume changes or clicks, and if the control element is an effect control element such as vibrato speed or tremolo speed, it will cause sudden fluctuations in the chestnut effect. It is rather unnatural. Furthermore, especially in electronic musical instruments, since the setting knobs are sometimes operated while playing the hammer, sudden operations against the player's will are likely to occur, and the above-mentioned problems are also likely to occur. Problems similar to those described above occur not only when the setting knob is suddenly operated, but also when noise is added to the analog signal. In particular, when converting the output signal of the touch sensor into digital, the sensor output is originally a small output, so it is amplified before digital conversion, so even a small noise can have a large effect.

In view of the above-mentioned points, the present invention has a plurality of analog signal setting means, and the output signals thereof are time-divisionally converted into digital data by one analog/digital converter. The present invention further aims to provide a digital data setting device that suppresses sudden fluctuations in set values by controlling the analog/digital converter so as to suppress the amount of change with respect to the previously obtained digital data within a predetermined value. be.

Embodiments of the present invention will be described in detail below with reference to the accompanying drawings.

Description of an embodiment showing the basic configuration of the invention In FIG. 1, VRI to VRn are analog pressure setting volumes, and a plurality of volumes are provided corresponding to various control elements. Desired analog Narita values are set by manually operating the knobs (not shown) of the volumes VRI to VRn to adjust the values of the variable resistors. The analog voltages set by the respective volumes VRI to VRn are input in parallel to the analog voltage multiplexer 200. The analog voltage multiplexer 200 is
The output voltages of the volumes VRI to VRn are sequentially sampled in a time-division manner according to a control signal given from the sampling control circuit 201, and the samples are multiplexed onto a common output line and output.

The analog/digital converter 202 converts the analog voltage applied from the analog voltage multiplexer 200 into digital data.

The memories 206-1 to 20t-n correspond to each volume VRI.
They are provided corresponding to the volumes VRI to VRn, and store digital data corresponding to the setting values of the volumes VRI to VRn converted by the analog/digital converter 202, respectively. The multiplexer and demultiplex control circuit 204 has a function of
Function to allocate digital data corresponding to set values 1 to VRn to predetermined memories 203-1 to 203-H (
(demultiplexing function).

Therefore, from the sampling circuit 201 to the control circuit 20
4 is given a sampling control signal, and the output digital data of the analog/digital voice converter 202 is sent to predetermined memories 203-1 to 203-1 in synchronization with the time-divisional sampling of the analog voltage in the multiplexer 200.
I am trying to distribute it to 3=n. Valley memory 203-1
The digital data stored in 203-n to 203-n is output as data indicating the set value of each control element.

For example, the analog/digital converter 202 calculates the current sampling by adding or subtracting a minute value corresponding to the analog value sampled at the current sampling timing to the digital data obtained at the previous sampling timing. This is a type of method that obtains digital data corresponding to a value. That is; a data register 2o5 that stores digital data, a digital/analog conversion circuit 206 that converts the value of the digital data stored in this data register 205 into an analog voltage, and this digital/analog conversion circuit 2.
A comparator 207 compares the output voltage of 06 with the analog voltage given from the multiplexer 200, and the contents of the data register 205 are adjusted according to the output of this comparator 207! and a data register control circuit 208 for controlling the data register control circuit 208.

In addition, multiplexer and demultiplex control circuit 2
As a second function, 04 reads out the data stored in the memories 203-1 to 203-n in a time-divisional manner in synchronization with the time-divisional sampling of the analog range pressure in the multiplexer 200, multiplexes the data, and performs analog/digital conversion. 202 (multiplex function).

Digital data is read from the memories 205-1 to 203-n corresponding to the volumes VRI to VRn in synchronization with the analog voltage sampling timing for the volumes VRI to VRn, and the analog/digital converter 20
Give to 2. In the converter 202, the digital data (data obtained at the previous sampling timing) given from the memories 20t-1 to 20t-1 to 20t-n via the control circuit 204 is transferred to the data register 20 via the control circuit 208.
Load into 5. The digital data obtained at the previous sampling timing, loaded into the register 205 in this way, is converted to analog 4 by the digital/analog conversion circuit 206.
The voltage is converted into a voltage and compared with the analog voltage sampled this time by a comparator 207.

The control circuit 208 performs control to add or subtract a predetermined value to or from the contents of the data register 205 in accordance with the output of the comparator 207. As a result, data register 205
The value of the digital data stored in the multiplexer 200 changes and approaches the value corresponding to the analog voltage provided by the multiplexer 200. Here, if the above addition or subtraction is repeatedly executed until both input voltages of the comparator 207 match at l sampling timing, digital conversion that immediately follows changes in the input analog voltage can be performed. On the other hand, in order to suppress the change t in digital data at one sampling timing to within a predetermined value, the number of additions or subtractions performed at one sampling timing may be limited to within a predetermined number. A signal responsive to the sampling timing is supplied from the sampling control circuit 201 to the control circuit 208, and predetermined control is performed at each sampling timing in accordance with this signal. When the digital conversion operation for one sampling timing is completed by the control as described above by the control circuit 208, the contents of the data register 205 are taken into predetermined memory 9206-1 to 203-n via the control circuits 208 and 204. .

Note that in order to save wiring and control circuits, the analog/digital converter 202 and memories 205-1 to 203-n
It is preferable to transfer digital data between the two in serial format.

More Detailed Description of the Overall Structure of an Embodiment Next, a more specific embodiment of an electronic musical instrument to which the present invention is applied will be described with reference to FIG. 2 and subsequent figures. FIG. 2 is a block diagram of the overall configuration roughly showing the relationship between the detailed parts of the electronic musical instrument divided and shown from FIG. 3 onwards. The keyboard 10 includes a plurality of keys for selecting pitches (note names) of musical tones.

The touch sensor 11 detects the touch of six keys and generates an output signal corresponding to the touch of the key. Key press detection l11
2 detects the pressed key with the key 11i10 and outputs information TDM indicating the pressed key. The key press detection section 12 scans the key switches corresponding to the six keys, and the output of the counter 16 is used for rounding. The sound generation assignment circuit (key assonator) 14 is used to allocate and generate a musical tone corresponding to a pressed key to one of a limited number of musical tone generation channels, and in one embodiment, it includes a single note key assigner 14A and a double note key assigner 14B. The electronic musical instrument can be operated selectively in either single-note mode or double-note mode. In addition, a single note mode selection switch MON O-BW is provided in connection with the sound generation allocation circuit 14, and when the armpit switch QNO-8W is on, @1'' is output as the single note mode selection signal MONO to the circuit 14. and other essential circuits to enable this electronic musical instrument to operate in single note mode.Slur effect selection switch 8L
-mW is a rounding switch that selects the slur effect,
Slur-on signal 8L when the switch 5L-IW is on
When ON, @l'' is applied to the sound generation assignment circuit 14, enabling the slur effect. In this embodiment, the slur effect means that when the electronic musical instrument is operating in a single note mode, the pressed key is in legato form. When a new pressed key is pressed before the old pressed key is completely released, the pitch of the generated musical note changes smoothly from the pitch of the old pressed key to the pitch of the newly pressed key. .

Various effect setting operator reviews 15 each include round variable operators for setting control amounts of control elements (time, speed, level, etc.) of various effects such as vibrato, initial touch control, and aftertouch control. , where the operator corresponding to the control element for touch control is adapted to adjust the sensitivity of the output signal of the touch sensor 11. To give an example of various effects, pitch control related items include "vibrato", "delay vibrato", "attack pitch control", "aftertouch vibrato", and the aforementioned "slur", etc., and level control related i is r initial. These include touch level control J, r7 lid touch level control, envelope sustain time control J, etc. "Delay vibrato" is an effect that gradually adds vibrato after the time elapsed from the start of the sound of a musical note.
"Attack pitch control" is an effect that adds vibrato at the beginning of a musical note. In this embodiment, the "attack pitch control" is controlled in response to a single key touch (preferably in response to an initial touch).

"Aftertouch vibrato" controls vibrato in response to a key touch that corresponds to a key press pattern. [Initial touch level control] controls the level of the musical tone according to the initial touch of the key when the key is pressed down (this is called the initial touch), and "aftertouch level control" controls the level of the musical tone in response to the initial touch of the key (this is called the initial touch). This is to control the level of musical tones in accordance with the key touch (this is called aftertouch) in step 11. Depending on the initial touch and aftertouch, nine controls can be performed not only on pitch and volume, but also on timbre and other musical tones.

In this embodiment, the setting data corresponding to each operator output from the operator details 15 is expressed as an analog voltage.
, analog voltage! These analog voltages are time-division multiplexed by a lutep receiver 16. Analog/digital conversion (
The unit 17 (hereinafter simply referred to as Mu/D conversion) is the Mu/D converter 1
8 and a control and storage unit 19], the multiplexed analog voltage is A/D converted, and the digitally converted setting data of each operator is stored and demultiplexed. The output of the counter 16 is used for time division multiplexing in the multiplexer 16 and control in the A/D converter 17.

In this embodiment, initial touch and aftertouch are detected using a common touch sensor. That is, a touch sensor 11 capable of aftertouch detection is used, and the output signal of this touch sensor 11 is selected for initial touch detection for a predetermined period of time from the start of key pressing, and the selected touch sensor 11 is used for initial touch detection. The initial touch is detected based on the output signal. For example, the peak value of the selected touch sensor output signal is held for a predetermined period of time from the start of key pressing, and this peak value is used as the initial touch detection signal. for that,
An initial sensing signal is sent from the sound generation allocation circuit 14 for a predetermined period of time (for example, a period of 10m5i1 degree, which is negligible to human hearing) from the start of key pressing! The multiplexer 16 and the M/D converter 17 are controlled by this signal ILK, and during this period, the above-mentioned initial touch detection is exclusively performed. At the same time, in the sound generation assignment 1 path 14, the start of sound generation of musical tones is delayed while the initial sensing signal 1g is output. This is to prevent the start of sound generation before the initial touch is detected, and to enable initial touch control at the same time as the start of sound generation. Incidentally, as described above, in this embodiment, the attack pitch control is also performed in response to the initial touch.

The effect applying circuit 20 is a rounding circuit that applies various effects related to pitch control, including vibrato, delay vibrato, attack pitch control, and a rounding circuit that modulates the pitch rotation number. A modulation signal VAL is output, and regarding a slur effect, a slur effect is added and a sound frequency information block is output. Mu/D conversion I! Of the setting data of the type effect setting repeater outputted from 17, pitch control-related setting data is given to the effect imparting circuit 20, and level control-related setting data is given to the tone signal generating section 21. The effect applying circuit 20 is supplied with an attack pitch start signal S, a slur start signal 88, and a key code MKC indicating the pressed key in the single note mode from the sound generation assignment circuit 14. The single note key assigner 14A selects a single key from among the pressed keys (for example, the lowest pressed key of the 19th press) and outputs it as the pressed key key code MKC for the single note mode.

The attack pitch data ROM (abbreviation for read-only memory) 22 contains attack pitch control datum P8.
AP') and AP') are stored in advance. Attack pitch control is an effect that is particularly suitable for wind instrument tones because it is controlled in a round manner suitable for each tone, for example, and can express the disturbance in pitch at the beginning of a wind instrument's blowing. That rounding, tone selection switch 2
Depending on the round tone selected by RO, the Attata Pitch Suntrol is suitable for that tone! J! The control datums ps, MUPR, MUPUR having values that can be expressed are read out from the ROM 22. The elements that control the attack pitch are the depth of the initial pitch deviation (at the beginning of the sound), the envelope that shows the temporal change in pitch deviation O#l, and the number of repetitions of the pitch deviation. It is. The depth of the initial pitch deviation, ie, the initial value of the attack pitch, is set according to the above-mentioned initial touch detection data.

Specifically, the initial attack pitch value is set according to the initial touch and the timbre (by scaling the initial touch detection data by the attack pitch initial value coefficient datum PBK corresponding to the timbre). # of pitch deviation
It is set by the attack pitch envelope plate datum pici4c, which indicates the temporal change in the amplitude. It is set by the repetition number of circumferential wrinkles of pitch deviation and the attack pitch rate datum P 凰.

Effect imparting path 20 is an attack pitch start signal 8
When 9 is given, it starts forming a modulation signal VAL for attack pitch control based on the above-mentioned data, and then forms a modulation signal VAL for normal vibrato, delay vibrato, or aftertouch vibrato. In order to form the modulation signal VAL, the effect imparting circuit 20 is designed to facilitate control of the modulation frequency and modulation depth.

9. At effect imparting time 1120, slur start signal S
When 4 S is seen and 9, processing is performed to smoothly change the musical tone frequency information SKC of the pressed key for the single note mode from the value corresponding to the old pressed key to the value corresponding to the newly pressed key. The newly pressed key is indicated by the single note mode pressed key code MKCK given from the sound generation assignment circuit 14.

In the musical tone signal generation section 21, in the single tone mode, musical tone frequency information 8K for the single tone mode given from the effect imparting circuit 20 is used.
A musical tone signal is generated based on the CK, and in the multitone mode, it is divided into multiple channels given from the sound generation assignment circuit 14 (II tone key assignment: t-14B), and the key code PICCK4 to 111 [number of keys indicating nine pressed keys] is generated. A musical tone signal is generated in each channel. The frequency (pitch) of these musical tone signals is modulated according to the modulation signal WALK, and the volume level is controlled according to the level control data from the music 21 conversion 1117. Furthermore, the tone selected by the tone color selection switch 26 is added to these musical tone signals, and the tone signals are fed to the sound system 24.

Next, a detailed example of each part of the #I2 diagram will be described.

Explanation of the key press detection unit and the single note key assigner [Figure I3 shows the key press detection unit 12 and the click key assigner. 16 detailed examples are shown 9
, FIG. 4 shows a detailed example of the single note key assigner 14m. The counter 16 receives the second phase system clock pulse φ1. A 16-stage/l-bit shift register 25 controlled by φmK and a 1-bit half adder 26
and a latch path 27 that periodically f/C5-latches the contents of the shift register 25, and performs counting operations by serial calculation. In the detailed example described below, serial calculations are used throughout the counter 13, which contributes to saving on the circuit configuration.

The key press detection unit 12 includes a key switch matrix 28 in which key switches corresponding to the six keys of the keyboard 1o are arranged in a matrix, a decoder 29 that supplies a scanning signal to input keys of every half octave in this matrix 28, and and a multiplexer 6° for multiplexing the output line signals corresponding to each of the six note names within each half-octave in the matrix 28. key switch matrix 28
is scanned by J[lK from the treble side key switch, and the single note key analyzer 14A selects the highest pressed key as the pressed key for the single note mode.

Scanning Qr for l keys in the key switch matrix 28
In other words, the processing time for l keys in the 14-m single note key assigner (this will be referred to as 1 key time)
consists of 32 bond time slots as shown in Figure 5-. l The length of the time slot is the system clock pulse φ
It corresponds to one period of φ:, and the length is 0,511 m. Therefore, the length of one key time is lams. Various processes are controlled periodically at each time slot within this l key time. To round this off, various O timing signals as shown in JllI511 are generated by a tie signal generation circuit (not shown) and supplied to various '& circuits. 32110
Time slots l) Each is repeated with a period of 1611s. The rounding that distinguishes individual time slots within a key time will be referred to as 1st and 1st tie slots in order of occurrence. In order to make the generation timing, generation period, and pulse width of various timing signals clear at a glance, each timing signal is assigned a code according to the following rule. For example, when numbers are written before and after the letter ryJ, such as rly8J, sha, front +
The 110 number #il key time KTh indicates the time slot number in which the pulse first occurs, and the latter number indicates the period in which the pulse repeatedly occurs in time slot number. For example, the signal lt8 is initially generated in the first tie slot, as shown in FIG. Next, in rly88J, which has the letter [J added to the end, the pulse width is not Fi over the entire l time slot width, but a half of the l time slot, that is, the clock pulse - It means that it occurs in synchronization with the desired pulse width.Also, when numbers are written before and after the character 1T, such as "rlT8", the time slot order indicated by the former number is Assume that the pulse (@1''') continues to occur up to the time slot order indicated by the latter number, and that the period is #'i32 time slots.For example, the signal IT8 is generated from the first time fourth to the fourth time slot. It has a pulse width of 8 time slots that continuously occurs in the interval up to 8 time slots, and repeatedly occurs at a period of l time slots.In addition, the pulse width display rl T 6J as in "l terror y8" When 0 is followed by the letter ryJ and a number, the number written after the letter ryJO indicates the local area by the number of time slits. For example, the signal 16y8 first occurs in a 6 time slot width from the first time slot to the 6th time slot, and a good pulse is generated with a repetition period of 8 time slots, and then from tSSe2 to the 14th time slot, and from the 17th to the 17th time slot. This means that pulses are generated in each section up to the fourth time slot and from the fifth to the fifth time slot.

In Figure 1 and 3, the output 916 of the final stage of the shift register 25 is applied to the adder 260 cam, and the signal 17y32 is applied to the input ci via the OR circuit 61. Therefore, the 17th signal 17 y 32 becomes 1''.
When the time is 4 KTh and 1'' is added to the output of the final stage of the shift register 250, it becomes.When both the input cam and CI are @1'' and a carry signal is generated,
The carryout output C・+1 is arithmetic tireing) is also 1
Assume that the time slot is delayed and becomes @l''.C・0
Next, add a circle symbol + 1 til time slot) to indicate 0 deviation. The carry output of the adder shown below is C・+
1 is l time slots behind the calculation timing. It is assumed that there is no delay in the addition output 8. Carry field output C, +1 is AND circuit s
2 and the OR circuit 61, it is returned to the input Ci. Therefore, the carry signal can be added to the upper bits.

The output aO signal of the adder 26 is inputted to the shift register 25 via the AND circuit 66, and returned to the input cam after a delay of 16 time slots. The signal z1 applied to the other input of the AND4 path 66 is normally "1'". With the above configuration, a serial operation is performed in which the count is increased by one every l key time (32 time slots) using the signal 17y32 as a count clock. Therefore, the first
The signal output from the last stage of the shift register 25 in the 7 time slots is the least significant bit of the count value, and at that time, each stage has the first to last stage.
The count values of the top (Pi)O count values are stored sequentially going back to the stage. Similarly, in the first time slot after four (17th time slot) 016 times, the count values of K from the most significant stage to the first stage of the shift register 250 are arranged from the least significant bit to the most significant bit. Therefore, the signal ly 321! occurring in the first half of the first time slot! K therefore shift register 25
C) 7th stage output Q7 to final stage output Q16
By latching this in the latte circuit 27, a 10-bit j1 column 2 different count value is obtained. Gang, signal IF16
The AND circuit BL2 is made inoperable in the 0 tie, that is, in the 1st and 17th time slots, and this is to prevent the carry signal of the most significant bit from being added to the least significant bit.

The count value of the lower 7 bits of the counter 1 black is used for key scanning and multiplexing. Among them, the bottom 4 pits) a4. ;w3. *2. Specify the note name of the key (note name within l octave) by drunkenness, top 3 pitches) 13.1! ,
III specifies the octave to which the 0 key belongs. Bits B3 and B2 of the nine count values are latched in the latch circuit 27.

B1 and N4 are decoded by a decoder 29, and four scanning signals are applied to input lines for every half octave in the key switch matrix 28. Maku, lower pitch) N3. N2. N
l is applied to multiplexer 60, which time division multiplexes the signals of the six output lines within each half-octave in key switch matrix 28. In this way, time-division multiplexed key data 'rDllI indicating the press or release of six keys is output from the multiplexer t60 in response to the scanning of six keys. Time division multiplexing key data TDMFi If the key currently being scanned is pressed, @1'' is 69, and if it is not pressed, it is @O.

Since the key to be scanned changes every time the count value B3 ~ correction latched in the latch circuit 27 changes, the scanning time for one key is from the first time slot to the nth time slot as shown in FIG.
There are 32 time slots up to the time slot, and during this time, the key data DM for one key is continuously output. As mentioned above, ■One key time spent scanning a key is 16μ.
Since it is determined by S, l scanning nicles, that is, the count value is 13
~ Approximately 2m island where the revision goes around once (Fable 16J11 x 2
).

The key switch matrix 28 is set at tk-) so that scanning is performed in the order of high notes. That is, count value i】
6 keys are sequentially assigned corresponding to the predetermined value so that the small h and treble) and the large heart and low notes, and as the count value 13 to N1 increases, the treble to low notes are sequentially changed. The scanning is now shifted to the side. The count value (13~punishment) of the lower 7 bits of the counter 1 black is the O key currently being scanned, that is, the time division multiplexed key data TDM.
A code signal representing a key corresponding to K, that is, a key code K
It is C. However, the count value i of the counter 12S]~
As for the key code KC, the value of tt is small for high-pitched keys, and the value is large for low-pitched keys. The pigeonhole that converts the key code into frequency information by repeatedly adding the lower two bits of the key code to the lower digits, and the process of becoming a treble key - there will be a problem if the code 0 value does not become large, so the counter The key code KC output from the key assigner 14A,
I am trying to use it at 14m.

For example, the relationship between the official key code KC and the six keys is as shown in the following table. The key code KC is the upper 3 bits of the octave code 113, 112. Bl and the lower 4 bits of the note code N4. N3. N2. It consists of Nl.

In Table 1, the display in the seventh to final stages of the shift register 25 shows the weight of each stage of the first and seventeenth time suits. In other words, this first
0 to final stage (QIO to Q16) Ka mentioned above 9
Contains the lower 7 bits 13 to N1 of the count value. First, the seventh to ninth stages (Q7-99) contain bits of about 8 tns in time representation, about 4 tns, and about 211,110 weights. These time displays are counter 1
These time display bits are used when the counter 16 is used as a timer, as will be described later. Bit is key code 11
3-) is latched in latch path 27 along with II.

In FIG. 4, the single note key assigner 14 is configured to time-division multiplex keep-vertical DMK-processing for six keys starting from the ninth time slot. Seventy round,
The 9 time division multiplexed key data 'rDMtj output from the 311th multiplexer JSO is the latch circuit 64 in FIG.
and is latched in synchronization with the ninth time slot by signal 9y32. Therefore, the latch circuit 414 outputs the key data TDM delayed by 8 time slots. On the other hand, the lowest pitch (Nl) of the key code KC output from the final stage (Q16) of the shift register 25 (FIG. 3) in the first time slot is the 8th pitch in the ninth time slot after eight time slots. It has been shifted to stage (Q8).

Therefore, in order to synchronize with the slow grinding of the key data TDM in the latch EWt64 (Figure 84), the shift register 25
The output of the eighth stage (Q8) in FIG. 3 is taken out as a serial key code KC (9-) and supplied to the single note key analyzer 14A in FIG. 4. This key code KC (9~.) is from the 9th time slot to the 15th time slot.
Each bit (Nl) sequentially from the least significant bit up to the time slot.

N2. N3. N4, 111.12.13 are lined up.

This key code KC (9-) is inverted by the inverter 5 in FIG. 4, and the above-mentioned official key code KC is output from the inverter 65 in serial form.

In Figure 4, the single note key assigner 14 is mainly
perform one function. One is to select the key code KC of the highest pressed key, the other is to detect a new key press, and the other is to set a constant value when a new key press is detected. The purpose of the present invention is to prohibit processing related to keys being pressed without interruption, and to enable detection of an initial touch during that period. Detection of a new key press is performed when some key is pressed for the first time after all keys have been released (this is called any key-on), and when some key is pressed in legato form from a state where any key is pressed. When the key is changed to a new round key press (this is called legato 221 key on)
It is designed to be done separately. If any key-on is detected, the flip-flop AKQ is set, and if any legato key-on is detected, the flip-flop NKQ is set. When the key-on detection causes the 7-lip program KQ or NKQ to be set, the counter 16 shown in FIG. 3 is operated as a timer, and the initial sensing signal Ig is output for a certain period of time (approximately IQms).

Processing related to this newly pressed key is prohibited, and when the predetermined time period ends, an attack pitch start signal A8 or a slur start signal S8 is generated to start control of the attack pitch or slur. The highest pressed key key code register 36 is for temporarily storing the key code XKC of the highest pressed key, and the single note key code register 37 is for storing the key code M of the pressed key that is sounded in the single note mode.
It is a rounded one that stores KC. At the end of the certain period of time, the key code XKC of 6 is entered in register 6.
7. Therefore, the pressed key code MKC for the single note mode does not change immediately when a new key is pressed, but changes after the predetermined period of time.

7 lips each 70 tubes XIQ, MKI, MK2゜AKQ
, NKQ, TM61d loads input signals by timing signal 6y8 (see Figure 5) and loads input signals by signal 1y8 (5th
Figure) Switching the output in synchronization with K.

Therefore, the load good signal is continuously output for 8 time slots from the signal 1y80 generating time slot (1t9th, 91st, 171st, 6th time slot).

Flip 70 is used to indicate that some pressed key is detected in one scanning cycle. When the key data TDM output from the latch circuit 64 is 11'', this 7-lip 70-bit XKQK" 1 '" is loaded via the AND circuit 8 and the OR circuit 40. ” is held via the AND circuit 69 and the OR 1 circuit 40.

When the l-scan cycle is completed and the inverter 410 output becomes @0'', the AND circuit 69 becomes inoperable and the 7-lip 70-tub XKQ is reset.The count value output from the latch circuit 27 in FIG. Lower 3 bits N3
, N2 , )il are input to the AND(c) path 42,
Upper 4 bits igo, B2.11. )14 is AND circuit 4
It is input in a. The output signal N7 of the AND circuit 42 and the output signal B15 of the AND circuit 46 are input to the AND circuit 44 in FIG. At the end of one scanning cycle, all bits from the count value 11 to the penalty become 11'', and the signals N7 and B15 both become ``l'', and the condition of the AND circuit 440 is established.Other inputs of the AND circuit 44 A timing signal 9T16 (see FIG. 5) is input. Therefore, the output of the AND circuit 44 becomes '1' from the 9th time slot to the 16th time slot at the end of one scanning cycle. The output signal 11'' of this AND circuit 44 is the scanning end signal 80.
If E is selected, inverter 41 inverts this signal SCE. Therefore, when some - is pressed, the output of the 7 lip-flop 1".When no key is pressed, XK
Q is always @0''.

A signal obtained by inverting the output of the flip-flop XKQ and the key data TDM output from the latch circuit 64 are input to the good AND circuit 45, which is a round circuit for detecting the highest pressed key. In other words, due to the delay of 8 time slots between input and output in Flip Syrup XKQ, the key data TDM of the most pressed key is
``When the key data TDM rises, the output of the flip-flop xxQ is still @0'' during the 8 time slots of the rising edge of the key data TDM, that is, the 9th to 16th time slots.
The inverted signal is #i@1''. Therefore, the condition of the AND circuit 45 is satisfied only at the 9th to 16th time slots (8 time slots in total) of the rising edge of the key data TDM of the most pressed key. The output signal XS becomes @1''. The AND circuit 46 is enabled by "1" of the signal XS, and the key code EC of the most pressed key given from the inverter 55 is loaded into the register 66 via the AND circuit 46 and the OR path 47.

9, the key code KC output from the inverter 65 and the key data TDM output from the latch circuit 34
The key code K of the most pressed key is synchronized with
C is loaded into register 36 in order from the least significant bit.

All bits N1 to B3 of key code KC are 9th to 15th bits.
is loaded into register 66 between timeslots and the first
In the 6th time slot, unrelated count data is stored in the key code KC. For the rounding, the timing signal 16 V 32 is inverted and the good signal is added to the AND circuit 46, and in the 16th time slot, the 10 g'
is loaded. The nine highest pressed key key code XKC loaded into the register 36 is self-held via the AND circuit 48. The signal XS is inverted by an inverter 49 and a good signal is added to the other input of the AND circuit 48, enabling the AND circuit 46 and transmitting the key code KC to the register 3.
When loading to 6, I try to clear self-hold.

The register 36 and the register 417 to which the contents XKC of the register 66 are transferred are 8-stage/1-bit shift registers, and the system clock pulses φ1. The shift is controlled by φ3. Therefore, registers 66 and 6
The contents of 7 are rotated every 8 time slots. In the figure, the weights of each stage of registers 36 and 37 at the 9th, 17th, 25th, or 1st time slot are shown.

The flip 70 knob MKi is a rounded one indicating that some pressed key was detected in the previous scan cycle. When one cycle of scanning is completed, that is, when the scan end signal 8CE is @1'', AND1 is executed on the condition that @1'' is stored in the slip-flop XKQ.
The slip flop MKi outputs @1'' through the OR circuit 52 and loads the slip flop MKll (11''). It is held during the cycle and reset by the scan end signal 8CE.

The slip-flop MK2 is for indicating that some pressed key was detected in the previous i scan cycle. When the scan end signal 5cic is generated, slip 7
The output of the 0 tube MKl is connected to an AND circuit 53 and an OR circuit 55.
Load it into the 7rip 707'MK2 via. The AND circuit 54 is for holding the memory of the flip 70 block MK2 for one scanning cycle, and is used to receive the scanning end signal 8CK.
When this occurs, the flip-flop MK becomes inoperable.
Reset 2. These three 7 lips 70 tubes
KQ, MKl, and MK2 are useful for detecting key suppression and key release in single note mode without chattering.

Flip-flop AKQ is used to indicate that the aforementioned any-key-on has been detected. The AND circuit 56 includes the output of the flip-flop XKQ, the flip-flop MKi, , MK2゜A K Q r N K
When the inverted output of Q and the scan end signal SCE are applied, the condition is met when any key is on, and I+ is output at the timing of the scan end signal 8CE. In other words, in the AND circuit 56, no key was pressed at all in the previous scan cycle and the scan cycle before the previous one (MKl, MK
2 are both @0"), and a key press is detected for the first time in the current scan cycle (XKQ is @l"), any key-on is detected. The reason why the inverted outputs of AKQ and NKQ are added to the AND circuit 56 is because AKQ
This is to prevent the AND circuit 560 condition from being satisfied when "or NKQK@1" is stored), and to prevent the timer described later from being reset to the start state many times. The output signal is loaded into the 7 lip-flop AKQ via the OR circuit 58. This flip 70 tripmu KQO "1" is held for a certain period of time via an AND circuit 57 and an OR circuit 58.

The output signal @l'' of the AND circuit 56, that is, the 22-N key-on detection signal, is also used as a timer start signal.
It is input to the 7th lip 70th tube 60°61 of the stage. These 7 lip flops 60°61 are Aritsubu 70tsubu XK
Like Q, it is controlled by timing signal 678.1y8. The outputs of both seven lip-flops 60 and 61 are applied to an OR circuit 62, further inverted by an inverter 6!1, and input as a signal z1 to an AND circuit 66 in FIG.

The any key-on detection signal output from the AND circuit 56 is synchronized with the scanning end signal BCBVC.
It becomes @l'' during 8 time slots up to 6 time slots. This is expanded to 16 time slot width by 7 lip-flops 60°61 and OR circuit 62, and the output signal z1 of inverter 66 becomes 0'' during 16 time slots. Make it.

At all other times, the signal z1 always remains at 11", allowing the counter 16 (FIG. 3) to perform a counting operation. During the 16 time slots when the signal z1 becomes @0", the AND circuit 66 (FIG. 3) (Fig. 3) becomes inoperable, and the contents of all 16 stages of the shift register 25 are cleared to 0. In this way, the counter 16 starts counting from all count values of 0, and the timer function starts. .

Of the count value latched by the latch circuit 27 in FIG. 3, the bit with a weight of about gms in time representation is input to the AND circuit 64, and the bits with weights of about 4 ms and about 2 ms are inverted, respectively, and the AND circuit 64 other inputs. The output signal TM5 of this AND circuit 64 is applied to an AND circuit 65 in FIG. The AND circuit 65 has a third
AND circuits 42 and 42 in the figure! I to signals N7 and B1
5 is input, and the timing signal 9T16 and the output of the OR circuit 66 are also added. The OR circuit 66 receives the outputs of 7 lip flops KQ and NKQ. The output of the AND circuit 65 is used as a timer end signal QB. The reason for inputting the output of the 7-ripple pump KQ and Hiro NKQ to the AND circuit 65 is 1. These flip 70 knobs are set and the timer function is activated only when the key is turned on at the ninth position.

The count value of the lower 10 bits of the counter is “100”
1111111'', that is, approximately 10 m$ has passed since the time when the signal was cleared by signal 21, and at 9 o'clock,
All the conditions of AND circuits 42, 45, and 64 (Fig. 3) are satisfied, and the signal N is applied to the AND circuit 65 of Fig. 4.
7,115. All TMS becomes @l''. At this time, the output signal QR of the AND circuit 65 becomes 1'' during the 9th to 16th time slots in response to the signal 9T16. Note that the symbols (9 to 16) written next to the signal lines in the figure mean that this signal is generated from the 9th time slot to the 16th time slot.

This timer end signal QR is inverted by an inverter 67 and applied to an AND circuit 57. Therefore, flip flop A
KQ @1” is held for about IQms until the timer end signal QR is generated, but this timer end signal Q
R occurs and is cleared at 9 o'clock. Specifically, when the timer end signal QR falls at the 17th time slot, the output of the 7-rip, 70-tube AKQ also falls to "o".

When the timer end signal QR is generated, 7 rip 70 rip
On the condition that @l'' is set in KQ (the key is being pressed), 8 is set to the output signal of the AND circuit 68.
”. This signal enables AND circuit 69 by 8, register! 16th highest pressed key key code IIC (
This shows the new friend press key) for the AND circuit 69
and register via OR circuit 70! 17. The key code of the new highest pressed key loaded into the register 67 is output from the key assigner 14A as the pressed key key code MKC for the single note mode, and is also outputted from the AND circuit 7.
1 through register 37.

When loading the new key code XKC to the signal 8, the AND circuit 71 becomes inoperable and the old key code MKC is cleared.

The AND circuits 72.7M and 74, the OR (c) circuit 75 and the slow sharpening flip 70 knob 76 are for rounding and comparing the key codes XKC and MKC of the registers 66 and 67. The inverted signal of the key code MKC and the key code XKC are input to the AND circuit 72, and the inverted signal of the key code XKC and the key code M section C are input to the AND circuit 76. Key codes XKC and MKC have the same weight Opi) Nl-1
3 are synchronously output from registers 66 and 37, respectively.

If the values of both key codes MKC and XKC differ by even 1 bit, the AND circuit 72 or 750 condition is satisfied, 1 to 7, and the flip 70 block 7+6K"l" is loaded. @l'' of this 7-rig flop 76 is self-held via an AND circuit 74.The highest pressed key detection signal xS is sent to an inverter 49
The pressure signal is inverted and applied to each AND circuit 72, 76, 74, and the memory of the knob 70 is cleared every time the highest pressed key is detected in each scanning cycle.

Flip-flop NKQ is a rounded flip-flop indicating that the above-mentioned new key-on has been detected. AND circuit 77IIi is for detecting legato new key-on, and is the output signal N11 of the 7 lip-flop 76.
．． A single note mode selection signal MONO, output signals of 7-rip flops XKQ, MK1, and MK2, signals obtained by inverting the outputs of 7-rip flops KQ and NKQ, and a scanning end signal BCE are input. Single sound mode selection signal MONO
is entered into the rounding that allows detection of legatonie key-on only when in single note mode. As mentioned above, the key code for Shi Jistaro 6 and 67 is XKC.

When MKC is different, the output signal NIQ of the Arriv flop 76 becomes ``1''. This signal NEQ of 11" indicates that a new key has been pressed. If this new key is 4, which corresponds to any key on, then the AND (c) path 56 is Since the condition is met and the flip-flop KQ is set, its inverted signal becomes O.
”, and the 770 condition does not hold.If this new nine key press corresponds to legato 221 key-on, then 7 lip flop KQ is 4y), and each flip 70 knob XKQ , MK1.MK20 output is @1'', indicating that some key is persistently suppressed. Therefore, in the case of legato knee-key on, the condition of the AND (c) circuit 77 is satisfied when the scanning end signal BCEO is established, and the 7 rip 7 is passed through the OR circuit 79.
@l'' is loaded into the 0-tube N section Q. @1'' of the Artub flop NKQ is self-held via the AND circuit 78.

On the other hand, the nine-legato new key-on detection signal outputted from the AND1 path 77 is passed through the OR circuit 59 to the delay flip 70 knob 60, similarly to the any key-on detection signal.
is used as a timer start signal. Therefore, based on the legato any key on detection, the counter 16 in FIG. 3 functions as a timer in the same manner as described above, and approximately I
After Qms, the timer end signal QR is output from the AND circuit 65 (FIG. 4). This timer end signal QR makes the AND circuit 78 inoperable, and the 7 lip-flop N
KQ is reset. Therefore, the flip 70 knob NKQ holds 11'' for about IQms after the legato new key-on is detected.

Further, as described above, the AND circuit 68 outputs the signal KB based on the timer end signal QRK, and the new highest pressed key key code XKC stored in the register 66 is loaded into the register 67.

The flip-flop TM6 is a rounded flip-flop indicating that the waiting time of about 10 m5 due to any-any-key-on has ended in order to form an attack pitch start signal in the double tone mode. The timer end signal QR is input to the flip-flop TM4 via the AND circuit 80 and the OR circuit 82.
When the waiting time of about IQms is completed, this timer end signal QRK causes the flip-flop TM6 to
l'' is set.Jin's 7 lip flop TM601
1'' is self-held via the AND circuit 81 and reset by the scan end signal SCE.Therefore, 11'' of the arrest flop TM6 is held for only one scan cycle. Note that in the double-note mode, the detection of the Leonton key-on is not performed, so in the single-note mode, the timer end signal QR based on the double-tonnie key-on is not detected.
Therefore, 7 rip 70 g TM6 is set, and even if it is 9, it has no effect.

AND circuits 86, 84, and 85 are round circuits that form a key-off signal MKOF for single note mode. Each circuit 8J
When the #i single note mode selection signal MONO is applied to S, 84.85, it becomes operable in the single note mode. And(c) path 85 has flip-flops MKI, MK2.
) @1'' on the condition that the JKQ inversion signal is input and the release of all keys is detected for two consecutive scan cycles.
Output.

The output of this AND circuit 85 @l''IIi indicates normal key-off.The condition that MKl and MK2 are both 60'' is to prevent chattering. The AND circuit 85 receives the output of the 7-lip flop AKQ and outputs a function 11'' of the waiting time of about IQms when any new key-on is detected.
Lip 70 tube NKQ output and slur on signal 5LO
When N is inverted by the inverter 86 and a large signal is applied, ``1'' is output for a waiting time of about 10 m1o when the new key is detected (Legger) on the condition that the slur effect is not selected.

The outputs of the AND circuits 8M and 84.85 are input to the OR circuit 87, and are used as the key-off signal MKOF for the single note mode. This key-off signal MKOF is sent to the inverter 8.
The key-on signal M section O for single note mode is reversed at 8.
It is N. In the musical tone signal generation section 21 (FIG. 2),
The amplitude envelope may be controlled based on this key-on signal MKONK, which generates a musical tone signal corresponding to the pressed key key code Ml:CK for the single note mode.

If any key-on is detected in single note mode, or if legato any key-on is detected when no slur effect is selected, attack pitch control is performed, and initial touch detection is performed for this purpose. A certain waiting time (approximately 1
Between 0m5)O, the output of AND circuit 8S or 84 is “1”
′, the key is forcibly turned off. And-
The outputs of paths 86 and 84 are output from the key assigner 14 as a forced dump signal FDMP via an OR circuit 89, and are applied to a tone signal generator 21 (FIG. 2) K.

The output of the AND circuit 84 is also given to an OR circuit 90.

In front, the output of the 7-lip flop KQ is connected to the AND circuit 91.
is applied to the OR circuit 90 via. Incidentally, the AND circuits 38, 80.degree. 91, etc., which have only one input, simply pass the input signal, and are not particularly necessary, but are omitted for the sake of illustration. The output of the OR circuit 90 is the initial sensing signal I
s is used for initial touch detection. This initial sensing signal! 8 is about IQms from the start of suppression of a new key based on the output of the flip-flop AKQ when any new key is turned on regardless of whether the mode is single note mode or double note mode.

11''.Also, if there is a legato new key on when the slur effect is not selected in single note mode, the IQmi will be approximately IQmi from the start of suppression of the new key based on the output of the flip-flop NKQ.

The interval becomes "l". When the slur effect is selected in the single note mode, the legato new key-on signal Ig is not generated.

The AND circuit 92 is a round circuit that generates the attack pitch start signal MAII for the single note mode, and the key-off signal MKOF from the OR circuit 87 and the flip-flop X
A KQIDm power signal and a timer end signal QB are input. During the waiting time of approximately 16 m5 based on any key-on detection, the output signal of the AND circuit 86 or 84 causes the key-off signal MKOF to change to @l", and the ALED circuit 92 becomes operational. When the waiting time is over, the key is turned off. Under the condition that it is pressed (XKQ is @l''), the output signal M8 of the AND circuit 92 becomes ``l'' at the 9th to 16th time slots corresponding to the timer end signal QiLK. This signal is input to the slow fall flip-flop 94 via the MASH OR circuit 9i1. This 7-rig frog 94 loads the input signal with the timing signal 13 y 32,
The output is switched by the signal 17T24Ktj three times. Therefore, the signal MA8 generated in the 9th to 16th time slots
e) “l”Fi is loaded into the 7-rip 70 block 94 in the 13th time slot, and the attack pitch start signal B is loaded for one key time (32 time slots) from the 17th time slot to the next 16th time slot. is output as

AND (b) path 95U is the rounded 4 that generates the attack pitch start signal EAS for the compound tone mode, and the slip 70 is the rounded 4. The output of M6, the inverted signal of the output of clip-flop XKQ, the signal obtained by inverting the single note mode selection signal MONO by inverter 96, and the key data TDM from latch circuit 64 are input. In the double tone mode, the output "l" of the inverter 96 enables the AND circuit 95 to operate. As mentioned above, the output of the 7-rip 70-tube TM6 becomes 1'' during one scanning cycle immediately after the end of the approximately IQms time wait based on the any new key-on detection, and the output of the key data TDM of the highest pressed key in this cycle becomes 1''. Ando Road 9 between 9th and 16th timeslots
50 conditions are satisfied. The output signal IA8 of the AND circuit 95, which becomes 11'' between the 9th and 16th time slots, is input to the flip 70 and the flip 94 via the OR circuit 96.
Similarly to the above, the attack bits are outputted as the 8+- bit signal A8 during the l key time from the 17th time slot to the next 16th time slot.

AND circuit 97 is a round 4 circuit which generates slur start signal 88 and timer end signal QB.

Output of flip 7o tube XKQ, single tone mode selection signal M
A key-on signal MKON for the ONO1 single note mode and a signal NEQ indicating a key code mismatch are input. Register 66 and! 17 key code XKC.

When MKC matches and there is no tee (NleQ @1”),
It is in the waiting period (MuKQtk#1NKQ is 11"),
At this time, if the conditions of AND circuit 8 and 840 are not satisfied (MKO)J is ``1''), it means that the slur effect is selected and the legato new key is on. Therefore, the slur effect is selected and
When there is a legato new key-on, it is determined that the key is currently being pressed (
Under the condition that The slur start signal SS is output for one key time from the 17th time slot to the next 16th time slot.

As described above, the attack pitch start signal AS and the slur start signal &IS are generated after the waiting time of about IQms ends. In the single-note mode, the attack pitch start signal S is the legato tone λ when the Kosan-221 key is on or when the slur is not selected.
- Generated when the key is turned on; in double tone mode, generated when the any new key is turned on. Further, the slur start signal SS is generated when there is a shikata-to any key-on when selecting a slur in the single note mode.

A detailed example of the various effect setting operator group 15 is shown in FIG. For convenience of illustration, the A/D converter 17 is shown in the sixth column, and the control and storage section 190 is shown in FIG.

In the sixth factor, the various effect setting operator group 15 includes rounded scales v1 to v8 for setting the control N11l corresponding to the control elements of the various effects using analog voltages. VI
Fi vibrato speed (ji6 number), v2 is the vibrato depth (depth), v4 is the delay vibrato time, v5 is the speed of pitch change in the slur effect (slur speed), v7 is the attenuation series f of the sustain part of the amplitude envelope (sustain speed). Vru. V6. VB is touch sensor 1
1 is a polyneem for the output signal 0 sense flinl. V3
4 adjusts the sensitivity of the key touch detection signal for setting the depth of aftertouch vibrato, v6 adjusts the sensitivity of the key touch detection signal for setting the level of aftertouch level control, and Vaa adjusts the sensitivity of the initial touch detection signal. It is something to do.

The initial touch detection signal ti whose sensitivity has been adjusted with Polyneem V8 is used for two purposes. One is the rounding of the initial value setting of the attack pitch control, and the other is the level setting of the initial touch level control.

As the touch sensor 11, a 77 touch sensor 11m common to each key is used. Aftertouch sensor 411
A may be of any type as long as it can detect a key touch while the key is being pressed, for example, it may detect a key touch in response to any of the suppression speed, suppression depth, pressing force, strength, etc. There may be. The output signal of the aftertouch sensor IIA is applied to the initial touch sensitivity adjustment polyneem v8 via the booster 98, and is also applied to the low-pass filter 99. The output of the low-pass filter 99 is added to an aftertouch vibrato sensitivity adjustment volume v6 and an aftertouch level sensitivity adjustment volume v6. The low-pass filter 99 is for suppressing sudden fluctuations in the touch detection signal used for aftertouch control.

The aftertouch sensor 11m is commonly used for both initial touch detection and aftertouch detection. For example, if the touch detection signal inputted from the aftertouch sensor IIA 1fj is as shown in FIG. The peak value of this touch detection signal is detected within a distance of approximately 10 m5, and this peak value is held and used as the initial touch detection signal.

As described above, the sound generation starts after the initial sensing signal 18 falls (K after peak value detection is completed). Maku,
The aftertouch sensor output signal when peak value detection is in line 1 (-) (at the time of IS occurrence) is not used as the aftertouch detection signal, but the senna output signal at other times is used as the aftertouch detection signal. By doing so, there is no need to separately provide an initial touch sensor and an after touch sensor, which is economical and also simplifies the sensor device provided below the key.

The 98 analog voltages set or adjusted by polynemes v1 to v8 are converted into digital data using one MU/D converter 18. For this purpose, an analog voltage matrix receiver 9) 16 is provided.
M/V1 to V510 analog voltages are time-division multiplexed.
The signal is sent to the D converter 18. Further, a control and storage section 19 shown in FIG. 7 is provided in connection with the A/D converter 18,
The time-division A/D conversion operation in the A/D converter 18 and the demultiplexing operation of digital data obtained by this A/D conversion are controlled. The circuit configuration can be considerably simplified by this more A/D conversion operation.The control and storage s19 shown in FIG.
~Registers 101 to 10 as storage means corresponding to v8
Contains 8. (vl) to (v8) written near each register 101 to 108 are the corresponding polynyms v
1 to v8 are shown.

These registers 101 to 108 store digital data obtained by digitally converting the output and output voltages of the corresponding polynemes v1 to v8, respectively.

These registers 101 to 108Fi are shifted by system clock pulses φl, φsnow) 111JllH and 2
．． It consists of an 8 stage/1 bit circular shift register. The circled numbers in the profile of each stage of each register 101 to 108 indicate the 1st. The weights of data in each stage at the 9th, 17th, and δ time slots are shown as an example. The unit stock of the weight value in each register 101 to 108 is ra according to the nature of each control element, as noted near each output data display.
z'' (frequency), ``cent'' (cent value indicating the depth of pitch deviation), msJ (time), and dBJ' (level).These weightings are shown as an example only. First, it is not very important in terms of circuit operation, but it is useful in clarifying the relationship between the weight of each bit and the time slot when it is sent out as serial data.

The control and storage unit 19 in FIG. 7 includes each register 101 to
Multiplexer and demultiplex control circuits 111 to 118 are provided corresponding to 108. circuit 112
-117 are the same configurations, only the circuit 112 is shown in detail, and the circuits 116-117 are omitted. The multiplex and demultiplex control circuits 111 to 117
Fi, each register 101 to 1 corresponds to the time side multiplexing operation in the analog voltage multiplexer 16 (FIG. 6).
The digital data of 07 is multiplexed and sent to the A/D converter 18 (FIG. 6) for use in time-division A/D conversion operations, and the resulting digital data is sent to the A/D converter 18 (FIG. 6). It has the function of inputting and deleting data from and loading them into the corresponding registers 101-107. However, the control circuit 118 corresponding to the register 108 for storing initial touch detection data has a multiplex function (the data in the register 108 is transferred to the A/D converter 1
8).

In FIG. 6, the analog voltage multiplexer 160 control input has eight output signals H from the decoder 29 in FIG.
O to H7 are applied, and an initial sensing signal=S is applied from the OR circuit 90 in FIG. Bits B2 and 11 of the count value of the decoder 29 counter (FIG. 3).

The value of 9 is decoded and the value of 9 is output as signals HO to 7. Each of the signals He to H7 becomes @l'' in the order shown in FIG. Each signal HO to H7 makes two rounds in between.

The multiplexer 16 normally samples analog voltages of the polynemes V'l to v7 in sequence according to the signals H1 to H7 as shown in FIG. 9, multiplexes them, and outputs them.

When the initial sensing signal I8 is 11", sampling of v1 to v7 by the signals H1 to ■7 described above is prohibited, and the analog voltage from polyneem v8 for initial touch sensitivity adjustment is continuously selected and output. Multiplexer 11) The output voltage is supplied to the input l of the analog comparator 1100 in the M/D converter a.First, the overcurrent Om/
D conversion will be explained, and then A/D conversion of the initial touch detection signal will be explained.

System clock pulse φ1
．． Data register 100 consisting of an 8-stage/1-bit circular shift register whose shift is controlled by φ snow.
Contains. Normal mu/D in mu/D converter 18
The conversion operation is performed in a time-division manner corresponding to the time-division sampling of each analog voltage by the multiplexer 16.

Initially, digital data resulting from the previous M/D conversion is loaded into the data register 100. This previous data is converted into an analog voltage by a digital/analog conversion (hereinafter referred to as D/A conversion) circuit 119, and this is converted to an analog voltage by a comparator 1.
100 input A plus the analog voltage from multiplexer 16 and performs the A/]) conversion by counting up or down the contents of data register 100 depending on the result of this comparison.

Digital data resulting from the previous A/D conversion is taken into the data register 100 from one of the registers 101 to 1070 in FIG. 7 immediately before the sampling timing. As the rounding control signal, the signal N7.25T32 is sent from the AND circuit 120 in FIG. 3 to each control circuit 11 in FIG.
It is input to AND circuits 121, 122, and 125 within 1 to 117. In FIG. 3, the output of the AND circuit 42 and the timing signal 25 T 32 are applied to the seventh AND circuit 120 . The AND circuit 42 operates on the lower 3 bits of the count value of color/16, 103. N2. The condition is met when N1 is "111". This is each signal HO-H for sampling.
7 shows the last 1 key time.

Signal 25 T 32 is the connection @1'' of 8 time slots from 6th to 32nd time slot in l key time.
This is the result. Therefore, in the last 8 time slots of each signal HO to H7,
” becomes.

In FIG. 7, control circuits 111 to 117 are supplied with output signals HO to H7 from a decoder 29 (FIG. 3), and based on these signals HO to H7 and the signals N7 and 25T32, multiplex, Control multiplexes simultaneously. Each of the four control circuits 111 to 117 includes an AND circuit 124° 125 for multiplexing, an AND circuit 126° 127 for demultiplexing, and an AND circuit 12 for hold.
Contains 8,129. In the last 8 time slots of the sampling timing, the data stored in the register (one of 101 to 107) corresponding to the next sampling timing is selected via the multiplexing AND circuits 124 and 125, and the data is sent to the A/D. At the same time as the data is supplied to the data register 10m (Fig. 6) of the converter 18, the A/D converted data at the sampling timing is passed through the demultiplexing AND circuits 126 and 127 to correspond to the sampling timing. register (1
01 to 107). Such demultiplexing and multiplexing control for the registers 101 to 107 is performed at times other than the approximately 10 m5 waiting time for initial touch detection. For rounding, each AND circuit 121 in the control H paths 111 to 117
, 122, 123 are supplied with an inverted signal 1g of the initial sensing signal I8 from the inverter 130, and are enabled when xS is O''. is signal N7/5T
32 is commonly input. Each AND circuit 121.122
．． 12+! Signals HO, H1, and 12 are input separately to $, and the AND circuit 12! of each control circuit 116-117 is inputted separately.
Signals H3 to H7 are input to the same AND circuit as I, respectively.

When the signal 11G is @1'', as shown in FIG. 9, the analog voltage multiplexer 16 (FIG. 6) does not sample the voltage of any of the polygons v1 to v8. Therefore, at this time, the A/D converter 18, no MU/D conversion operation is performed.In the last 8 time slots of signal HO, signal N
7.25 When T32 becomes 11', AND circuit 121 (
The condition shown in FIG. 7) is satisfied, and @l'' is given from this AND circuit 121 to the AND circuit 124 and the OR circuit 161. Therefore, the output signal TiM of 1 which is subjected to the OR circuit is The signal H is generated as shown in the figure (a).
This is an enlarged view of the timing of the change from O to [1. Note that the outputs of AND circuits 122.12S, which are equivalent to the AND circuit 121 in each of the control circuits 111 to 117, are provided to other inputs of the OR circuit 161, respectively. Incidentally, in FIG. 10 and other timing charts, numbers such as "δ~ proverb" written in the pulse indicate the position of the time slot.

Serial 8-bit digital data output from the final stage of register 101 is applied to the other input of AND circuit 124. This serial digital data is sequentially arranged from the least significant bit (hereinafter referred to as L8B) to the most significant bit (hereinafter referred to as M8B) between the δth to 32nd time slots. AND circuit 124 is the first
(b) Lf - The 8-bit digital data stored in the register 101 by being enabled during the same 8 time slots as the signal TiM is sampled by the AND circuit 124 in synchronization with the signal Ti; It is applied to the OR circuit 162. The output ODD of the OR circuit 162 (
old digital data) is supplied to the A/D converter 18 in FIG.
is loaded into the data register 100 via. Therefore, when the next sampling signal H1 rises to 11'', the data in the data register 1001r and the mole register 101 (indicated by VBR) has been transferred.
OR circuit 132 (Fig. 7) K is each control circuit 111 to 11
The outputs of 7 multiplex AND circuits 124 and 125 are respectively applied. The data of each register 101 to 107 is input to VIR, VBD, KVBD, DYER (before DEL).
), 81M, 8BE, MUTL, and 8TRA, data register 1 is set at the beginning of each sampling timing.
The data output from 00 is as shown in FIG. 9(C). That is, as shown in FIG. 9), the digital conversion results of the analog voltages of each sampled polyneem v1 to v7 at the previous sampling timing are sent from the data register 100 corresponding to the current sampling timing of the same polyneme v1 to v7. Output.

On the other hand, the good signal Ti output from the OR circuit 161 in FIG.
MFi is applied to the A/D converter 18 in FIG. This signal tem M is inverted by an inverter 165, and the AND circuit 1
66 is rendered inoperable. The AND circuit 166 is for holding the data in the data register 100, and inhibits the holding of the register 100 by the signal TiMK when loading the old data ODD. Signal T i
M Fi 3rd grade j! 167 (flip-flop shift register) 167. This clip 70 knobs 167
loads the input signal with the timing signal 6y8, and the signal t
Switch the output in synchronization with y8. Therefore, as shown in FIG. 10(C), the output signal 7iMIFi of the first stage becomes @1'' between the first to eighth time slots of the rising edge of the signal Ml, and the The outputs are combined with the OR circuit 168 and the good signal T iMz 13 is the 10th
As shown in FIG. 3(d), the signal becomes @1'' between the 9th and 9th time slots immediately after the falling edge of the signal TjMl.

In FIG. 6, the data register 100 constitutes an 8-bit serial counter together with a 1-bit full adder 164. The latch circuit 169 is for latching the output of each notage (ie, count value) of the register 100 in parallel at the timing of the signal 1 y 88. Signal 1) '88 occurs at the 16th 9th. At the 17th and 6th time slots 4'--, the first
From stage to 8th stage, from MBll to L811t
The data is lined up in the fist 9, this is the latch circuit 139
latched to. JIIEIO diagram (e) As shown in K, at the 8 time slot of the rising edge of signal H1,
The contents of latch 1 169 indicate data VBR of register 101 (FIG. 7). The contents of this latch circuit 1119 change every eight time slots in accordance with changes in the count value (response in register 1000).

The output of the latch circuit 169 is given to the D/A conversion circuit 119 and converted into an analog voltage. The comparator 110 compares the inputs A and B, and when B≧m, that is, when the value of the analog voltage applied from the multiplexer 16 to the input IIK is the same as or greater than the value of the data in the data register 100, it outputs '12. Output. The output of this comparator 110 is given to a slow grinding flip-flop 140, and a signal 1y
8 and is output with a delay of 8 time slots. The output of this flip-flop 140 is in/(-141
The signal is inverted at , and applied to the AND circuit 142 for down counting. Further, the output of the flip-flop 140 is applied to an AND circuit 143 for amplifier counting at the time of initial touch detection. The AND circuit 144 is a normal A
This is for up-counting during /D conversion operation.

From the inverter 160 in FIG. 7 to the MU/D converter 1 in FIG.
8 is given an inverted signal Is of the initial sensing signal Is. This signal T1 is connected to the AND circuit 142 and 1
These circuits 142 are added to 44 during normal A/D conversion operation except when initial touch is detected.
, 144 are enabled. Signal I8 to inverter 14
The signal Is inverted at 5 is applied to an AND circuit 146, enabling this circuit 146 when detecting an initial touch.

During normal A/D conversion operation, the contents of the data register 100 are incremented by one count at the timing of the signal TjM1, regardless of the comparison result of the comparator 110. That is,
The signal TiMI and the signal 1y8 are input to the AND circuit 144, and the output of the AND circuit 144 becomes @l'' at the first time slot when the signal TiM1 rises. The output 11'' of the ant circuit 144 is an OR circuit. 146 to adder 1640 input cam. When the signal T i M 1 is @1'' and the 1! signal TiMt'i'''0', the output of the data register 100 is applied to the adder 1640 input B via the AND circuit 136 and the OR circuit 162S. At the timing of signal ly8, the least significant bit of data vBR loaded into register 100 is added to adder 1540 input BK. Therefore, the lowest pitch f--1'' is added.

If there is a carryout signal, @1'' is output from the carryout output C +1 after l time slot delay.
It is applied to input C1 via AND circuit 147. Ant by signal ly8 for rounding to prevent the carry-over signal from being added at the timing of the least significant bit.

The circuit 147 becomes inoperable and becomes 1.

In this way, the previous data VIRKI is added in the interval tMl shown in Fig. 1θ (f>).This addition result rVI
Latch circuit 169 while IR+IJ is in the next TiH2 section
(FIG. 10(e)).

TiH2 (D section in Fig. 10(f))
The comparator 110 compares the analog voltage (mu) of R+lJ with the current analog voltage (II) of the volume v1,
B≧A” is established and when mourning, add or subtract [V
IR+lJ is held in register 10G. On the other hand, 1B≧
When the 7 lip-flop 140 does not hold, that is, [A) BJ, 1 is subtracted from the data (VBR+1j. When jA>BJ, the output of the 7 lip-flop 140 is @0" and 69,
11'' is applied from the inverter 141 to the AND circuit 142.
A signal TiM2+3 is given from , and the interval TiM2
and TiH3 (see Fig. 1.theta. (f)). When the condition of the AND circuit 142 is satisfied in the interval TiM2, the output of the AND circuit 142 becomes @1'' during the interval riwz (during 8 time slots). to adder 1640 input 4 through register 1.
@l'' is added to all bits of the data IVBR+IJ of 00, and a de facto countdown of 1 is performed.

Therefore, the value of the data obtained in the register 100 by the operation in the interval TiM2 is rviIg+tJt, which is [VIR
(=VBR+t-t)J69, and this data is latched by the latch circuit 169 in the interval TiM3 (see FIG. 1.theta.(e)).

In section TiM3, data [VIIR
The comparator 110 compares +IJt or "vBR" with the current analog voltage of Poly&-AVI, and when "B≧m" is established, the current value rV I R+ of the register 100 is calculated without performing addition or subtraction. I J ma9 holds l'-VIIRJ. On the other hand, when "M>Il", the AND circuit 142 outputs @1" as described above, and 1 is subtracted from the data in the register 100. By this subtraction of 21H, the data in the register 100 becomes rvmg-1 (= vmg+l-
1-1) It becomes J.

When the interval TiM3 ends, the signal TiM2+3 falls 9.
, AND circuit 142 becomes inoperable.

Therefore, subsequent counting operations are stopped. In this way, the MU/D conversion operation is performed only during three periods TiM1 to TiM3 (24 time slots) at the rising edge of the sampling signal H1.

The value of data VBR (A
) and the setting value of polyname v1 sampled this time (
B), then l in the interval TiMl:
Due to the addition, the contents of the register 100 become [vni+IJ, so in the comparison in the interval TiM2, B)
is established, 1 is subtracted, and the contents of register 100 become “VB
R”. In the comparison in interval TiM3, A=B holds true, and no subtraction by 1 is performed. Therefore, in the end, the same data [V B RJ as the data register 100]
is held.

If the setting value (B) of the volume v1 sampled this time is larger than the value (A) of the data VBR obtained by the previous A/D conversion, the contents of the register 100 are changed to rvnR+IJ by adding 1 in the interval TiMl.
Therefore, in the electric ratio @ device 110, only either B=A or B)A holds true. Therefore, no subtraction is performed in the intervals TiM2 and TiN2, and finally [VBR+I
J is register 100K: held.

If the set value (B) of the sampled volume v1 this time is smaller than the value of the nine data VIR obtained by the previous Mu/D conversion (Mu), the sections TiM2 and TiN
At 2, Mu〉3 always stands.

Therefore, 1 subtraction is performed twice after 1 addition, and finally [VIIR-IJ is held in register 100.

As mentioned above, one sampling period (7131 m s
) is limited to +1. This is to prevent the analog setting values of volumes v1 to v7 from changing rapidly and responding to them as they are, causing unpleasant noises such as clicks. This is due to OII reasons, such as 19th, which prevents the analog setting value from suddenly changing temporarily due to noise, etc., and not reacting to this. The maximum change in digital data in a 14J sampling cycle is +1
In short, it is sufficient that smooth A/D conversion can be performed.

Nine, three sections T in one A/D conversion operation
iM1, TiN2. Although addition and subtraction are performed using TiN2, the noise cape helps prevent the digital data from fluctuating randomly when the output of the comparator 110 is unstable. For example, in section TiM2, B
In the case where ≧ is satisfied but not in the interval TiM3, the digital data does not ultimately change due to "+1" in the interval TiM1 and "-1" in the interval TiM3.

In addition, all the outputs of the latch circuit 139 are input to the nine AND circuit 1.
48 and Noah enclosure 149 (FIG. 6) are companions for detecting the maximum count value and the minimum count value, respectively. When the maximum count value is reached, the AND circuit 14S is activated by the output of the circuit 148.

144 and prohibits up-counting. When the minimum count value reaches 9, the AND circuit 142 is made inoperable by the 15 force of the Noah circuit 149, and down-counting is prohibited.

Theory when sampling signal [1 is generated v! A.K.
Returning, after the end of section TiM3, the digital data that is the M/D conversion result is sent to the data register 100 via the AND circuit 166, the OR circuit, the adder 1640, and the data register 100.
It is cycled and held.

The data in this register 100 is supplied as any digital data NDD to demultiplexing AND paths 126 and 127 of each control circuit 111 to 117 in FIG. When the signal H1 is @l'', the AND circuit 122 of the control circuit 111 can operate, but when the signal N7
During "0", the condition is not satisfied, and this AND circuit 122
The output of the AND circuit 122 is inverted by the O'' inverter 150 and applied to the AND circuit 126 for holding. Register 1010 data vii1i OAND circuit 126 and OR1 path 15
1 and held in circulation.

In the last 8 time slots of signal H1, signal N7.
25 T When 32 becomes 11'm, AND circuit -22
The condition is satisfied, and this AND1 path 122 also gives @1'' to the AND circuit 126. At the same time, the AND circuit 12
The output "l" of 2 is the AND circuit 181 for multiplexing of the control 1 circuit 112 corresponding to the next sampling signal H2.
25 and is also applied to the OR circuit 131.

In the control circuit 111, the hold AND circuit 128 becomes inoperable due to the output @1'' of the AND circuit 122.
AND circuit 126 becomes operational. Therefore, signal H1
At the timing of , new digital data NDD\ indicating the setting value of the polyneme V1 that has been A/D converted is selected by the AND circuit 126, and is loaded into the register 01 via the OR circuit 151. AND circuit 122
outputs the function "1''" from the 5th to the 32nd time slot, and during this time, the data NDD output from the data register 00 (Figure 6) is exactly 8 bits from the lower bit to the most significant bit serially. It is lined up at number lI. Therefore, #! Between the 25th time slot and the 32nd time slot, new digital data NDD is stored in register 01.
The weight of each stage of register 01 in the first time slot is 6 (as shown in the figure, the first stage is the highest pitch) (a Hz).
65, and as the stages are completed, it moves to the lower bits, and the eighth stage is the lowest bit (-B→h).

On the other hand, the signal TiM is output from the OR circuit 161 in response to the output @l'' of the idle circuit 122, and the AND circuit 1
25 and the OR circuit 132, the data VID of the register 02 is converted to A as the old digital data ODD.
/D converter 18 (FIG. 6) K is provided. Then, when the numbering signal is switched to Hz, MU/D conversion regarding polyneme v2 is performed in the same procedure as described above.

Below, control i paths 112 to 11 correspond to signals H2 to H7.
7 operates in the same manner as described above, and Mu/D conversion regarding each volume V1 to V7 is sequentially performed. In this way, each register 01~107KFi, each lsuz AV1~V70
Digital data corresponding to the outputs are respectively stored.

The reason why register 04 corresponding to delay vibrato (volume V4) has two data displays, DVIR and DEL, is because volume v4 is used both for setting the start time of delay vibrato and for setting the slope of the envelope of delay vibrato depth change. This rounding function is also used for . D.Y.
ER is delay vibrato envelope plate data for setting the speed of temporal change in depth in the delay vibrato, and its weight is shown below in each stage block of register 04.

The unit of this weight is (Hz), and the envelope change rate is converted into a peripheral fluid number and expressed as a nine speed. That is, the time from the start to the end of the envelope corresponds to the τ period of the frequency display. DEL is delay vibrato start time data 69, and its weight is shown above in each stage block of register 04. Of course, these two data DYER and D do not have truth values, but they appear to have different weights on the user side.

Slur Speed (Polyneem V5) fL) [The reason why there are two ways to display the data in the register 105, 81M and 8-winged, is because the 8-bit data is divided into a mantissa and an exponent for rounding to ensure a wide dynamic range. This is the rounding to use. The least significant bit is not used, and the lower 2nd to 5th bits are used as the mantissa part M1. M2. Mru. M4 and top 3
Bit as index smet, Ii2,1! + 8RM
is a data display of the slur rate mantissa part, and 51R1 is a data display of the slur rate exponent part.

The nine initial sensing signals 18 output from the OR circuit 90 of FIG. 4 are input to the delay flip-flop 152 of FIG. The input signal is loaded by the 2R delay 7-rig 70-tub 152Fi signal 6y8, and the output state is switched in response to the signal tygK. delay arrival 7
The output of the first stage of the 0 tube 152 is the AND circuit 156
and is inverted by an inverter 155 and applied to an AND circuit 154. The output of the second stage is AND circuit 1
54, is inverted by inverter 130, and is applied to AND circuit 156. The outputs of the inverters 1 and 30 are applied as a signal T1 to the M/D converter 118 in FIG. ?, and the AND circuit 154#' outputs a pulse with a width of 8 time slots in response to the rising Yj of the polarized signal I8."The outputs of the AND circuits 156 and 154 are added to the -OR circuit 131, and the signal T
+M to the MU/D converter 18 in FIG. FIG. 11 shows the states of signals TsM and 11 generated in response to signal Is.

In Figure 6, the signal! In response to the rising edge of signal Ti
AND1 path 1 between 8 time slots where M becomes @l''
66 is disabled and all bits of data register 100 are cleared to @0'', signal 1j is “0”.
As a result, each control circuit 111 to 117 in FIG.
is disabled and each register 101-107 holds its stored data in rotation. And the AND circuit 1 in Fig. 6
42 and 144 are disabled and AND circuit 146 is enabled. AND circuit 146 is enabled and in the first 8 time slots, signal TiM is delayed by 8 time slots, good signal TiM1 is turned off at 11', and inverter 1
The operation of the AND circuit 14s is inhibited by the output @0'' of the signal 56. This is to wait for the state of each signal to become stable at 9 o'clock when the signal 8 rises, but this process does not need to be performed in particular. The signal 1y8 and the output of the delay 7-lip 70-tub 140 are added to the other inputs of the AND circuit 146. Therefore, if "B≧m" is established in the comparator 110, the AND circuit is activated at the timing of the signal 1y8. 14 Rukara@
l” is output and sent to the adder 164 via the OR1 path 146.
given to the incoming cam. The timing of this signal 1y8 is the timing of the least significant bit of the data in the data register 100. Therefore, every time one pulse is given from the AND1 path 143 at the timing of the signal 1y8, (
Approximately 4 μIIK:) The contents of the data register 100 are counted up by 1. As described above, while the initial sensing signal 18 is being generated, the multiplexer 16 continues to select the analog voltage of the polyneem V8. Therefore, the sensitivity is adjusted with the volume v8, and the friend touch detection signal is input to the comparator 1100.
given exclusively to

Since the data register 100 is initially cleared to all @0'', "B≧A" is initially established in the comparator 110. Each time the signal ly& is generated, the count in the register 1000 is rapidly counted up until the value of the data register 100 matches the value of the touch detection signal. When the count value of the data register 1000 matches the value of the touch detection signal, [B=AJ is established in the comparator 110. Based on this, the contents of the register 100 are further incremented by one count, and then "1<um" is established in the comparator 110, the AND circuit 146 is disabled, and counting is stopped. Thereafter, even if the level of the touch detection signal goes down, the data register 100 is not counted down, so the peak value is held. If the touch detection signal becomes larger than the value of the data register 100, the comparator 110 establishes "B≧m" and performs an additional count-up. Thus, the initial sensing signal! Digital data corresponding to the peak value of the touch detection signal of the leap where S is generated is stored in data register 1.
It is held at 00. The peak value data held in the data register 100 is transmitted to the AND circuit 157 in the control circuit 118 in FIG. 7 via the data NDD line.
given to.

When the initial sensing signal 1B falls after approximately IQ m s has elapsed from the start of the key press, the AND circuit 1 in FIG.
The output of 54 is in the 5th to 8th time slots) Kfj1 period and becomes @1'' for 8 time slots.

Output 11 of this AND circuit 154 AND circuit 158
given to. The other input of the AND circuit 158 includes a fourth
The output XKQ& of the 7 lip-flop XKQ shown in the figure is applied via a 70-stage delay slip 159. This delay arrival time is 70 times 159 is delay time 7 times 70 times 15 times.
This is a rounded signal that is synchronized with the 20 output timing. The AND circuit 158 outputs "1" for eight time slots on the condition that some key is pressed (XKQ8 is 11") at the end of the initial touch detection time.

The output 11'' of the AND circuit 158 enables the AND circuit 157 to operate, passing the peak value data (JDD) of the touch detection signal held in the data register 100' (FIG. 6), and turning on the OR circuit 160. Load the register 108 via the AND circuit 15.
The peak value data held in the data register 100 is cleared by the signal 'rtMK applied to the inverter 135 in FIG. Register 108 (Fig. 7) K during 8 time slots of 61''
When the loading of the corresponding peak value data is completed and the output of the AND circuit 154 falls to @0'', the AND circuit 15
7 becomes operable. The peak value data of the nine touch detection signals loaded into the register 108 is subsequently held via the AND circuit 161. In this way, the 1'' initial touch detection data is held in the register 108.

It should be noted that the data displayed in the register 108 is 2, PI and ITL.
The reason for this is that the same initial touch detection data is used for both the attack pitch controller, initial touch level controller, and Kl. PI is attack pitch initial value setting data, and its weight is written above in each stage block of the register 108. The lower 3 bits are truncated, and the upper 5 bits are approximately 1.
It corresponds to pitch deviations of 2 cents to about 19 cents.

ITL#'i is initial touch level control data.

Of the nine data stored in each register 101 to 108 in FIG. 7, pitch control [1% data, vibrato rate data VIB, vibrato depth data V
BD, aftertouch vibrato depth data [VII
D. Delay vibrato envelope rate data DY
ER, delay vibrato start time data DEL, slur rate mantissa data 111tM, slur rate exponent data RE.

The attack pitch initial value setting data API is supplied to the effect applying circuit 20 (FIG. 2). Level control related data, i.e. aftertouch level control data A
TL, sustain rate data fi STR, initial touch level control data ■TL is musical tone signal generator 2
1 (Figure 2).

In the effect adding circuit 20, based on the attack pitch start signal S or slur start signal 8S given from the single note key assigner 14A, a good operation for forming the modulation signal VAL or musical tone frequency information 8KC to which a slur effect is added is formed. start the operation. A detailed explanation of the effect imparting circuit 20 is omitted, but its outline is as follows.
It is.

When the attack pitch start signal S is given,
A modulation signal VAL for the attack pitch is formed in accordance with the attack pitch initial value setting data API and the control datums ps, PR, and APF:R given from the attack pitch data ROM 22.

Then, if delay vibrato is selected,
A modulation signal VAL for delay vibrato is formed according to the delay vibrato start time data DEL and delay vibrato envelope data DVER. After the delay vibrato ends (immediately after the attack pitch ends when the delay vibrato is not selected), a rounded modulation signal VAL of normal vibrato and aftertouch vibrato is formed. The modulation signal VAL for normal vibrato is formed according to the vibrato rate data V18 and vibrato depth data VBD. The modulation signal VMUL for aftertouch vibrato is the above data VBR and aftertouch vibrato depth data KVBD.
formed according to. If the normal rubibrato and the aftertouch visit are selected at the same time, the frequency of the modulation signal VAl is determined by the data VIIR, and the amplitude) is determined by both the data VIID and KVBD. When the slur start signal S8 is given, the value of the frequency information @SKC is changed from the value corresponding to one note to the new note according to the slur rate data S, IRE, and the key code MKC given from the single note key assigner 14A. Control is performed to gradually shift to a value corresponding to . After the slur control is completed, variable # signals VAL for delay vibrato, normal vibrato, and aftertouch vibrato are generated in the same manner as described above.

A detailed explanation of the musical tone signal generating section 21 will also be omitted, but its outline is as follows. In the single tone mode, a musical tone signal is formed based on the frequency information @5KC (corresponding to key code MKC) given from the effect adding path 20. In the multitone mode, a musical tone signal is formed based on the key code PKC given from the multitone key assigner 14B. At the same time, controlling the pitch of the musical tone signal formed therein according to the modulation signal VAL, and controlling the tone of the musical tone signal according to the aftertouch level control data ATL and the initial touch level control data ITL; , and controls the ametaining time of the amplitude envelope of the musical tone signal according to the sustain rate data STH.

In addition, in the A/D converter 18 of FIG. 6, the amount of data change in one sampling period is limited to +11 in order to prevent sudden changes in data regarding A/D changes related to volumes 1 to v7. . However, it is also possible to limit the data change amount in one sampling period + C to within ±N (N is a predetermined number of 2 or more), or to not limit the data change amount at all. It may be determined within a range that can be tolerated depending on the nature. In the latter case, the output of the delay flip-flop 140 is input to the AND circuit 144 for up-counting in FIG.
Just remove it. In the former case, after changing the input combination of the AND circuits 142 and 144 as described above, the number of connected delay flip-flops 167 (number of shift stages) is increased corresponding to N, and from each stage T
It is sufficient to enable the AND circuits 142 and 144 only while the delayed iM signal is being output.

Although a serial processing type A/D conversion section 17 is shown in FIGS. 6 and 7, a parallel processing type A/D conversion section 17 can also be configured in the same manner as in these embodiments.

Further, time division sampling in the analog voltage multiplexer 16 may be controlled by a microcomputer program. In that case, the time-division sampling timing does not always have to be in a regular order, and may be irregular or discontinuous depending on the processing convenience of the microcomputer. If the sampling period is irregular, it is also possible to automatically change the limit value of the amount of change in digital data according to each sampling period using a microcomputer program.

As explained above, according to the present invention, multiple types of
When variably setting digital data, a plurality of analog signal setting means are provided, and these analog setting values are time-division multiplexed and converted into digital data by one analog/digital conversion means. The configuration of the manual setting means is simplified, and the configuration of the analog/digital conversion means is also simplified, making it possible to achieve savings in manufacturing cost, number of wires, installation space, and circuit space. Also, during analog/digital conversion, 1
Since the amount of change in the digital data during the sampling period is limited, rapid changes in the digital data are suppressed, and a favorable effect is exhibited when applied to a certain ridge or the like.

[Brief explanation of the drawing]

Fig. 1 is a block diagram showing one embodiment of the present invention, Fig. 2 is a block diagram showing the entire configuration of an electronic musical instrument in an embodiment in which the invention is applied to a t-i child musical instrument, and Fig. 3 is a block diagram showing the entire configuration of an electronic musical instrument. A circuit diagram showing a detailed example of a key press detection unit and a counter, FIG.
FIG. 5 is a timing chart showing an example of timing signals used in each part of the second key assigner; FIG. 6 is the touch sensor shown in FIG. 2, a group of various effect setting operators, Analog voltage multiplexer and A
, ' A circuit diagram showing a detailed example of the D converter part, FIG. 7 is a circuit diagram showing a detailed example of the control and storage section in the A/D converter section of FIG. 2, and FIG. A signal waveform diagram to show that both initial touch and aftertouch are detected based on the output of the touch sensor, and Figure 9 shows the time division state for analog/digital conversion by the circuits in Figures 6 and 7. Timing chart shown, No. 10
The figure is a timing chart showing an example of the normal operation of the A/Di converter in Figure 6 (other than when initial touch is detected), and Figure 11 is a timing chart showing the main operations during initial touch detection in Figures 6 and 7. 5 is a timing chart showing a signal generation state. VRI to VRne V1 to V8-7 Volume for analog pressure setting, 200.16--Analog voltage multiplexer, 202.18-A/D converter,
203-1 to 205-nttol to 108...Memory or register corresponding to analog voltage setting volume, 204, 111 to 117...Multiplexer and demultiplex control circuit, 205, 10
0...Data register, 206,119...D/
A conversion circuit, 207, 110... Comparator, 208...
・Data register control circuit. Patent applicant Nippon Musical Instruments Manufacturing Co., Ltd.

Claims (1)

[Claims] 1. A plurality of analog signal setting means, an analog signal multiplexing means for time-divisionally sampling and multiplexing the analog signals set by each of the analog signal setting means, and each of the analog signal settings. A plurality of storage means are provided corresponding to the means, each storing digital data of a value corresponding to the analog signal set in each storage means, and the analog signal outputted from the analog signal multiplexing means is digitalized. An analog/digital conversion means for converting into data, and an operation of the analog/digital conversion means is controlled in synchronization with time-division sampling in the analog signal multiplexing means, and the output digital data of the analog/digital conversion means is A digital data setting device comprising: control means for storing data in one of the storage means in accordance with time-division sampling timing. 2. The control means is a first control means that selects and multiplexes the corresponding storage data of the storage means at the beginning of each sampling timing or immediately before that sampling timing, and sends the multiplexed data to the analog/digital conversion means. a second control means for providing a control signal to the analog/digital conversion means in synchronization with the data sending timing by the first control means; and a third control means for distributing and storing the digital data to the storage means corresponding to the sampling timing, and the analog/digital conversion means distributes and stores the digital data provided by the first control means. a register for storing the data, a digital/analog converter circuit for converting the data stored in the register into an analog signal, and an output signal from the digital/analog conversion path and an analog signal output from the analog signal multiplexing means. A control operation is started based on the comparator to be compared and the control signal given from the second control means, and the value of the digital data stored in the register is increased or decreased depending on the output of the comparator. The digital data setting device according to claim 1, further comprising a control circuit for controlling the digital data setting device. 6. Each of the storage means outputs its stored data serially, the digital data sent to the analog/digital conversion means via the first control means is serialized, and the register is The stored data is serially outputted as an output of the analog/digital conversion means, and the digital data distributed to the storage means via the third control means is serialized. The digital data setting device according to item 2. 4. The digital data setting device according to any one of claims 1 to 3, wherein the analog signal setting means comprises an analog pressure setting period volume. 5. A plurality of analog signal setting means, an analog signal multiplexing means for sampling and multiplexing the analog signals set by each of the analog signal setting means in a time division manner, and providing corresponding to each of the analog signal setting means. a plurality of storage means for respectively storing digital data of a value corresponding to the analog signal set therein; and an analog/digital storage means for converting the analog signal outputted from the analog signal multiplexing means into digital data. a conversion means; a first control means for storing output digital data of the analog/digital conversion means in one of the storage means in correspondence with the time-division sampling timing; a second control means for controlling the analog/digital conversion means 41-j so that the amount of change in the digital data to be obtained this time in accordance with the storage means for the digital data at the previous sampling timing is within a predetermined value; A digital data setting device comprising: 6. The analog/digital conversion means includes a register to which data stored in the storage means corresponding to the sampling timing is transferred at the beginning of each sampling timing or just before that sampling timing, and a digital/digital converter that converts the data stored in this register into an analog/digital signal. analog conversion circuit,
a comparator that compares the output signal of the digital/analog conversion circuit with the analog signal output from the analog signal multiplexing means; and a comparator that increases the value of the digital data stored in the register according to the output of the comparator. or an arithmetic circuit that decreases, and the second control means controls the arithmetic circuit to limit the maximum increase amount or decrease amount in one sampling timing to a predetermined value. The digital data setting device according to item 5. Z The second control means includes a first step of increasing the contents of the register by a predetermined value regardless of the output of the comparator, and then determining that the output of the comparator is larger than the contents of the register. A second step in which the contents of the register are decreased by a predetermined value on the condition that the contents of the register are indicated, and a third step in which the same control as in the second step is performed are sequentially executed at one sampling timing. A digital data setting device according to claim 6.