JPS5868942A - Die bonding device - Google Patents
Die bonding deviceInfo
- Publication number
- JPS5868942A JPS5868942A JP56168431A JP16843181A JPS5868942A JP S5868942 A JPS5868942 A JP S5868942A JP 56168431 A JP56168431 A JP 56168431A JP 16843181 A JP16843181 A JP 16843181A JP S5868942 A JPS5868942 A JP S5868942A
- Authority
- JP
- Japan
- Prior art keywords
- die
- semiconductor chip
- collet
- circuit board
- bonding
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
Classifications
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
- H10W72/00—Interconnections or connectors in packages
- H10W72/071—Connecting or disconnecting
- H10W72/073—Connecting or disconnecting of die-attach connectors
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
- H10W70/00—Package substrates; Interposers; Redistribution layers [RDL]
- H10W70/60—Insulating or insulated package substrates; Interposers; Redistribution layers
- H10W70/67—Insulating or insulated package substrates; Interposers; Redistribution layers characterised by their insulating layers or insulating parts
- H10W70/68—Shapes or dispositions thereof
- H10W70/682—Shapes or dispositions thereof comprising holes having chips therein
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
- H10W72/00—Interconnections or connectors in packages
- H10W72/071—Connecting or disconnecting
- H10W72/0711—Apparatus therefor
- H10W72/07141—Means for applying energy, e.g. ovens or lasers
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
- H10W72/00—Interconnections or connectors in packages
- H10W72/071—Connecting or disconnecting
- H10W72/073—Connecting or disconnecting of die-attach connectors
- H10W72/07331—Connecting techniques
- H10W72/07336—Soldering or alloying
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
- H10W72/00—Interconnections or connectors in packages
- H10W72/071—Connecting or disconnecting
- H10W72/073—Connecting or disconnecting of die-attach connectors
- H10W72/07331—Connecting techniques
- H10W72/07337—Connecting techniques using a polymer adhesive, e.g. an adhesive based on silicone or epoxy
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
- H10W72/00—Interconnections or connectors in packages
- H10W72/30—Die-attach connectors
- H10W72/351—Materials of die-attach connectors
- H10W72/352—Materials of die-attach connectors comprising metals or metalloids, e.g. solders
Abstract
(57)【要約】本公報は電子出願前の出願データであるた
め要約のデータは記録されません。(57) [Summary] This bulletin contains application data before electronic filing, so abstract data is not recorded.
Description
【発明の詳細な説明】
不発明は、半導体チップケ回路基板にダイボンドする際
、半導体チップを損傷させずに回路基板に接合固定でキ
ろグイボンド装置?提供′1′″ゐことを目的とする。[Detailed Description of the Invention] The uninvention is a die-bonding device that can bond and fix semiconductor chips to a circuit board without damaging them when die-bonding semiconductor chips to a circuit board. The purpose is to provide '1'''.
周知のように拡散、フォトエッチ工程が終了したシリコ
ンウェハは、機能単位ごとに分割さn半に固定し、いわ
ゆるダイボンド装置う。従来、前記ダイボンドに、ダイ
しレットに半導体チップヶ真空吸引しグイコレットに機
械的加重ケ加え、(ロ)路基板に圧着、ムu −Si合
金又は接着性樹脂によV接合固定するものであった。As is well known, the silicon wafer that has undergone the diffusion and photoetching processes is divided into functional units and fixed into n and a half pieces using a so-called die bonding apparatus. Conventionally, the semiconductor chip was vacuum-suctioned to the die-let, mechanical load was applied to the die-let, and (2) the semiconductor chip was crimped to the road board and fixed by V-bonding using Mu-Si alloy or adhesive resin. .
しかし、この方法に工ゐと第1図(ム)に示すダイコレ
ット1に半導体チップ2ケ真空吸引した前記ダイコレッ
ト自体に圧力?加え、回路基板3に半導体チップ2′l
t圧着し、圧カケ加えた′!1前後方向瓢、左右方回す
にダイコレット1ヶ動かさねばならない。However, there is a problem with this method and there is no pressure on the die collet itself when two semiconductor chips are vacuum-suctioned into the die collet 1 shown in FIG. In addition, a semiconductor chip 2'l is mounted on the circuit board 3.
I crimped it and added pressure! One die collet must be moved to turn the gourd in the front-back direction or left-right direction.
この時、同図(B)に示す様に、ダイボンド時において
半導体チップ2のエッヂ4にクラック6が発生する。こ
のクラック6はグイコレット1が半導体チップ2のエッ
ヂ4に接触した[L加圧した状態で第1図(ム)に示す
とおりダイコレット1ヶ前後方向a、右左方向すに動か
すため半導体チップ2のエッヂ4に無理な刀が加わるた
め発生するものである。At this time, as shown in FIG. 2B, a crack 6 occurs at the edge 4 of the semiconductor chip 2 during die bonding. This crack 6 is caused by the die collet 1 coming into contact with the edge 4 of the semiconductor chip 2 [L] As shown in FIG. This occurs because an unreasonable sword is added to Edge 4.
本発明は、前記従来の欠点ケ除去するものであり、半導
体チップケ回路基板にダイボンドする際、前記ダイコレ
クトの中空部に加圧気体ケ導入し、−この圧力により前
記半導体チップ2回路基板に押しつけ、ダイコレットが
前記半導体チップのエッヂに接触する事なくダイボンド
出来るダイボンド装置ケ提供丁/)ものである。The present invention eliminates the drawbacks of the conventional method, and when die-bonding semiconductor chips to a circuit board, pressurized gas is introduced into the hollow part of the die collect, and the semiconductor chips are pressed against the circuit board by this pressure. , a die bonding device is provided which can perform die bonding without the die collet coming into contact with the edge of the semiconductor chip.
第2図は、本発明の一実施例におけるダイボンド装置の
構@?示す図である。第2図に示すように、同装置はダ
イコレット1に、半導体チップケ吸引して、回路基板の
ダイボンドする箇所まで移動させるための真空装置系統
16と、ダイボンド時に半導体チップに圧カケ加え回路
基板に接合固定するた、めの加圧気体供給装置系統17
と?備えており、そfぞn開閉栓14,15及び圧力計
13ケ装備している。ダイコレット1への半導体チップ
の吸引、脱着は、真空開閉栓1.4の開閉側(財)にニ
ー正性い・ダイボッド時における半導体チップの回路基
板への加圧は、カロ圧気体開閉栓16の制御によって行
う。12にダイボンド時加圧気体が冷態であった場合に
用いらnる回路基板の冷却を防ぐ加熱ヒータである。FIG. 2 shows the structure of a die bonding device in an embodiment of the present invention. FIG. As shown in FIG. 2, the device includes a die collet 1, a vacuum system 16 for sucking up semiconductor chips and moving them to the die-bonding location on the circuit board, and a vacuum system 16 for applying pressure to the semiconductor chips and applying pressure to the circuit board during die-bonding. Pressurized gas supply system 17 for joining and fixing
and? It is equipped with valves 14, 15 and 13 pressure gauges. The suction and removal of the semiconductor chip to the die collet 1 is done by the opening/closing side of the vacuum valve 1.4. Pressurization of the semiconductor chip onto the circuit board during die botting is performed using the Calorie pressure gas valve. 16 control. 12 is a heater that is used to prevent cooling of the circuit board when the pressurized gas is in a cold state during die bonding.
次に第3図ケ用いて、前記実施例におけるダイボンド装
置の動作r説明する。Next, referring to FIG. 3, the operation of the die bonding apparatus in the above embodiment will be explained.
1ず第3図(ム)において、真空開閉栓14ケ開けるこ
とにエリあらかじめ分割さnた半導体チップ2ケダイコ
レツト1に真空吸引させ、この状態で半導体チップ2ヶ
回路基板3上に位置させる。次に第3図(B)において
2、ダイコレット1ケ降下させ1:半導体チップ2の下
面ケ回路基板3に接触させ、真空開閉栓14會閉じる。First, in FIG. 3(m), 14 vacuum stopcocks are opened to apply vacuum to the 2-piece semiconductor chip collector 1, which has been divided in advance, and in this state, the 2 semiconductor chips are placed on the circuit board 3. Next, in FIG. 3(B), one die collet is lowered to bring the lower surface of the semiconductor chip 2 into contact with the circuit board 3, and the vacuum stopper 14 is closed.
次に第3図(C) において、ダイコレット1ヶ半導体
チップ2の厚さの1/2程度上向へ垂直に移動させる。Next, in FIG. 3(C), one die collet is vertically moved upward by about 1/2 of the thickness of the semiconductor chip 2.
前記ダイコレット1の上方への移動が完了した後、加圧
気体開閉栓157開き、ダイコレットの中空部7に加圧
空気ケ導入させると共に、グイコレット12前後方回a
、左右すに動かし半導体チップ2ケ回路基板3次に第3
図中)において、半導体チップ2が接着樹脂又に五u−
8i合金6で回路基板3に接合固定さrL、b工程が完
了丁nは半導体テップ2ケ(ロ)路基板3上に残して、
ダイコレット1に引き上げたあと加圧気体開閉栓r閉じ
てグイボンド?完了丁ゐ。After the upward movement of the die collet 1 is completed, the pressurized gas opening/closing valve 157 is opened to introduce pressurized air into the hollow part 7 of the die collet, and the die collet 12 front and rear turns a
, move 2 semiconductor chips left and right, 3 circuit boards, 3
(in the figure), the semiconductor chip 2 is bonded with adhesive resin or
The 8i alloy 6 is bonded and fixed to the circuit board 3. Steps R and B are completed, and two semiconductor chips are left on the circuit board 3.
After pulling up to die collet 1, close the pressurized gas valve r and use Guibond? Completed.
次に第4図rもとにして半導体チノプケ回路基板に固T
する際のダイコレットと半導体チップとの位置関係につ
いてさらに詳細にのべる。Next, fix the T to the semiconductor circuit board based on Figure 4r.
The positional relationship between the die collet and the semiconductor chip during this process will be described in more detail.
枦1図におい′て、ダイコレット1と半導体チップ2の
エッヂ4との間に少なくとも、前記夕”イコレソト1と
エッヂ4が接しない間隔例えば、半導体チップ2の厚さ
2分の1程度の間隔D2設ける。In Figure 1, there is at least an interval between the die collet 1 and the edge 4 of the semiconductor chip 2 such that the die collet 1 and the edge 4 do not come into contact with each other, for example, an interval of about half the thickness of the semiconductor chip 2. Provide D2.
この係に半導体チップ2とダイコレット1との間に間隔
Dy設けておき、加圧気体ケ導入し、グイコレット1r
前後、左右に勤かし+導体チン12r回路基板3に接合
固定させるものである。この方法であnば、半導体チッ
プ2はダイコレット1に対し完全に半導体チップのエツ
ジが非−触の状態で接合固定できるものである。つ壕り
、ダイコレット1の中空部に加圧気体ケ導入し半導体チ
ップ2ケ(ロ)路基板3に圧着グイボンド丁ゐ際、ダイ
コレクト1と半導体チップとにおのおのの壁面5でしか
接触せず半導体チップのエツジは無接触の状態である。In this connection, a gap Dy is provided between the semiconductor chip 2 and the die collet 1, and pressurized gas is introduced into the die collet 1r.
It is connected and fixed to the circuit board 3 by working + conductor chins 12r on the front and rear, left and right sides. With this method, the semiconductor chip 2 can be bonded and fixed to the die collet 1 without the edges of the semiconductor chip completely touching. Pressurized gas is introduced into the hollow part of the die collet 1, and the two semiconductor chips are crimped onto the circuit board 3. When the bond is pressed, the die collet 1 and the semiconductor chips are brought into contact only at their respective wall surfaces 5. First, the edges of the semiconductor chip are in a non-contact state.
従がって、半導体ペレットのエツジの損傷?防止できる
。Therefore, damage to the edges of the semiconductor pellet? It can be prevented.
このように前記実施例のダイボンド装置によfば、半導
体チップのエッヂがダイコレットと強く当接子^ことが
ないため半導体チップのクラックr防止できる。
゛
次に本発明の他の実施例におけるダイボンド装置につい
て説明する。As described above, according to the die bonding apparatus of the above embodiment, cracks in the semiconductor chip can be prevented since the edge of the semiconductor chip does not come into strong contact with the die collet.
゛Next, a die bonding apparatus in another embodiment of the present invention will be explained.
ムu −Si共晶合金法によるダイボンドでに、あらか
じめ加熱さnた回路基板に半導体チソグr接合固足丁ゐ
ことはすでに公知である。しかし、ダイボンド時加圧気
体が冷態の場合、回路基板が冷却さn、ダイボンド条件
が不安定となり、こnら會防ぐべに第6図においてダイ
コレット1の上部の管内部に発熱体12ケ設置し、そこ
ケ通過″f′ゐ加圧気体全直接加熱さす構成としている
。It is already known that semiconductor chisels can be firmly bonded to a preheated circuit board by die bonding using the mu-Si eutectic alloy method. However, if the pressurized gas is cold during die bonding, the circuit board will be cooled and the die bonding conditions will become unstable. The pressurized gas "f'" passing therethrough is directly heated.
第6図は本発明のダイボンド装置のさらに他の実施例ケ
示″′jもので、陶器製管に発熱体12r内装し、さら
に管内部に放熱翼18ケ設は加「気体r加熱する構成と
している。FIG. 6 shows still another embodiment of the die bonding device of the present invention, in which a ceramic tube is equipped with a heating element 12r, and 18 heat dissipating blades are installed inside the tube to heat a gas. It is said that
さらに他の実施例として前記の工すにダイコレット1の
上部の管内部に発熱体ケ設置せずに、夕゛イコレットに
加圧気体ケ導入する管の途中に加圧気体ケ高温に丁ゐ手
段?設け、この高温の気体rダイコレット1に導入して
も良い。As another example, in the above-described process, a heating element is not installed inside the tube above the die collet 1, but the pressurized gas is heated to a high temperature in the middle of the tube that introduces the pressurized gas into the die collet. means? Alternatively, the high temperature gas may be introduced into the die collet 1.
、このような不発型の実施例におけるダイボンド装置に
工nば、ムu−3i共晶合金法では、夕”イコレノトの
中空により、加熱さnた加圧気体ケ導入出来、グイボン
ド時に、回路基板の温度が低下し、接合条件ケ変動せし
め接合不良ケ発生させることがない。つ1v、半導体チ
ップ、ダイコレットによって、回路基板から逃げる熱ケ
加熱さfした加圧気体で供−給丁ゐことができ、安定し
たダイボンドが実施できる。又、樹脂接着法においても
加熱さfした加圧気体r導入丁ゐことによジ接着後の樹
脂の硬化ダイボンド時に実施できる。したがって工程ケ
短縮できる。なお、加圧気体はN2.ムr等の不活性ガ
スヶ用いることKより半導体チップ表面1の酸化ケ防止
し、塵等ケ除去丁ゐことができる。If the die bonding equipment in such a non-explosion type embodiment is constructed, in the Mu-3i eutectic alloy method, heated pressurized gas can be introduced through the hollow space of the die, and the circuit board can be bonded during the bonding process. The temperature of the circuit board decreases, and the bonding conditions do not change and bonding failures do not occur.The heat escaping from the circuit board due to the semiconductor chip and die collet is supplied with heated pressurized gas. In addition, in the resin bonding method, by introducing heated pressurized gas, it can be carried out during die bonding when the resin is cured after bonding.Therefore, the process can be shortened. The pressurized gas may be an inert gas such as N2.By using an inert gas, it is possible to prevent oxidation of the semiconductor chip surface 1 and remove dust and the like.
来のダイコレットによるダイボンドと同様、ダイコレッ
トにエリ半導体チップに機械的加重ケ加え、(ロ)路基
板に圧着、グイボンドする事も可能である。Similar to the conventional die bonding using a die collet, it is also possible to apply a mechanical load to the semiconductor chip using the die collet and press and bond it to the circuit board.
以上の実施例説明により明ら刀・なように、従来はダイ
コレットが半導体チップ表面に接し、わずかでも傾斜し
ていると半導体チップ一方の表面。As is clear from the above description of the embodiments, in the past, the die collet was in contact with the surface of the semiconductor chip, and if it was even slightly inclined, it would cause damage to one surface of the semiconductor chip.
エッヂのみに圧力が集中し、半導体チップ表面。Pressure is concentrated only at the edges, and the surface of the semiconductor chip.
エツヂケ著゛じるしく損傷するものであったのに対して
本発明のダイボンド装置に、加圧気体のガス圧によって
前記半導体チップケ加圧手段ケ有している。このような
構成に工nば、半導体チップの表面にガス圧孕均等に加
え本ことにより半導体チップケ回路基板に接合固定丁ゐ
ので、均一な接合固定が得らnるばかジではなく、グイ
コレクトと半導体チップが強ぐ当接して半導体チップが
損傷丁ゐことがなく、半導体装置の歩留り向上の点から
極めて有効なものである。In contrast to the die bonding device which causes severe damage to semiconductor chips, the die bonding apparatus of the present invention includes means for pressurizing the semiconductor chip by the gas pressure of pressurized gas. If such a configuration is used, the surface of the semiconductor chip will be uniformly impregnated with gas pressure, and the semiconductor chip will be bonded to the circuit board. This is extremely effective in improving the yield of semiconductor devices since the semiconductor chips are not damaged due to strong contact.
第1図(ム)は従来のダイボンド装置で半導体チン1ケ
グイボンドする状態ケ示す図、第1図(B)は同装置の
グイボンドによって半導体チップにクラックが発生した
状−態ケ示す図、第2図は不発明の一実施例におけるダ
イボンド装置の構成r示す図、第3図(ム)〜(D)は
同装置に工つ、て半導体チック“ケタ。
イボンドする工程r示す図、第4図に同工程の要部ケさ
らに詳しく説明するための図、第6図は本発明の他の実
施例におけるダイボンド装置の要部拡大図、第6図は本
発明のさらに他の実施例におけゐダイボンド装置の要部
拡大図である。
1・・・・・・ダイコレット、2・・・・・・半導体チ
ック、3・・・・・・回路基板、12・・・・・・発熱
体、14.15・・・・・・頁空開閉栓、16・・・・
・・真空装置系統、17・・・・・・加圧気体供給装置
系統。 1
代理人の氏名 弁理士 中 尾 敏 男 ほか1名w4
1図
(B)
第2図
、第4図
第5図
2FIG. 1(B) is a diagram showing a state in which a single semiconductor chip is bonded using a conventional die bonding device, FIG. The figure shows the configuration of a die bonding device in an embodiment of the invention, and FIGS. 6 is an enlarged view of the main parts of a die bonding apparatus in another embodiment of the present invention, and FIG. 6 is a diagram for explaining the main parts of the same process in further detail. It is an enlarged view of the main parts of the die bonding device. 1...Die collet, 2...Semiconductor chip, 3...Circuit board, 12...Heating element, 14.15...Page Empty open/close stopper, 16...
... Vacuum device system, 17... Pressurized gas supply device system. 1 Name of agent Patent attorney Toshio Nakao and 1 other person w4
Figure 1 (B) Figure 2, Figure 4, Figure 5 2
Claims (2)
ットと、前記ダイコレットに連結さn前記半導体チップ
ヶ前記ダイコレットの開口部に吸引する吸引手段と、前
記ダイコレットに連結さn前記ダイコレットの開口部に
加圧気体ケ供給する手段とを備えたダイボンド装置。(1) A die collet having an opening for sucking semiconductor chips, a suction means connected to the die collet for sucking the semiconductor chips into the opening of the die collet, and an opening of the die collet connected to the die collet. A die bonding device equipped with a means for supplying pressurized gas to the part.
nていることを特徴とする特許請求の範囲第1項記載の
ダイボンド装置。(2) The die bonding apparatus according to claim 1, wherein means for heating the pressurized gas is provided in the die collet.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP56168431A JPS5868942A (en) | 1981-10-20 | 1981-10-20 | Die bonding device |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP56168431A JPS5868942A (en) | 1981-10-20 | 1981-10-20 | Die bonding device |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPS5868942A true JPS5868942A (en) | 1983-04-25 |
Family
ID=15867985
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP56168431A Pending JPS5868942A (en) | 1981-10-20 | 1981-10-20 | Die bonding device |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPS5868942A (en) |
Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS63228728A (en) * | 1987-03-18 | 1988-09-22 | Sumitomo Electric Ind Ltd | Die bonding equipment for semiconductor chip |
| JP2009064903A (en) * | 2007-09-05 | 2009-03-26 | Canon Machinery Inc | Semiconductor chip mounting apparatus and method |
-
1981
- 1981-10-20 JP JP56168431A patent/JPS5868942A/en active Pending
Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS63228728A (en) * | 1987-03-18 | 1988-09-22 | Sumitomo Electric Ind Ltd | Die bonding equipment for semiconductor chip |
| JP2009064903A (en) * | 2007-09-05 | 2009-03-26 | Canon Machinery Inc | Semiconductor chip mounting apparatus and method |
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