JPS5869467A - Absolute value circuit - Google Patents

Abstract

PURPOSE:To obtain an absolute value circuit adapted for an IC by composing a circuit by interposing a resistor between an emitter follower transistor connected to each input terminal and an output transistor connected to its base. CONSTITUTION:Emitter follower transistors 3, 4 connected at the bases to input terminals 1, 2 and output transistors 5, 6 connected to their bases are provided, a resistor 11 is connected between the emitters of the transistors 4 and 5, and a resistor 12 is connected between the emitters of the transistors 3 and 6, and a load resistor 13 is connected to the collectors of the transistors 5, 6. Further, constant-current sources 7, 8 and offset output suppressing constant power sources 9, 10, 14 are provided. Accordingly, the resistors 11, 12 are set to the same value, thereby equalizing the gains in the positive and negative output amplitude and simplifying the circuit without arithmetic amplifier.

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention relates to an absolute value circuit for obtaining the absolute value of an electrical signal, which is often required during various arithmetic operations.

Various absolute value circuits have been proposed in the past, but most of them use operational amplifiers and the like, which increases the number of circuit elements used, making them unsuitable for use in semiconductor integrated circuits (ICs).

This invention uses a simple circuit configuration without using an operational amplifier.
The purpose is to provide an absolute value circuit suitable for IC implementation.

FIG. II1 is a circuit diagram showing an embodiment of the present invention.
and (2) are input terminals between which an alternating hexagonal signal is supplied, and (3) and (4) are input terminals 11 and 11, respectively.
1k YU (2) sc Toranozistor for emitter follower connected to the base, (5) and (6) are outgoing transistors whose bases are connected to the bases of transistors (3) and (4), respectively, (7J and (8J) are the emitter follower transistor (4) and (
491 and 491 are the emitter constant current sources of the output transistors (5) and (6), respectively (current values are ) is the input terminal [11,
(2) A resistor (resistance) through which a voltage generated between the emitter of the emitter-follower transistor (41) and the emitter of the output transistor (5) is applied due to the alternating voltage applied between them, and a corresponding current flows therethrough. value Rh),
(Similarly, the voltage generated between the emitter of the emitter follower transistor (3) and the emitter of the output transistor (6) is applied to the resistor (resistance value R2) through which the corresponding current flows, and the α field is The load resistance (resistance value Rs) of the commonly connected collectors of output transistors (5) and (6), (14) is connected to the commonly connected collectors of both output transistors (5) and (6), and the emitter constant Current source (91, together with GQ, a constant current source (current value IC) for suppressing offset output due to output imbalance when the input voltage is near zero, (11G is a constant voltage source (voltage value Eb) that operates this circuit ), (Iφ and aη are output terminals.

FIG. 2 is an input/output waveform diagram for explaining the operation of this circuit, and the horizontal axis indicates time t. In Figure aI2, A is the input signal Vl, 13 is the constant current source (91, QQ and (1
The output voltage vOt O when 4 is not provided is a constant current source (9
).

Below, the operation of this circuit will be explained using No. 250.

At time 1o shown in FIG. 2, the constant voltage source 061 is connected, and at time 11, potentials v1 and v are supplied to the input terminals (11 and (2), respectively, and Vl m
The input voltage of Vl-v is marked as shown at zla.

First, a constant current source (91, clc) for suppressing offset output.
The case where there is no and - will be explained. Time t1-t2
Since the threshold of is vz>V, that is, vi>o, the transistor (6) tends to be on and the transistor (6) tends to be off, the current 2m shown in Figure 5111 flows, and the current 2 tends to zero, The current flow l at this time is kl = [vx - (kTJ) In (Ih)
+ (kr/q) in ((rol-工f)AI)-
” (vl −V bird) Jz + (kT/((lRx)
J In ((Work O1 - Work 1)/il)...[I
] It is.

However, in: Bollmano constant T: Absolute temperature q: electron charge Technique 8: Reverse saturation current of transistor It is.

Then, the output voltage at this time is (vo) = (incl.
Njima, )in ((工OX - 工z)/Vz)Va 工l)〕...mark〕.

Next, between time points t2 and t3, vl (vg, that is, vl
The transistor (5) tends to be off and the transistor (6) is on, the current Xtx flows, and the current □ tends to zero, and the current flowing at this time is 1× - (vg - vz). Am + (tsuqR Mayuzushi))
In ((ko2-koa)/i黛)...spit], and the output voltage at this time is ("i'o) vg>, □, (R-g)(vg
-Vl + (kr/q) In ((work 6m - work s+
)/i♀)]...J].

In the above expression), RlwsRsSCfi
Then, the gains for the input potential difference are both R3/R1, which is equal to 1, and as shown in FIG. 2B, i;wtl-
It can be seen that the absolute value output of the output amplitude is the same between the threshold of ts and j, -t♀ to t5.

Now, if we pay attention to the time of tmt snow, it is VL-y2mQ, and the first term on the right side of the above equation (:I), On) is zero, but in the second term, OX>O, os>O. Therefore, engineering l〉0. (In) −(kT/(qRx)) j'n
((Iol-Eng x )/' [1) V
(Work 02 - Workll/f 2kv1 紫v2 ... [[ It does not become zero as in . Then, the time points tl, ts,
The output voltage at t3, that is, vl -vl-o is αo
, ) - ([Work 1] + [Work 2) ) Rst -tx
Vl=V2Vl -Vm= ((kZ/(q
Rx)) in ((ko1-koz IAl)+(](
``VCqR Mayuzumi)) In ((工 oII-I2)/!
II)) Rs Although it has the disadvantage that it does not become zero like HV and has an offset of a certain value V as shown in FIG. 2B, it can be seen that it operates as an absolute value circuit.

Next, the means for controlling the offset voltage V will be explained. First, connect the constant current source tJ4,
(Ml is not provided, M-〇, than-0) Constant" can flow source Cl4
)'s "# to flow C to Ic - (kT/(qRx)) ln ((Work01-WorkH) + (k'rAqR-)) in ((rag
-1s), 4*), the above [ma] and [old style offset current can be supplied, so the output resistance The offset current flowing through α4 can be made zero, and as shown in FIG. 2C, an absolute value output that is improved over that in FIG. 2B can be obtained.

Furthermore, by adding a constant current circuit (91, nO),
While satisfying the condition +1B, any current value number A,
By setting the value, a value of 71:ffi vs. value output as shown in FIG. 2C is output. At this time, time points t1 to 1. The flow of turtle flow 1 between the two is 11 = (v yaw V2) AI+ (kT/(qR
l))! ” ((Work 01 - Work 1) A M 10 Work 1)) The electric current flowing to the threshold at time tll - t5 is Work. = (
Vx −V2 )A2 +(kT/1(lR2)) i
n ((Step 02 - Step 2)/(+12)) The current at time tl e tQ + tQ is from Step A■,
If kool * ko2, then (Il] = C ko2] ta = 0 1°.

It goes without saying that a similar absolute value circuit can be obtained even if the circuit of the embodiment shown in FIG. 1 is used as a quadruple circuit.

As explained above, the absolute value circuit according to the present invention can be constructed with a simple circuit without using an operational amplifier, etc.
■It can also be used in a wide range of applications.

[Brief explanation of the drawing]

FIG. 1 is a circuit diagram showing an embodiment of the present invention, and FIG. 2 is a waveform diagram for explaining its operation. In the figure, (1) is the first input terminal, (2) is tg2
input terminals, (3) is the first transistor, (4) is the third transistor, (5) is the second transistor, (6
) is the fourth transistor, (11) is the second resistor, 02
1 is the first resistor, the end is the load resistance, Kasumi, and Oη is the output terminal. Agent Shin Kuzuno - (1 other person)

Claims (1)

[Scope of Claims] [11] A first and a second transistor, both of which have their bases connected to the first input terminal; and a third and fourth transistor, both of which have their bases connected to the second input terminal; a first resistor connected between the emitter output terminal of a first emitter follower circuit constituted by the first transistor and the emitter of the fourth transistor; a second resistor constituted by the third transistor; -f':@2 resistor connected between the emitter output terminal of the emitter follower circuit and the emitter of the second transistor;
and a load resistor that is commonly connected to the collectors of the second and fourth transistors and forms an output amplification circuit together with the second and fourth transistors.