JPS5870133A - Detecting circuit for light signal - Google Patents
Detecting circuit for light signalInfo
- Publication number
- JPS5870133A JPS5870133A JP56169148A JP16914881A JPS5870133A JP S5870133 A JPS5870133 A JP S5870133A JP 56169148 A JP56169148 A JP 56169148A JP 16914881 A JP16914881 A JP 16914881A JP S5870133 A JPS5870133 A JP S5870133A
- Authority
- JP
- Japan
- Prior art keywords
- terminal
- switch
- terminals
- unit
- inverting input
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Granted
Links
- 238000001514 detection method Methods 0.000 claims abstract description 37
- 230000003287 optical effect Effects 0.000 claims description 6
- 230000037303 wrinkles Effects 0.000 claims description 4
- 239000002184 metal Substances 0.000 claims 1
- 239000003990 capacitor Substances 0.000 abstract description 46
- 238000009825 accumulation Methods 0.000 abstract description 7
- 238000010586 diagram Methods 0.000 description 5
- 206010011224 Cough Diseases 0.000 description 4
- 238000000034 method Methods 0.000 description 4
- 235000006693 Cassia laevigata Nutrition 0.000 description 3
- 241000522641 Senna Species 0.000 description 3
- 238000007599 discharging Methods 0.000 description 3
- 238000004519 manufacturing process Methods 0.000 description 3
- 229940124513 senna glycoside Drugs 0.000 description 3
- 210000001364 upper extremity Anatomy 0.000 description 3
- 238000013459 approach Methods 0.000 description 2
- 239000011324 bead Substances 0.000 description 2
- 238000005520 cutting process Methods 0.000 description 2
- 230000007423 decrease Effects 0.000 description 2
- 210000004709 eyebrow Anatomy 0.000 description 2
- 239000007788 liquid Substances 0.000 description 2
- 230000003647 oxidation Effects 0.000 description 2
- 238000007254 oxidation reaction Methods 0.000 description 2
- 238000012552 review Methods 0.000 description 2
- 238000003860 storage Methods 0.000 description 2
- 235000002568 Capsicum frutescens Nutrition 0.000 description 1
- 208000003251 Pruritus Diseases 0.000 description 1
- 230000003749 cleanliness Effects 0.000 description 1
- 238000010276 construction Methods 0.000 description 1
- 235000013399 edible fruits Nutrition 0.000 description 1
- 230000000694 effects Effects 0.000 description 1
- 230000005611 electricity Effects 0.000 description 1
- 210000003414 extremity Anatomy 0.000 description 1
- 230000003993 interaction Effects 0.000 description 1
- 210000000554 iris Anatomy 0.000 description 1
- 230000005855 radiation Effects 0.000 description 1
- 239000004065 semiconductor Substances 0.000 description 1
- 229910000679 solder Inorganic materials 0.000 description 1
- 230000003068 static effect Effects 0.000 description 1
- 239000000758 substrate Substances 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04N—PICTORIAL COMMUNICATION, e.g. TELEVISION
- H04N25/00—Circuitry of solid-state image sensors [SSIS]; Control thereof
Landscapes
- Engineering & Computer Science (AREA)
- Multimedia (AREA)
- Signal Processing (AREA)
- Photometry And Measurement Of Optical Pulse Characteristics (AREA)
Abstract
Description
【発明の詳細な説明】
本発明は信号の噴出回路に―す、待rC#を荷蓄核形ホ
トセンサの微少信号の咲出にjIk通な演出回路に関r
る。さらに詳しくは、七/すの微少な等備靜電容量c以
下コンデンサという)&゛ζζ薯検た似少&&c荷信号
を、出力ラインに付加される大容量コンデンサの値に無
関係に、低jII猾で低歪の大きな出力信号として検出
でさ、かつ回路構成が棚めて量率で、検出4度の屈い積
出回路に関する。DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a production circuit which is used in a signal ejection circuit, and which is suitable for the emergence of a minute signal of a storage nuclear type photosensor.
Ru. In more detail, the small equivalent capacitance (capacitor with a capacitance of less than c) & It can be detected as a large output signal with low distortion, and the circuit configuration has a uniform quantity rate, and it is related to a 4 degree curved loading circuit.
従来mいらルていた演出回路、峙に光横出回路O−例を
講1図に示す、lおよび2はスイッチ素子C以下スイッ
チと菖う)、3は前記a4R蓄積形ホトセ/?(以下ホ
トセンサ、センナあるいはホトダイオードという)、4
は該センサ3と該スイッチlを結ぶ配線、5は該スイ、
チlI!:該スイ。Figure 1 shows an example of the production circuit that was required in the past, as well as the optical horizontal output circuit O.L and 2 are the switch elements C and below, respectively. (hereinafter referred to as photosensor, senna or photodiode), 4
is the wiring connecting the sensor 3 and the switch l, 5 is the switch,
ChilI! : The sui.
チ2を耐ぶ出力ライン、6は出力端子、7は該センサ3
を充電するための電圧源、50fi負蓚コンデンナであ
る。第2図、第3図は該センナ30等価回路である0図
において31は等価ダイオードc以下タイオードという
)、32は等価接合コンデ/す(以下コンデンサという
)、33は等価抵抗素子(以下抵抗という)、34ij
等倫電流源である。以下、該センサ3t−説明する時は
第213!Jの等m回路を用いる。なお核抵抗33は光
強度に応じ、その抵抗値が変化する。縛ち、光強度が強
い楊金、抵抗値が小さく、光強度が弱い場合、抵抗値は
大きい、また光pA射がない場合、抵抗値は通常はぼj
I@大と見なせる程度に大きい、第4図Vよ縦センサ3
に第2図を用いて示した8g1図の等m回路である。な
お、同図において第1図、第2図と同一番号の素子は譲
1図、第2wJの素子と同一である。41ri鍍配線4
の等幽コンデンサである。6 is the output terminal, 7 is the sensor 3
The voltage source for charging is a 50fi negative condenser. Figures 2 and 3 are equivalent circuits of the Senna 30. In Figure 0, 31 is an equivalent diode (hereinafter referred to as a diode), 32 is an equivalent junction capacitor (hereinafter referred to as a capacitor), and 33 is an equivalent resistance element (hereinafter referred to as a resistor). ), 34ij
It is a constant current source. Hereinafter, the 213th sensor 3t will be explained. An equal m circuit of J is used. Note that the resistance value of the nuclear resistance 33 changes depending on the light intensity. When the light intensity is strong, the resistance value is small, and when the light intensity is weak, the resistance value is large, and when there is no light pA radiation, the resistance value is usually vague.
Vertical sensor 3 is large enough to be considered as I@large, as shown in Fig. 4 V.
This is an equal m circuit of the 8g1 diagram shown using FIG. In addition, in the figure, elements having the same numbers as in FIGS. 1 and 2 are the same as the elements in FIG. 1 and 2WJ. 41ri wiring 4
It is a similar capacitor.
51d該出カライン5の41+diiコンデンサで、構
造上、極めて大きな容量−を持つ場合がしばしばある。51d The 41+dii capacitor of the output line 5 often has an extremely large capacitance due to its structure.
第5図は該スイッチ1,2の開閉のタイミングと出力信
号波形のタイミングである。l13よび12はそれぞれ
該スイッチ1および2に対応し、11あるいは12が高
レベルで示されている期間および低レベルで示されてい
る期間はスイッチがそれぞれ閉じているJ18間および
開いている期間に対応している。次に第4図、第5図を
用いて、本検出回路の動作を説明する。・12本検出回
1の動作期間中破センサ3へは常時元wa肘があり、該
抵抗33の抵抗値はあるf限の−であるとする。今すセ
ット期間14ではJスイ、チ2は閉じているから、該コ
ンデンサso、siは短絡さIし、蓄積されていた電荷
離放゛1する。従って、端子60山力値号7よ13に示
すように産地レベルにセットされる。一方、該スイッチ
lも閉じているから、Jコンデンサ32r!充電され、
端子35μ景地レベルに、端子36は該電圧#i7の電
圧レベルBボルト(ここではE>Oと仮定する)にそれ
ぞれセ。FIG. 5 shows the timing of opening and closing of the switches 1 and 2 and the timing of the output signal waveform. 113 and 12 correspond to the switches 1 and 2, respectively, and the period when 11 or 12 is shown as high level and the period that is shown as low level corresponds to the period when the switch is closed and the period when it is open, respectively. Compatible. Next, the operation of this detection circuit will be explained using FIGS. 4 and 5. - It is assumed that during the operation period of 12 detection times 1, there is always an original contact with the intermediate failure sensor 3, and the resistance value of the resistor 33 is - within a certain f limit. In the current set period 14, J switch 2 is closed, so the capacitors so and si are short-circuited, and the accumulated charge is released. Therefore, the power level of the terminal 60 is set to the production area level as shown in numbers 7 to 13. On the other hand, since the switch l is also closed, the J capacitor 32r! charged,
The terminal 35μ is set to the ground level, and the terminal 36 is set to the voltage level B volts of the voltage #i7 (assuming E>O here).
トされる0次に該スイッチ1,2が共に開いている蓄積
期間15では該コンデンサ32に充電された電荷鉱抵抗
33を介し放電する。その結果、前記眉間14で接地レ
ベルにセットされた端子35の電位は徐々に上昇し、B
に近ずく。今該蓄積期間15の最終時点で、該端子35
の電位がVポルトに達した表する(V≦8)。同時に該
期間15で該コンデンサ41は充電される。次に検出期
間16でスイッチ1のみが閉じるから、該コンfy+3
2.41,50.51の間で電萄の再分布が生じ、13
に示すように、端子6の電位は接地レベルよりわずかに
上昇する。4ら、該上昇分が本検出回路の出力1JI−
号となる。以上該期間14゜15.16が信号検出の一
周期で、以後これを繰り返えすことにより順次信号検出
がf?なわれる。During the accumulation period 15 during which the switches 1 and 2 are both open, the charge stored in the capacitor 32 is discharged through the resistor 33. As a result, the potential of the terminal 35, which was set at the ground level between the eyebrows 14, gradually rises, and B
approach. Now, at the end of the accumulation period 15, the terminal 35
represents that the potential of has reached V port (V≦8). At the same time, the capacitor 41 is charged during the period 15. Next, since only switch 1 closes during the detection period 16, the configuration +3
A redistribution of electricity occurs between 2.41 and 50.51, and 13
As shown in , the potential of terminal 6 rises slightly above the ground level. 4, the increase is the output 1JI- of this detection circuit.
number. The above period of 14°15.16 is one cycle of signal detection, and by repeating this, the signal detection is sequentially f? be called.
第1図の回路において、該出力ライン5は通常橋めて長
いため、その等価コンデ/す51も500pF〜100
0pF といった樹めて大きな値となる場合が多い。こ
のため負荷コンデンサ50を別遜接続する必要もなく、
皺コンデンサ51のみで負荷コンデンサと見なせる。こ
れより、咳従来の検出回路を以下ではコンデンサ形検出
回路と呼ぶ。今、−例として、前記コンデ/す32,4
1,50゜51(D容量値をそれぞれo、zpr 、4
.8pF’gQ、ZpF。In the circuit shown in FIG. 1, since the output line 5 is usually long, the equivalent capacitor 51 is also 500 pF to 100 pF.
It is often a very large value such as 0 pF. Therefore, there is no need to separately connect the load capacitor 50,
The wrinkled capacitor 51 alone can be considered as a load capacitor. Therefore, the conventional cough detection circuit will be referred to as a capacitor type detection circuit hereinafter. Now - as an example, the said conde/su 32,4
1,50°51 (D capacitance values are o, zpr, 4, respectively)
.. 8pF'gQ, ZpF.
419.89F とし、蓄積期間15で端子35の電位
Vが1−5ボルトであったとすれば、出力信号は約1
y=vとなり、約1/100に減少する。など該コンデ
ンサ51の容量値は前8J2′4緻値よりさらに大きな
値となることがしばしrfある。この場合、出力11号
はさらに小さくなる。従来のコンデンサ形検出回路の最
大の欠点は、出刃ライン5の彎−コンデンサ51が−め
て大きいために、出力信号が前記のように極めて小さく
なることである。また前記スイッチ1,2は通常)’E
T等が用いられるので、出力信号に74−トスルーが重
畳する上、人きなスイツナング雑歯が一人する。このた
めダイナI、クレンジが極めて低下する。さらに出力1
8号が−めて小さいから、出力端子6と4幅回路tバ、
フ1回路を介して接線し、信号の増幅を行なう必要があ
る。このため、回路の繁雑化、高消費電力化、低87N
化等極めて不都合な結果を生ずる。419.89F, and if the potential V at the terminal 35 is 1-5 volts during the accumulation period 15, the output signal will be approximately 1
y=v, which decreases to about 1/100. The capacitance value of the capacitor 51 is often larger than the previous 8J2'4 value. In this case, output No. 11 becomes even smaller. The biggest drawback of the conventional capacitor-type detection circuit is that since the curve of the cutting line 5 and the capacitor 51 are very large, the output signal becomes extremely small as described above. Also, the switches 1 and 2 are normally)'E
Since T, etc. are used, 74-to-through is superimposed on the output signal, and there is also one person who has a strange problem. For this reason, Dyna I and cleanliness are extremely reduced. Furthermore, output 1
Since No. 8 is very small, the output terminal 6 and the 4-width circuit t-bar,
It is necessary to connect the signal through the F1 circuit and amplify the signal. For this reason, the circuit becomes more complicated, the power consumption increases, and the low 87N
This results in extremely inconvenient results such as oxidation.
従来用いられていた検出回路の他の例を第6図に示す、
この回路は負荷として抵抗素子21を用いているので、
ここでは抵抗形検出回路と呼ぶ。Another example of a conventionally used detection circuit is shown in FIG.
Since this circuit uses the resistive element 21 as a load,
Here, it is called a resistance type detection circuit.
岡!IK#いて、各41系が第1図、第2図の各素子と
同一のものは10ト1号で示されている。なお該センf
3の勢価回路として第2図を用いるものとする。第7−
の22は第6図のスイッチ1の開閉を示すタイ1ングと
第6図の端子6より得られる信号液形の一例を示したも
のである。なお鴇5図と同様、琳7−の22が鳥レベル
の期間Sよび低ジベル0IIIII間はそれぞれスイッ
チlが閉じている眉間および開いている期間に対応する
。次に第6嗣、第7図を用いて、従来の抵抗形検出回路
の動作を説明する。なお―作条性は第4図と同一である
とする。今期間24の最終状總で端子35が接地レベル
に設定されているものとする。蓄積期間25で該スイッ
チlが開くと、該コンデンサ32に蓄積された電荷は光
照射され抵抗−が、b))育成の−を持った抵抗33を
介し放電する。そのに来、前記期間24でII地レベル
にあった端子35の電圧は徐々に上昇し、Eに近すいて
ゆく。今蓄槓期間25の最終時点で該端子35の電位が
Vボルトに連したとする(V≦g)。次に検出期間26
でスイッチlが閉じると、端子6の電位ζ、23に示す
ように、まず接地レベルから上昇し、ピーク値KMI、
、次に減少して、最後には再び舗地レベルに戻る。従っ
て、該期間中、譲コンデンf32#i再び充電される。hill! IK#, each 41 system having the same elements as those shown in FIGS. 1 and 2 is designated by No. 10. In addition, the said Sen f
Assume that Figure 2 is used as the price circuit for No. 3. 7th-
22 shows an example of a signal liquid type obtained from the tie 1 indicating opening/closing of the switch 1 shown in FIG. 6 and the terminal 6 shown in FIG. Note that, similarly to the figure 5, the period S when 22 of Rin 7- is at the bird level and the low level 0III correspond to the period between the eyebrows when the switch 1 is closed and the period when it is open, respectively. Next, the operation of the conventional resistance type detection circuit will be explained using FIG. 6 and FIG. Note that the row construction properties are the same as in Figure 4. It is assumed that the terminal 35 is set to the ground level in the final state of the current period 24. When the switch 1 is opened during the accumulation period 25, the charges accumulated in the capacitor 32 are irradiated with light and are discharged through the resistor 33 which has b)) growth. After that, the voltage at the terminal 35, which was at the II ground level during the period 24, gradually increases and approaches E. Assume that the potential of the terminal 35 reaches V volts at the end of the storage period 25 (V≦g). Next, detection period 26
When the switch l is closed, the potential ζ of the terminal 6 first rises from the ground level as shown in 23, and reaches the peak value KMI,
, then decreases and finally returns to pavement level again. Therefore, during this period, the transfer capacitor f32#i is charged again.
以上が11号検出の一周期で、以後蓄積、検出期間を繰
り患えずことにより、次々と信号を検出する。今、−例
として、該コンデン?32,41.51の静m容量値が
そルそれ0.21)F、4.81)F、5001)F
(!: シT:、 dVカ1.5ホtkトであったとす
る。この時の出力信号23のピーク値はたかだか約t7
mVICJぎない。こnは、前述し九従来のコンデ/す
形砿出回路と同様、Vか大きな−となるにもかかわらず
、読み出される信号は極めて小さいという重大な欠点を
生ずる。mスイ、チ素子lが例えばFISTの場合、期
間26に現われる出力15号は、該スイッチ1を閉じる
時に生ずるスイ、チンダ鑵音が重畳される。また該スイ
ッチを開く時、期間25の最初の部分に兇られみよ5に
、出力信号23に負方向(同図では下方向)Oスイ、チ
ンダ雑音が生ずる。このように、微少信号出力に対して
大きなスイ、チ/グs11が存在するから、ダイナミッ
クレンジ、8/Nが非常に小さくなる0本回路の他の欠
点は回路の時定数が大きいため1#号の読み出し速度が
遅くなることである。従って信号を検出期間内で完全に
読み出すことが不可1となる(不完全読み出し)。即ち
、検出眉間26で端子6の電位が接地レベルに戻らない
伏線が生ずる。さらに、出力信号が砿少な上、波形23
で示すように出力1d号がホールドされないため、出力
信号のホールドと増@を必要とする。このため、バ、フ
ァ回路、8/H回路あるいは積分−路、増幅回路を付加
する必要が生じるから、1g回路の*酸化、消費電力の
増大、4虐の増加など重大な欠点が生じる。The above is one cycle of No. 11 detection, and since the accumulation and detection periods are not repeated, signals are detected one after another. Now - as an example, the condensate? The static m capacitance value of 32,41.51 is 0.21)F, 4.81)F, 5001)F
(!: Suppose that the dV power is 1.5 tk. The peak value of the output signal 23 at this time is about t7 at most.
mVICJginai. Similar to the nine conventional condenser type lead-out circuits described above, this has a serious drawback in that the signal read out is extremely small even though V is large. When the switch 1 is a FIST, for example, the output No. 15 appearing in the period 26 is superimposed with the sound of the switch 1 generated when the switch 1 is closed. Further, when the switch is opened, a negative direction (downward direction in the figure) noise is generated in the output signal 23 at the beginning of the period 25. In this way, since there is a large switch/ch/g s11 for a small signal output, the dynamic range and 8/N become very small. The issue is that the reading speed of the issue becomes slower. Therefore, it becomes impossible to completely read out the signal within the detection period (incomplete readout). That is, a foreshadowing occurs in which the potential of the terminal 6 does not return to the ground level at the detection glabella 26. Furthermore, the output signal is small and the waveform 23
As shown in , since the output 1d is not held, it is necessary to hold and increase the output signal. For this reason, it becomes necessary to add a buffer circuit, an 8/H circuit, an integral circuit, and an amplifier circuit, resulting in serious drawbacks such as oxidation of the 1g circuit, increased power consumption, and increased power consumption.
本発明の目的は上記従来のlJI伽点を解決し、出力ラ
インの−めで大きな等価コンデンサの影響を全(除去す
ると共に、大きな出力が得られ、読み出しスピードが速
い上、8/N8よびダイナミ。The purpose of the present invention is to solve the above-mentioned disadvantages of the conventional IJI, completely eliminate the influence of a large equivalent capacitor on the - side of the output line, obtain a large output, have a fast readout speed, and achieve 8/N8 and dynamism.
クレンジが大きく、構成が−めて簡単な検出回路を提供
することにある。The object of the present invention is to provide a detection circuit with a large range and a simple configuration.
本発明によればホトダイオードと駅ホトダイオードを繰
り返し充放−させるスイッチ素子が接続され九ユニ、ト
と、少なくでもコンデ/す、スイッチ素子右よび演痒増
幅器1−1む積分回路を備え、該ユニットの該スイッチ
素子側の端子と該積分回路の反転入力端子が配線静電6
114を含む出力ラインを介して接続され、禮ユニ、ト
のホトダイオード側の端子が電圧源に接続され、腋積分
回路の非反転入力端子が基準電圧源にthlI#lRさ
れ、該積分回路の反転3よび非反転入力端子がスイッチ
素子を介してjlI硫されていることを特徴とする元信
号検出1路が得られる。更に:複数−の前記ユニットと
前記積分回路を備え、砿各ユニ、トのスイッチ素+側O
端子を互いK11Jil!すると共に、該端子と該積分
回路の非反転入力端子を出力ラインを介して接続し、該
ユニットのホトダイオード側の端子を互いに接続した上
肢端子と電圧源を接続し、該積分回路の非反転入力端子
と基準電圧源を接続し、皺積分回路の反転および非反転
入力端子がスイッチ素子を介して接続されていることを
特徴とする光信号検出回路が得られる。またm個(m”
正整数)の前記1二、)で構成されるグロ、りがn個(
aツ正豊数)と、m記積分1ω路と、第1のスイッチ素
子、@2のスイッチ素子、・・・・・・第mのスイ、チ
嵩子の合計m個のスイッチ素子を備え、該各ブー、りO
第14目のユニット内のスイッチ素子側am子を互いに
接続した上肢端子と該第1のスイッチ素子の一方の端を
接続し、該各ブロックの嬉211目のユニット内のスイ
ッチA子側の端子を亙いK1141した玉鎖端子と該第
2のスイッチ素子の一方の端をi1続し、以下同様に、
該各グgffyりのllI目のユニット内のスイッチA
子側の端子を互いに遺統した上肢端子と該第mのスイッ
チ素子の一方の端を接続し、at第1.第2、・・・−
・第mのスイッチ素子の他方の端を互いに!I統した玉
鎖端と皺積分回路の反転入力端子を出力ラインを介して
IL練し、該各ユニ、トのホトダイオード側の端子を互
いにiI統した玉鎖端子と電圧源を接続し、該積分回路
の非反転入力端子と基準電圧源を接続し、該積分回路の
反転および非反転入力端子がスイッチ素子を介して接続
されていることt−特徴とする光信号検出回路が得らI
Lる。According to the present invention, a photodiode and a switching element for repeatedly charging and discharging the photodiode are connected, and the unit includes an integrating circuit including at least a condenser, a switching element, and an itch amplifier 1-1; The switch element side terminal and the inverting input terminal of the integrating circuit are connected to the wiring electrostatic capacitor 6.
114, the terminals on the photodiode side of the terminals are connected to a voltage source, the non-inverting input terminal of the armpit integrating circuit is connected to the reference voltage source, and the inverting voltage of the integrating circuit is An original signal detection path is obtained, characterized in that the input terminal 3 and the non-inverting input terminal are connected to each other via a switching element. Further: a plurality of the units and the integrating circuit are provided, and each unit has a switch element on the positive side O.
Connect the terminals to each other K11Jil! At the same time, the terminal and the non-inverting input terminal of the integrating circuit are connected via an output line, and the terminals on the photodiode side of the unit are connected to the upper limb terminal and the voltage source, and the non-inverting input terminal of the integrating circuit is connected to the terminal. An optical signal detection circuit is obtained, characterized in that the terminal is connected to a reference voltage source, and the inverting and non-inverting input terminals of the wrinkle integrating circuit are connected via a switch element. Also, m pieces (m”
There are n pieces (12,) of positive integers)
A total of m switching elements including a (a positive number), an m-th integral 1ω path, a first switching element, @2 switching element, m-th switch, and a switch element, Each boo, RiO
Connect the upper limb terminals that connect the switch element side AM elements in the 14th unit to one end of the first switch element, and connect the switch A element side terminals in the 211th unit of each block. Connect the ball chain terminal with K1141 through i1 to one end of the second switch element, and similarly,
Switch A in the llth unit of each group
Connect the terminals on the child side to the upper limb terminals that are inherited from each other and one end of the m-th switch element, and connect the at-th . Second,...-
・Connect the other ends of the m-th switch element to each other! Connect the I-connected bead chain end and the inverting input terminal of the wrinkle integrator circuit via the output line, and connect the photodiode side terminals of each unit to the II-connected bead chain terminal and voltage source. An optical signal detection circuit is obtained, characterized in that a non-inverting input terminal of an integrating circuit is connected to a reference voltage source, and the inverting and non-inverting input terminals of the integrating circuit are connected via a switch element.
L.
以下図面を参照して本発明の実施例を詳細に説明する。Embodiments of the present invention will be described in detail below with reference to the drawings.
第8図に本発明の第1実施例を示す、l、2rよスイッ
チ素子、3#i電荷蓄積形ホトセンサC以上センサ、ホ
トセンサあるいはホトダイオードという)、4は該セン
サ3と一スイ、チ4を接続する配線、5は出力ライ/、
6は出力端子、7は・−比値Bボルトの電圧#(ここで
はB〉0とする)である、31.32.33はそれぞれ
威センサ3の等価ダイオード、等価コンデンサ、′:4
噛抵抗抵抗素子2図に対応する。41は配@4の4噛ツ
ンデンナ、slは出力ラインSの等価コンデンサ、・O
は演算項−I)(以下OF A、、という)61・:I
yデンサ62.スイッチ素子63を含む積分回路、64
社電圧値IBボルトの基準電圧+1[(以下の説明では
、Bv&は接地レベルとする)、35゜36.37,5
2.53は端子、54および55はそれぞれ該積分回路
60の反転および非反転入力端子である。なお該センサ
3、スイッチlを含む回路をここでは便宜上エニv )
30と呼ぶ。第9図に該スイッチ素子1,63の開閉
のタイミングと端子35および6の電位変化の一例を示
す。FIG. 8 shows a first embodiment of the present invention, in which 1 and 2r are switch elements, 3#i are charge accumulation type photosensors (hereinafter referred to as C and above sensors, photosensors or photodiodes), 4 is the sensor 3, 1 switch, and 4. Wiring to connect, 5 is output line/,
6 is the output terminal, 7 is the voltage # of -ratio value B volts (Here, B>0), 31, 32, and 33 are the equivalent diode and equivalent capacitor of the power sensor 3, respectively, ': 4
Biting resistance element corresponds to Figure 2. 41 is the 4-bit tundenna of the distribution @4, sl is the equivalent capacitor of the output line S, ・O
is the operand -I) (hereinafter referred to as OFA) 61.:I
ydenser 62. Integrating circuit 64 including switch element 63
Reference voltage of company voltage value IB volt + 1 [(In the following explanation, Bv& is assumed to be the ground level), 35° 36.37, 5
2.53 is a terminal, and 54 and 55 are inverting and non-inverting input terminals of the integrating circuit 60, respectively. Note that the circuit including the sensor 3 and the switch 1 is referred to here for convenience.
Call it 30. FIG. 9 shows an example of the timing of opening and closing of the switch elements 1 and 63 and changes in the potentials of the terminals 35 and 6.
71#i該スイ、チ1に、該スイッチ63に対応し、1
1あるいは72が^レベルおよび低レベルで示されてい
る期間はそれぞれ各スイッチが閉あるいはllO状態を
示している。73および74はそれぞれ端子35の電位
変化および端子6のtt位変化(即ち、出力信号)であ
るs’−1:875については畿述する。71#i corresponding to the switch 63,
During periods when 1 or 72 is shown as ^ level and low level, each switch is in the closed or 110 state, respectively. 73 and 74 are the potential change at the terminal 35 and the tt level change at the terminal 6 (ie, the output signal), respectively. s'-1:875 will be described below.
以下では該スイッチ2がない場αの動作を説明する。な
お従来の検出回路の説明と同様、該センす3には常時光
が照射されており、該抵抗素子33はある有限の抵抗値
を有しているものとする。The operation of α in the absence of the switch 2 will be described below. Note that, similarly to the description of the conventional detection circuit, it is assumed that the sensor 3 is constantly irradiated with light and that the resistance element 33 has a certain finite resistance value.
また該電圧源7の電位Eはある正の値(例えばlOボル
ト)、該基準鑞圧源64の電位EkLはj地レベルとす
る。リセット期間81で該スイッチ63が閉じると該コ
ンデンサ62が放電すると共に、4子54の電位は該U
P Amp 61 、/)イマジナリシ、−トを介し接
地レベルとなっているから、端子6の電位も74に示す
ように接地レベルへ戻る。同f1に端子52.53も接
地レベルとなるから、該コンデンサ51は!!!L11
Kする0次の43禰82ではいずれのスイッチ素子も−
の状lItにある。従りて、該コンデンサ32に蓄積さ
れているmaは該抵抗素子33を介し、逐次放電されて
いるがら、端子35,370m位は、73に示すように
、次の期間J3で該スイッチlか閉じる時刻まで、逐次
変化(この場合、上昇)する、従うて該コンデンサ32
と411C蓄積されたttto変動分は端子35.37
の電位の変―分に両コンデ/すの静電容量の相を乗算し
た結果に尋しい。次の検出期間s3で、該スイッチlが
閉じると、各コンデンす!!、41,51.62に電荷
の両分布が生じ、端子54(同様に35.37,52.
j3)の電位が変−する、一方OP ADIg) 61
は該端子54の電位をイマジナリショートを介し基準電
圧レベル(接地レベル)へ戻そ5と働くゆ以上の動作を
繰り返えすことにより、最終的には4子53の電位砿接
鳩レベルに復帰する。従って、一時的に、鋏ブンブン−
?−51は電荷の充放電を行なうが、最終的にはC定常
状態では)該コンデンサ51には電荷は蓄積されること
はない。Further, the potential E of the voltage source 7 is assumed to be a certain positive value (for example, 10 volts), and the potential EkL of the reference solder pressure source 64 is assumed to be at the j-ground level. When the switch 63 is closed during the reset period 81, the capacitor 62 is discharged and the potential of the quadruplets 54 is
Since P Amp 61 , /) is at the ground level through the imaginary terminal, the potential of the terminal 6 also returns to the ground level as shown at 74 . Since the terminals 52 and 53 are also at the ground level at f1, the capacitor 51 is! ! ! L11
In the 0th order 43 wire 82 with K, any switch element is -
It is in the state of lIt. Therefore, while the ma stored in the capacitor 32 is sequentially discharged through the resistive element 33, the terminals 35 and 370m are not connected to the switch l in the next period J3, as shown at 73. The capacitor 32 changes sequentially (increases in this case) until the closing time.
and 411C accumulated ttto variation is terminal 35.37
This is the result of multiplying the change in potential by the phase of the capacitance of both capacitors. In the next detection period s3, when the switch l closes, each capacitor! ! , 41, 51.62, and the terminal 54 (also 35.37, 52 .
The potential of j3) changes, while OP ADIg) 61
By repeating the above operation of returning the potential of the terminal 54 to the reference voltage level (ground level) via an imaginary short circuit, the potential of the four terminals 53 is finally returned to the ground level. . Therefore, the scissors are buzzing temporarily.
? -51 performs charging and discharging of electric charge, but ultimately no electric charge is accumulated in the capacitor 51 (in the C steady state).
一方、端子35.37の電位も接地レベルとなるから、
該コンデンサ32線元の状態に光電され、該コ/デ/す
41は放電する。従って、前述したように、該期間83
が開始する直前までに変動し九両コンデンサ32と41
の区々変動分はこの時 点で%1−IE、トされ、該変
動電萄分に相当する電荷量が該コンデンサ62に積分さ
れたことになる。On the other hand, since the potential of terminals 35 and 37 is also at ground level,
The capacitor 32 is photoelectrically restored to its original state, and the code/de/su 41 is discharged. Therefore, as mentioned above, the period 83
It fluctuates just before the start of the nine-car capacitors 32 and 41.
At this point, the amount of variation in the voltage is calculated by %1-IE, and the amount of charge corresponding to the amount of variation is integrated into the capacitor 62.
従りて、74に不すよ5に、端子6の電位は接地レベル
より下がり、出力信号成分となる。次のホールド期間8
4で、該スイッチlが開いても、端子6の出力信号は7
4に示すよ5に、検出期間83の値をホールドする。と
同時に原コ/デンサ32は該抵抗素子33を介し、放電
を開始す6(73参照)0以上#4m01間81,82
゜83.84を一周期とし、これを繰り返えすことによ
り、順次信号の検出が行なわれる。Therefore, at 74 and 5, the potential at terminal 6 falls below the ground level and becomes an output signal component. Next hold period 8
4, even if the switch l is open, the output signal at terminal 6 is 7.
4, the value of the detection period 83 is held. At the same time, the original capacitor 32 starts discharging via the resistive element 33 (see 73) between 0 and #4m01 81, 82
83.84 is one period, and by repeating this cycle, signals are sequentially detected.
今該コンデンサ32,41.62の静電容量をそれぞれ
0.2p?、 t8pF、 5.0.F とし、譲ス
イッチlが閉じる直前に端子35の電位が約lボルト上
昇したとすれば、通常500〜1.0009Fという大
きな値のコンデンサ51の静電容量値K11li−係に
、端子6の出力信号「工約−1ボルトとなる。この憾は
従来の検出回路に比べ、極めて大きな−である。Now, the capacitance of the capacitors 32 and 41.62 is 0.2p each? , t8pF, 5.0. F, and if the potential at the terminal 35 rises by about 1 volt just before the yield switch l closes, then the output at the terminal 6 will change depending on the capacitance value K11li of the capacitor 51, which usually has a large value of 500 to 1.0009F. The signal voltage is approximately 1 volt. This voltage is extremely large compared to conventional detection circuits.
また、該スイッチ素子lがFNT→で構成さ7Lる勘合
、該スイッチの開閉時に互いに反対力1−へのスイッチ
ング雑音を生じる。しかし本発#41こよれGズ該スイ
、チング雑會はコンデンサ62で互&’+’Cキャンセ
ルされる方向で積分されるから、期間84で傷られる信
号はきわめて唯會の少ない出力信号となる。In addition, when the switch element 1 is made up of FNT→7L, switching noise occurs due to mutually opposing forces 1- when the switch is opened and closed. However, since the current signal #41 is integrated in the direction of mutual &'+'C cancellation by the capacitor 62, the signal damaged in the period 84 is an output signal with very little interaction. Become.
以上、咳スイッチ2が付加されていない場合について説
明した。次Kmスイ、チ2が付加された場合を説明する
。今咳スイ、チ2のi;ll閲状態が。The case where the cough switch 2 is not added has been described above. Next, a case where Km switch 2 is added will be explained. Now cough sui, Chi 2's i;ll review status.
該スイッチ63の開閉のタイミングと同一で、第9図7
2で示されるものとする。今何らかの原因で、例えば外
乱による雑鱈で、端子52.53の電位が接地レベルと
興なる場合、該コンデンサ51に:III積゛された雑
音による電荷t−強制的に放電させることが出来る。ま
た該スイッチlの開閉タイミングが75で、スイッチ4
2と63のタイミングが72で示される場合、該リセッ
ト期間81中に咳コンデンサ32,41.51を強制的
かつ急速にリセットすることができる。即ち、配線4゜
出力ライン5あるい紘抵抗素子70に雑音が重畳された
場合、あるいは駆動モードが―めて高速な場合等に譲ス
イ、チ1,2によるリセットが轡めて有効である。The timing of opening and closing of the switch 63 is the same as that of FIG.
2. If the potential at the terminals 52 and 53 rises to the ground level for some reason, for example due to a disturbance, the capacitor 51 can be forcibly discharged by the charge t due to the accumulated noise. Further, the opening/closing timing of the switch 1 is 75, and the switch 4
If the timing of 2 and 63 is shown at 72, the cough capacitor 32, 41.51 can be forced and rapidly reset during the reset period 81. In other words, when noise is superimposed on the wiring 4° output line 5 or the resistance element 70, or when the drive mode is extremely high speed, resetting using the transfer switch 1 and 2 is extremely effective. .
第1061K不発明の縞2の実m例を示す。本実施例は
第8図に示したユニ、ト30を複数個に拡張し、アレイ
化している。、410図において81゜82.83は第
8図の該ユニット30に対応し。An actual example of the 1061Kth uninvented stripe 2 is shown. In this embodiment, the units 30 shown in FIG. 8 are expanded into a plurality of units and arranged into an array. , 410, 81°82.83 corresponds to the unit 30 in FIG.
合計l閲(/=正!II数)噛えている。なお同図の各
構成便素は第8図の同一番号の構成要素と同一である。Total of 1 reviews (/=correct! II number) I can chew. Note that each component in this figure is the same as the component with the same number in FIG.
第11図は第10117)各スイッチの開閉状態と出力
信号波形の一例を示したものである。FIG. 11 shows an example of the open/close state of each switch (10117) and the output signal waveform.
91は該ユニット81のスイッチ1,92は核ユニ、ト
82のスイッチ1,93Fi該ユニツト83のスイッチ
1.94は該スイッチ2および6にそれぞれ対応し、各
波形の高レベルおよび低レベルの期間がそれぞれ各スイ
ッチが閉じている期間るよび關いている期間に相当する
。95は端子6より優られる出力信号波形で−bる。な
お不実14i例の動作は41J!施例(第8図)と′基
本的には四槽である。′fcだし該各ユニット81,8
2,83のスイッチlば、第11図にボしたように、一
定の周期でかつ規則正しく順次開閉し、各ユニ、)81
゜82.83の該センサ3tJ次読み出すj11方式と
なりている。従って、iIl数−の該センサ3から同時
に11号tdみ出すことσない。91 corresponds to the switch 1 of the unit 81, 92 the nuclear unit, the switch 1 of the unit 82, 93Fi the switch 1 of the unit 83, and the switch 94 corresponds to the switches 2 and 6, respectively, and indicates the high level and low level period of each waveform. correspond to the period when each switch is closed and the period when it is open, respectively. 95 is an output signal waveform superior to terminal 6 -b. In addition, the operation of the unfaithful 14i example is 41J! Example (Fig. 8) and 'Basically, there are four tanks. 'fc and each unit 81, 8
As shown in Fig. 11, the switches 2 and 83 are opened and closed in regular order and at regular intervals, and the switches 81
The J11 method is used to read out the sensor 3tJ times at 82.83 degrees. Therefore, the number 11 td does not protrude simultaneously from the sensor 3 with iIl number -.
嬉12図に本発明の第3の実施例を示す0本夷確例は1
s10図に示し九実−例をさらpc拡大したものである
。即ち、m個(rn=正整数)の前記ユニットを1ブロ
ツクとしてさらに該プロ、りをn個(膳冨正!l数)設
けた構成である。 101,103゜111.113,
121,123Fi第8図、/) ユニy ) 30
K対応している。101,103は第1番目のグー、り
を構成し、それぞれ肢グp、り内の1番目およびm1l
lのユニットである。なお該1番目のブロック内の第2
番目から第(ml)$dのユニットは第12図では省略
されて縞刀1t′Lでいる。以下間fiK111,11
3 ハソレぞれm2−1目ノア’f、り内の第1番目、
第m番目のユニット、121,123は第yh41/目
のプロ、り内の第1番目、第m番目のユニ、ト、である
。但し第12図でF13番目から第(n 1)井目の
グー、りは省略さルて描かれている。 201,202
,203 はスイッチ索子でそれぞれ各グー、り内の
1#目のユニット(101,111゜121)、第2番
目のユニット(Ilr略されている)、菖m曹目の!二
、 ) (103,113,123) K対応している
。なお同図の他の構成要素鵜第8図の同一番号の構成1
!巣と同一である。Figure 12 shows the third embodiment of the present invention.
This is a further pc enlargement of the nine fruit example shown in Figure s10. That is, the configuration is such that m units (rn=positive integer) of the above units are used as one block, and n units (the number of units) are further provided. 101,103゜111.113,
121,123Fi Figure 8, /) Uniy) 30
Compatible with K. 101 and 103 constitute the first group and ri, respectively, and the first and m1l in the limb group p and ri, respectively.
It is a unit of l. Note that the second block in the first block
Units from th to (ml) $d are omitted in FIG. 12, and are shown as striped sword 1t'L. between fiK111,11
3 Each m2-1 Noa'f, the first in the
The m-th unit, 121 and 123, is the first m-th unit in the yh41/th professional unit. However, in Figure 12, the goo and ri from the F13th to the (n1)th eye are omitted. 201, 202
, 203 are switch cables, respectively, for each goo, the 1st unit (101, 111° 121), the 2nd unit (Ilr abbreviated), and the irises! 2. ) (103, 113, 123) K compatible. In addition, other components in the figure 1 with the same numbers in Figure 8
! Same as nest.
第13図は第12図の各スイッチ索子の開閉状態と出力
波形の一例をボしたものである。300は第1番目のグ
ー、りに属するユニ、 ) 101,103のスイッチ
素子1に対応する。同様K 310は第2番目のグー、
りKJliするユニ、 ) 111,113のスイッチ
素子IK、320は’dE n a目のグーツクに属す
るユニ、 ) 141,123のスイッチ索子lにそれ
ぞれ対応する。401,402,403 はそれぞル
スイ。FIG. 13 shows an example of the open/closed states and output waveforms of each switch cord shown in FIG. 12. 300 corresponds to the switch elements 1 of uni, ) 101, 103 belonging to the first group. Similarly, K 310 is the second goo,
The switch element IK of ) 111, 113, 320 corresponds to the switch element I of ) 141, 123, which belongs to the 'dEna-th Gutsk. 401, 402, 403 are Rusui respectively.
チ素子201,202,203に対応する。SOOはス
イ。This corresponds to elements 201, 202, and 203. SOO is Sui.
チ素子2,63に対応すゐ。なお各液形の高レベルおよ
び低レベルの期間がそれぞれ各スイッチ索子が閉じてい
る期間および開いている期間に相当する。600は端子
6より慢らルる出力波形の一例で、高レベルかはぼ1準
電圧レベルに、低レベルが信号成分に対応する。It corresponds to chip elements 2 and 63. Note that the high level and low level periods of each liquid type correspond to the periods when each switch cord is closed and open, respectively. 600 is an example of the output waveform from the terminal 6, where the high level corresponds to a quasi-voltage level, and the low level corresponds to a signal component.
本実施例の基本動作は第1および第2実施例と全く一様
であるから、ここでは各スイッチ素子の開閉状態と各ユ
ニットからの信号続出し一序について簡単に説明する。Since the basic operation of this embodiment is completely the same as that of the first and second embodiments, the open/close states of each switch element and the order in which signals are successively outputted from each unit will be briefly explained here.
今期間6(11で、第11F目のグー、夕のユニ、 )
101,103のスイッチ素子lOみが閉じており、
他のプロ、りのユニットのスイッチ素子1は全部開いて
いる。該期間601でスイッチ素子201,202,2
03カそれぞ;1L401,402゜403で示すよう
に順次IjI閉する。各スイッチ素子201、!Oれ2
03 が順次閉じて次に開いた後、スイッチ素子2,
62により第12図の回路は毎回曽セットされる。従っ
て、第1着目のブロックにあるユニ、 ) 101,1
03の信号は600で示すよ5に順次端子6より読み出
される。該第111目のブー、りのm#目のユ=、、)
O1J号が挽み出された後1次の期間602では砿講l
膏目のプロ、りのスイッチ索子1が開いて、第24目の
プロ、りのユニット111,113のスイッチ索子lが
閉じる。一方、スイy+1子201,202,203
a*sa同様順次閉じた後間いくから稟12図の回路は
そのたびにす七、トされる。従って、該期間602では
第21I目のグー、りのユニ、 ) 111,113か
ら順次信号が疏み出される。以下、同様に第n着目のプ
ρ、りのユニ、トからも順次読み出される0次に第1番
目のプロ、りのユニ、トからの信号読み出しへ再び戻る
。以後これを繰り返えすことにより光信号O頑vC読み
出しを行ない複数個の該ユニ、トのセンサから同時に信
号を吠み出すことはない。This period 6 (at 11, 11th floor goo, evening uni, )
Switch elements 101 and 103 are closed,
The switch elements 1 of the other professional units are all open. During the period 601, the switch elements 201, 202, 2
03 respectively; 1L 401, 402, 403, IjI are closed in sequence. Each switch element 201,! Ore2
03 are sequentially closed and then opened, the switch elements 2,
62, the circuit of FIG. 12 is set to zero each time. Therefore, Uni in the first block, ) 101,1
The signal 03 is sequentially read out from the terminal 6 at 5 as indicated by 600. The 111th Boo, Rino's m# Yu=,,)
In the first period 602 after the O1J was extracted, the
The switch cable 1 of the second professional unit opens, and the switch cable l of the 24th professional unit 111, 113 closes. On the other hand, Sui y + 1 child 201, 202, 203
As with a*sa, the circuit shown in Figure 12 is closed each time because it is closed sequentially. Therefore, in the period 602, signals are sequentially output from the 21st I-th goo, Rinouni, ) 111, 113. Thereafter, the process returns to the signal readout from the 0th-order first program, unit, unit, and g, which are sequentially read from the n-th program ρ, unit, and unit of interest. Thereafter, by repeating this process, the optical signals are read out and signals are not emitted from the sensors of a plurality of units at the same time.
以上:&明した通り1本発明によれば、出力ライン5の
極めて大きなコンデ/すに信号電荷は全く蓄積されるこ
とはない。従って、本発明は従来の検出回路の出力信号
が重めて微少であったとか。As stated above, according to the present invention, no signal charge is accumulated in the extremely large capacitor of the output line 5. Therefore, in the present invention, the output signal of the conventional detection circuit is significantly smaller.
疏み・出しS度が極めて遅かったという出力ラインのコ
ンデンサの容量値が極めて大きいことに起因した欠点を
完全に除去でき、さらに−めで大きな出力信号を得るこ
とができるという優れ九幼果を有する。さらに出力信号
が大きいから、バッファ回路や増幅回路など複雑な信号
9&jI111w11に必賛としない。このため回路が
簡単vc itす、消貴鴫力や雑音の増加を阻止できる
。またフィードスルーやスイ、千ング雑會の影#を健め
て小嘔くできるのでダイナミックレンジは大幅に拡大さ
れる。さらに信号dみ出しの速度が早いから、信号の完
全dみ出しとII6遍―作ができ葛といっ九優れた効果
が生じる。It can completely eliminate the drawback that the output line's capacitance value is extremely large, such as the extremely slow rate of cutting and output, and also has the nine outstanding benefits of being able to obtain a large output signal at a very low speed. . Furthermore, since the output signal is large, complicated signals such as buffer circuits and amplifier circuits are not recommended. Therefore, the circuit can be simplified, and an increase in noise and noise can be prevented. In addition, the dynamic range is greatly expanded because the shadows of feedthrough, switching, and noise can be suppressed. Furthermore, since the speed of the signal d-projection is fast, it is possible to completely d-project the signal and produce an excellent effect.
以上、異体的な実施例をあげて本発明を説明し丸、上記
では動作の方法やスイッチの開閉のタイ1ノダは一例を
示し丸ものでうって、本発明の機峻が満足されれば、上
記の一例に限定されることはない、ホトセンサ(ホトダ
イオード)の!l!明に用いた等価ダイオードの向き(
極性)あるいは電圧源、基準電圧源の大きさおよびその
411性も一例であって、これに限定されない、実施例
に用いたスイッチ素子はスイツナング砿噛があればどの
ようなスイッチでも良い、例えば、トランジスタ、FE
T轡がある。また本発明の検出回路はスイッチを順次開
閉走査する走査回路と同一の半導体基板上に形成されて
も小まわない。In the above, the present invention has been explained with reference to different embodiments, and in the above, the method of operation and the tie 1 node of opening and closing of the switch are only one example. , but not limited to the above example, of photosensors (photodiodes)! l! The direction of the equivalent diode used in the description (
The polarity), the voltage source, the size of the reference voltage source, and their characteristics are also examples, and are not limited to these.The switch element used in the example may be any switch as long as it is a Swiss-Nang switch, for example, transistor, FE
There is a T-shirt. Furthermore, the detection circuit of the present invention may be formed on the same semiconductor substrate as the scanning circuit that sequentially scans the switches to open and close them.
第1図は従来の検出回路、第2図、43図はセンナの等
価回路、第4−は第1図の等価回路、第5図は第4図の
スイッチの開閉と411号のタイミング、第6図は他の
従来の検出回路、第7図は第6図のスイッチの開閉と信
号のタイζング、t48図は本発明に係る第1実施例を
不す検出回路、第9図は第8図の検出回路を駆−するス
イッチ開閉のタイミングと信号波形の一例を示す図、!
@10図は同じく、本発明に係るtjk2実施例を示す
検出回路、J%11図は第1θ図の検出回路を駆動する
スイッチの開閉のタイミングと信号波形の一例を示す図
、第12図は同じく本発明に係る第3央厖例を示す檎出
回1M、譲13図は第12図の膚出l路を駆wbするス
イッチの開開のタイミングと信号波形の一例を示す図で
ある。1,2,63,201゜202.203はスイッ
チ素子、3はセンナ、4#′i配線、5は出力ライン、
6L出力端子、7は゛電圧源、31はダイオード、32
,41,50,51゜62はコンデンサ、33はa仇素
子、34は電流−160は槓分崗路、61 dOP A
mp、 64 t;l1jii準電圧源、81 、82
、83 、101.It)3,111゜113.12
1,123はユニ、トである。
第1図
第2図
w、J3図
窮4図
第5図
6
415
′#16図
第7図
24 25 25第8図
第9図
81 82 83 84 85#+10
図
一一一一一一」l−一一一一一
1
第12図
w113図
1−= ++−二一一一「−一し−
601602603Figure 1 is a conventional detection circuit, Figures 2 and 43 are Senna's equivalent circuit, Figure 4 is an equivalent circuit of Figure 1, Figure 5 is the opening/closing of the switch in Figure 4, the timing of No. 411, and the 6 is another conventional detection circuit, FIG. 7 is the opening/closing of the switch and signal timing shown in FIG. A diagram showing an example of the switch opening/closing timing and signal waveforms that drive the detection circuit in Figure 8!
Similarly, Figure 10 is a detection circuit showing the tjk2 embodiment according to the present invention, Figure J%11 is a diagram showing an example of the opening/closing timing and signal waveform of the switch that drives the detection circuit in Figure 1θ, and Figure 12 is a diagram showing an example of the signal waveform. FIG. 13 is a diagram showing an example of the opening/closing timing and signal waveform of the switch that drives the skin exit I path shown in FIG. 12. 1, 2, 63, 201゜202.203 is a switch element, 3 is a sensor, 4#'i wiring, 5 is an output line,
6L output terminal, 7 is voltage source, 31 is diode, 32
, 41, 50, 51゜62 is a capacitor, 33 is an a-d element, 34 is a current -160 is a branch circuit, 61 dOP A
mp, 64 t; l1jii quasi-voltage source, 81, 82
, 83, 101. It) 3,111°113.12
1,123 is uni, t. Fig. 1 Fig. 2 w, J3 Fig. 4 Fig. 5 Fig. 6 415 '#16 Fig. 7 Fig. 24 25 25 Fig. 8 Fig. 9 81 82 83 84 85 #+10
FIG.
Claims (1)
放電させるスイッチ素子が接続されたユニ、)と、少な
くてもコンデンサ・、スイッチ素子および演算項−湯を
含む積分回路倉−え、該ユニットの鎮スイ、チ巣子偵の
端子と跋槓分回麺の反転入力端子が配線静4番皺を甘む
出力ラインを介して接続され、練ユニ、トのホトダイオ
ード關の端子が゛電圧源に接穂され、譲噴分回路の非反
転入力端子が基準電圧源に接続され、−積分回路の反転
および非反転入力端子かスイッチ素子を介して装線され
でいることを待歇とする光信号検出回路つ λ 複数個の―紀ユニ、トと繭記積分−路に儂え。 該各ユニットのスイッチ本子傭の端子を互いに接続する
と共に、シ趨子と該積分回路の非反転入力端子を出力ラ
インを介して接続し、該ユニ、トのホトダイオード側の
端子を互いに接続した上載端子と電圧龜を接続し、該積
分回路の非反転入力端子と基準電圧源をIi!続し、該
積分回路0[転および非反転入力端子がスイッチ素子を
介して接続されていることを特徴とする光信号検出回路
。 1 ■個(m=正整数)の前記ユニットで構成されるグ
ー、りが膳*(m=正整数)と、前記積分回路と1Ml
のスイッチ素子、第2のスイ。 チ素子、・・・・・・第1のスイッチ素子の合1m11
#のスイッチ素子を備え、皺各プロ、りのs1番目のユ
ニット内のスイッチ索子側や端子を互いにII統した上
載端子と賦第1のスイッチ素子の一方0@をII続し、
該各ブー、夕の第2番目の二品、ト内Oスイ、チ索子側
の端子を互いに接続し九上該端子と該第20スイ、チ素
子の一方の端金*ML、以下一様に、該各グ―、夕のm
番目のユニット内のスイッチ素子−の端子金工いKJI
続した上載端子と該第mのスイッチ素子の一方の端を接
続し、該1.第2、・・・・・・tsmのスイッチ素子
の他方の端を互いに接続した上載噌と線積分回路の反転
入力端子を出力ラインを介して接続し、該ユニ、トのホ
トダイオード側の端子を互いに接続した上載端子と電圧
源を!#続し、該積分回路の非反転入力端子と基$電圧
源を接続し、該積分回路の反転および非反転入力端子ρ
;スイッチ素子を介して#繞されていることを特徴とす
る元14号検出回路。[Claims] 1. A unit connected to a photodiode and a switching element for repeatedly photodischarging the photodiode; The unit's terminals and the inverting input terminals of the unit are connected via the output line that connects the fourth wrinkle of the wiring, and the terminals of the photodiode of the unit and the terminal of the unit are connected to the voltage. - the inverting and non-inverting input terminals of the integrator circuit are wired through the switching element; Optical signal detection circuit λ A plurality of -ki unit, t and cocoon integral - path. The terminals of the main switches of each unit are connected to each other, the non-inverting input terminal of the integrator and the integrating circuit are connected via an output line, and the photodiode side terminals of the units are connected to each other. Terminal and voltage pin are connected, and the non-inverting input terminal of the integrating circuit and the reference voltage source are connected to Ii! Next, an optical signal detection circuit characterized in that the inverting and non-inverting input terminals of the integrating circuit 0 are connected via a switch element. 1. A group consisting of ■ units (m = positive integer) of the above-mentioned units, the above-mentioned integrating circuit, and 1 Ml
switch element, second switch. 1m11 total of first switch elements
Equipped with a switch element of #, the upper terminal of which the switch cable side and terminals in the first unit of the wrinkles are connected to each other and one of the first switch elements is connected to one another,
Connect the terminals of the second two parts of each boot, the inner O switch, and the chain element side to each other, and connect the terminal on the upper side and the terminal metal of one of the 20th switch and the element *ML, hereinafter one. Like, each group, evening m
Terminal metalwork of switch element in the second unit KJI
Connect the above-mentioned terminal connected to one end of the m-th switch element, and The other end of the switch element of the second...tsm is connected to the upper mounting plate and the inverting input terminal of the line integrating circuit via the output line, and the terminal on the photodiode side of the unit is connected to the inverting input terminal of the line integrating circuit. Connect the above terminals and voltage source to each other! #Continuously, connect the non-inverting input terminal of the integrating circuit to the base voltage source, and connect the inverting and non-inverting input terminals of the integrating circuit to
; An original No. 14 detection circuit characterized in that it is connected via a switch element.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP56169148A JPS5870133A (en) | 1981-10-22 | 1981-10-22 | Detecting circuit for light signal |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP56169148A JPS5870133A (en) | 1981-10-22 | 1981-10-22 | Detecting circuit for light signal |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| JPS5870133A true JPS5870133A (en) | 1983-04-26 |
| JPH0381091B2 JPH0381091B2 (en) | 1991-12-27 |
Family
ID=15881169
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP56169148A Granted JPS5870133A (en) | 1981-10-22 | 1981-10-22 | Detecting circuit for light signal |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPS5870133A (en) |
Cited By (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPH05133801A (en) * | 1991-11-12 | 1993-05-28 | Hamamatsu Photonics Kk | Photodiode array type photodetector and photodetecting method |
| JP2002340670A (en) * | 2001-05-14 | 2002-11-27 | Hamamatsu Photonics Kk | Photodetector |
| JP2009004935A (en) * | 2007-06-20 | 2009-01-08 | Renesas Technology Corp | Semiconductor integrated circuit and ic card using the same |
Citations (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS55116226A (en) * | 1979-03-03 | 1980-09-06 | Hitachi Ltd | Discharging current integration-type photodetector |
-
1981
- 1981-10-22 JP JP56169148A patent/JPS5870133A/en active Granted
Patent Citations (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS55116226A (en) * | 1979-03-03 | 1980-09-06 | Hitachi Ltd | Discharging current integration-type photodetector |
Cited By (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPH05133801A (en) * | 1991-11-12 | 1993-05-28 | Hamamatsu Photonics Kk | Photodiode array type photodetector and photodetecting method |
| JP2002340670A (en) * | 2001-05-14 | 2002-11-27 | Hamamatsu Photonics Kk | Photodetector |
| JP2009004935A (en) * | 2007-06-20 | 2009-01-08 | Renesas Technology Corp | Semiconductor integrated circuit and ic card using the same |
Also Published As
| Publication number | Publication date |
|---|---|
| JPH0381091B2 (en) | 1991-12-27 |
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