JPS5870631A - Signal detecting circuit - Google Patents

Abstract

PURPOSE:To realize a signal detecting operation with high accuracy, by applying a voltage corresponding to an offset voltage to an antiphase input terminal of a differential amplifier. CONSTITUTION:When a clock phi1 is set at ''L'' level and a clock phi2 is at ''H'' level, a normal-phase input terminal of a differential amplifier 4 is grounded and a charge corresponding to an offset voltage of the differentral amplifier 4 is stored in a capacitor 17. When the clock phi1 is ''H'' level and the clock phi2 is ''L'' level, an input signal is added with an offset voltage by the capacitor 17 and is given to a normal-phase terminal 14 of the differential amplifier. In the differential amplifier 4, a signal inputted to the antiphase input terminal is shifted so as to be canceled with the offset voltage and compared with a detected voltage. Thus, the effect of the offset voltage can be eliminated.

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a signal detection circuit suitable for integration that can compare the voltage of an input signal with a detection voltage and detect it with high accuracy.

FIG. 1 shows a conventional signal detection circuit. This circuit has been commonly used in waveform shaping circuits such as limiters. l is a signal input terminal, that is, a negative-phase input terminal of a differential amplifier, ko is a positive-phase input terminal of a differential amplifier, 3 is an output terminal of a signal detection circuit, ≠ is a differential amplifier, i A is a first and a second terminal, respectively. , and 7 is the ground terminal. Since positive feedback is now applied to the differential amplifier ≠, output 3 is the high level saturation voltage ■ of the differential amplifier. Or low level saturation [pressure V. − becomes. The detection voltage of the signal detection circuit, that is, the voltage of the positive phase input terminal λ of the differential amplifier≠, is V at output 3. + when + vTif--knee vo, output J kaV, -oto*, r
t+r! It is given that vTH7≠r-”-.If the voltage of the input signal V□ is higher than the detection voltage of the signal detection circuit, the output 3 of the signal detection circuit is equal to the low level saturation voltage VO of the differential amplifier.
− becomes. Next, when the voltage of the large sword signal V becomes smaller than the detection voltage VTR- of the signal detection circuit, the output 3Fi is inverted and becomes the high-level saturation voltage V of the differential amplifier. It becomes +.

Therefore, the detection voltage of the signal detection circuit is
The voltage of the input signal VIM is the detection voltage vTi of the signal detection circuit.
! The output 3 of the differential amplifier is not inverted and remains at +VO until it becomes greater than +VO. Next, when the voltage of the input signal VrM becomes larger than the detection voltage vTH+ of the signal detection circuit,
The output 3 of the differential amplifier is inverted to V. - and 9, the same operation is repeated. FIG. 2 shows the waveform of the output of the signal detection circuit (output of the differential output circuit) when a sine wave input signal is applied. Here, if an AC signal is given where the maximum amplitude voltage of the input signal is smaller than the detection voltage of the signal detection circuit, the output 3 of the differential amplifier will be the initial voltage vo+ of the output 3.
Or it will remain as vo'''.As mentioned above,
The detection voltage of the conventional signal detection circuit is determined by the saturation voltage of the differential amplifier and the resistance division ratio. Therefore, the conventional signal detection circuit has a drawback that once the power supply voltage of the differential amplifier is determined, the high-level detection voltage vTII+ and the low-level detection voltage V- of the signal detection circuit cannot be independently set. That is, when the detection voltage on the high level side of the signal detection circuit is set, the resistance division ratio (first and second resistance values) is determined by the high level saturation voltage value of the differential amplifier/device. Therefore, the detection voltage on the low level side is determined by the previously determined resistance division ratio and the low level saturation voltage value of the differential amplifier. Furthermore, when integrating conventional circuits, the following drawbacks have been encountered. In order to obtain high accuracy of the detection voltage of the signal detection circuit, we needed a resistor with high specific accuracy and a differential amplifier that could obtain an accurate saturation voltage throughout the design. Furthermore, resistance.

Differential amplifiers were required to have characteristics with very little change over time. There was also a problem in terms of compatibility between power consumption and reduction of occupied area. That is, in order to reduce the current flowing through the resistor, a high resistance is required, but a large area is required to integrate the high resistance.

Rounding to eliminate the above-mentioned drawbacks The inventor of the present invention previously invented and applied for a signal detection circuit using a highly accurate and stable reference voltage source (Japanese Patent Application No. 1986/Hiroshi≠72). This signal detection circuit is shown in FIG.

In Fig. 3, l is the signal input terminal, that is, the negative phase input terminal of the differential amplifier, ko is the positive phase input terminal of the differential amplifier, 3 is the output terminal of the signal detection circuit, 蓼 is the differential amplifier, and t is the first input terminal. The input terminal of the reference voltage vrl (high level side reference voltage) is the second reference voltage vrB (low level side reference voltage)
, to and it are switches, 12 is an inverter, and 12 is an output terminal of the /3d inverter. Here ■1, >
It is vrs.

Next, the operation of the signal detection circuit shown in FIG. 3 will be explained. Now assume that the output terminal 3 of the differential amplifier≠ is at a low level.

When the switches to and it are turned on when the control terminals 3 and 13 are at a high level and off when they are at a low level, when the output terminal 3 is at a low level, the voltage at the positive phase input terminal of the differential amplifier becomes the second reference voltage Vr. , becomes. That is, the detection voltage of the signal detection circuit in this case is 1. Input signal■□
When the amplitude voltage of , is larger than the detection voltage vr of the signal detection circuit, the output 3 of the differential term width amplifier maintains a low level state. Next, when the amplitude voltage of the input signal V becomes smaller than the detection voltage V4, the output 3 of the differential amplifier is inverted and becomes a high level, and the voltage at the positive phase input terminal of the differential amplifier becomes the first reference voltage vr1. Therefore, the detection voltage of the signal detection circuit is vr
Changes to l. Here, the output 3 of the differential amplifier remains at a high level until the amplitude voltage of the input signal vxM becomes larger than the detection voltage vr0. Next, the amplitude voltage of the input signal is vr
When the voltage becomes larger than o, the output 3 of the differential amplifier is inverted and returned to the initial low level state, and the same operation is repeated thereafter.

Here, if an AC signal is given where the maximum amplitude voltage of the input signal is smaller than the detection voltage of the differential amplifier, the output 3 of the differential amplifier
is in the initial high level output or low level output state until t.

Therefore, since the operation is performed as described above, a highly accurate and stable reference voltage can be used as it is as a detection voltage. Here, a highly accurate and stable reference voltage is fully achievable with current integrated circuit technology, and differential amplifiers, switches,
Signal inversion circuits can be easily integrated. Furthermore, since a resistance element unlike the conventional circuit shown in FIG. 1 is not used, it is advantageous in reducing power consumption. However, despite having these advantages, the signal detection circuit shown in FIG. 3 has the disadvantage that it cannot detect signals with high precision due to the offset voltage of the differential amplifier. That is, since the differential amplifier shifts the signal voltage by the offset voltage and compares it with the detection voltage due to its own offset voltage, accurate signal detection cannot be performed. Generally, a differential amplifier has an offset voltage due to element variations, and with current integrated circuit technology, it is extremely difficult to completely reduce this offset voltage to 0. , the operation period of the signal detection circuit is divided into offset correction operation and signal detection operation,
The drawings will be described in detail below using sample values.

The reference figure shows an embodiment of the present invention, where l is a signal input terminal;
2 is the positive phase input terminal of the differential amplifier, 3 is the output terminal of the signal detection circuit, day is the differential amplifier, r#'i first reference voltage Vr
1 (/・reference voltage on the high level side) input terminal, ri is the input terminal of the second reference voltage vrS (low level (111 reference voltage)), 10. // is the switch, 12 is the inverter, 13 is the input terminal The second output terminal, /4, is the negative phase input terminal of the differential amplifier, that is, one end of the first capacitor 17, 12
is the output of the differential amplifier, 16 is the other end of the first capacitor 17, /
7. /I is the capacity of the first whistle and whistle 2, respectively, and 20 to 2j are switches. Here, V, > V,. Next, the operation of the signal detection circuit according to the embodiment of the present invention will be explained.

Switches 20, 22, and 21 are driven by clock φ1, and switches 2/ and 23.2≠ are driven by clock φyo. The phase relationship between the clock φ1 and the φ family is given so that their respective states (switch-on states) do not overlap with each other, as shown in Figure 5, for example. First, a case where the clock φ is at a low level and the clock φ2 is at a high level will be described.

In this case, to simplify the explanation, consider a switch with ideal characteristics, and the resistance of a switch that is always on is 0.
．． Since the resistance of a switch that is always in the OFF state can be considered infinite, the circuit shown in Fig. 6 becomes equivalent to that shown in Fig. 6. The output 3 of the signal detection circuit holds the voltage determined by the charge accumulated in the second capacitor jkl, that is, the voltage immediately before the switch 2j is turned off. Even if there is charge leakage in the capacitor, if the signal at output 3 is handled digitally, the voltage level at output 3 must fall below the digital signal threshold level by the next signal detection cycle. There is no problem in operation. The positive phase input terminal of the differential amplifier is grounded, and the output /j of the differential amplifier is fed back to the negative phase input terminal l≠. Therefore, the first capacity 1
7, a charge force corresponding to the offset voltage Voff of the differential amplifier is accumulated. Next, the operation when the clock φ is at the high level and the clock φ is at the low level will be described. In this case, the circuit in diagram Bgc is equivalent to the seventh
It will look like the figure. If the tsl capacitor connected between the input signal terminal and the negative phase input terminal and the λth capacitor provided between the output terminal 3 and ground are removed, the circuit is operationally equivalent to the signal detection circuit shown in Fig. 3. Become. Here, the λ-th capacitor provided at the output terminal 3 is a capacitor for holding voltage, and does not affect the operation of the signal detection circuit. First, the input signal is transmitted to the negative phase input terminal 1 of the differential amplifier with an offset voltage added to the first capacitor. Next, within the differential amplifier, the signal input to the negative phase input terminal is shifted in a direction to cancel the offset voltage and compared with the detected voltage. Therefore, since the circuit operates in this manner, accurate voltage comparison can be performed. The circuit operations other than those described above are the same as the circuit operations shown in FIG. 3, so the explanation will be omitted. Next, clock φ1 is at low level again, and clock φ! At the high level, the output terminal 3 retains the voltage immediately before the end of the detection operation as described above, and the offset voltage correction operation is performed.
Thereafter, the same operation is repeated. Therefore, since such an operation is performed, an accurate detection operation can be performed without being affected by the offset voltage of the differential amplifier. In the circuit of the present invention, the input signal is treated like a sample value. That is, the offset correction operation period (clock φ1 is low level, clock φ
, is at a high level (m), no signal detection is performed and the output terminal 3 maintains the state at the end of the previous signal detection operation. Therefore, in this case, the clock φ1. It is necessary to drive φ.

Figure 5 shows the λth embodiment of the present invention, and the same parts as in Figure 1 are denoted by the same reference numerals. 2B is a switch, and 27.21 is an inverter. The configuration is exactly the same as that in FIG. f except that the capacitor in FIG.

That is, with such a configuration, the voltage can be maintained without the problem of charge leakage as shown in FIG. The operations other than the voltage holding circuit are completely the same as those shown in FIG.

Fig. 3 shows a third embodiment of the present invention, and the same parts as in Fig. r are denoted by the same reference numerals. λ' indicates a terminal from which the 16th or second reference voltage is taken out as an output, 2 indicates a buffer circuit, and so, and it indicate the third and Vth reference voltages for driving the buffer circuit, respectively. . The operation of the circuit shown in FIG. 2 except for the buffer circuit and latch circuit is exactly the same as that of the circuit shown in FIG. The buffer circuit 2yFi is driven by the third reference voltage vr21 and the third reference voltage Vr4, and operates so that the output amplitude voltage of the buffer circuit is vr3 on the high level side and vr4 on the low level side. However, vrB > Vr4. That is, such a buffer circuit can be easily realized with an OMOS circuit. Therefore, since the signal detection circuit is configured in this way, by using the highly accurate and stable third and third reference voltages, a waveform-shaped output with a constant amplitude can be obtained from the output 17 of the buffer circuit. . A waveform-shaped output with a constant amplitude is also obtained from 2'.

As explained above, there is an advantage that a highly accurate and stable reference voltage can be used as it is as the detection voltage of the signal detection circuit. Further, since the operation period of the signal detection circuit is divided into an offset correction operation and a signal detection operation, and a sample value operation is performed, there is an advantage that the offset voltage of the differential amplifier can be corrected and a highly accurate signal detection operation can be obtained. Furthermore, by using the circuit of the present invention and configuring it as shown in FIG. 2, a highly accurate and stable waveform shaping circuit can be constructed.

Furthermore, since there is no resistance component unlike conventional circuits, there is an advantage that a signal detection circuit with low power consumption can be integrated. The waveform shaping circuit using the present invention can be applied to a limiter and a detector circuit of a PB (push button) receiver, and can be applied to a high-performance P7-button receiver.
The O

[Brief explanation of the drawing]

Figure 1 shows the conventional signal detection circuit, Figure 2 shows the output waveform of the conventional signal detection circuit when a sine wave input signal is given, and Figure 3 shows the output waveform of the conventional signal detection circuit when a sine wave input signal is applied.
The figure shows a conventional signal detection circuit, the figure ≠ shows a signal detection circuit according to the first embodiment of the present invention, and the figure 5 shows the phase relationship of drive clocks used in the signal detection circuit of the present invention. FIG. 7 shows an equivalent circuit of the signal detection circuit of FIG. μ during offset correction and signal detection, respectively, and FIGS. . l... Signal input terminal, 2... Positive phase input terminal of differential amplifier, 2'... Terminal from which the first or λ reference voltage is taken out as output, 3... Signal detection circuit output terminal, ≠...differential amplifier, j, 6...resistance, 7...ground terminal, g...first reference voltage, ri...second reference voltage, to, it ...Switch 'f-1/2...Inverter, /3...Inverter output terminal, lq...
anti-phase input terminal of the differential amplifier (one end of the first capacitor), lj
. . . Output of differential amplifier, /G . . . Other end of first capacitor, /7. tr...@l and WJ2 storage, 20-2
1. ...Switch, 27.21...Inverter, Kota...Buffer circuit, 30...Third reference voltage, 3
/... @≠ reference voltage. Figure 1

Claims (3)

[Claims] (1) A differential amplifier in which one end of a capacitor is connected to the negative-phase input terminal of the differential amplifier, and first and second switches that select and connect either an input signal or a ground potential to the ground potential of the capacitor. , third and third switches that select and output one of λ different reference voltages, and an output obtained by the third and V switches to the positive phase input terminal of the differential amplifier. You can select and connect either voltage or ground potential! and a sixth switch, a seventh switch connected between the output terminal and the negative phase input terminal of the differential amplifier, an r-th switch connected to the output terminal of the differential amplifier, and a seventh switch connected to the output terminal of the differential amplifier. a circuit that has a function of storing and holding the output information obtained from the switch; and when the output of the circuit having the function of storing and holding is at a high level, the reference voltage on the high level side is selected from the two different reference voltages. K, a circuit that controls the third and μth switches so as to select a reference voltage on the low level side from among the two different reference voltages when the output of the circuit having the storage and holding function is at a low level; and the first. A signal detection circuit comprising means for driving the second and j-th to t-th switches with a periodic clock. (2) The signal detection circuit according to claim 1, wherein the circuit having the function of storing and retaining is constituted by a capacitive element. (3) The signal detection circuit according to claim 1, wherein the circuit having the function of storing and retaining data is constituted by an inverter and a switch.