JPS5871664A - Semiconductor device - Google Patents

Abstract

PURPOSE:To form a solid state display unit for a plane television in lieu of a cathode ray tube by forming other insulating gate type semiconductor device and other inverter and resistor on the same substrate to construct a decoder and a driver on the same substrate. CONSTITUTION:A gate insulated film 16 is formed as an isolation film for S1(12) and S3(15), electrode holes 8, 7 are respectively formed for the S1(12) and S3(15), and a metal or semiconductor layer connected to the gate electrode is again laminated. Then, the film is selectively etched, a gate electrode 17 is laterally laminated on gate insulators 16, 16', and wirings are simultaneously formed in contact with the surface of the substrate or an insulator 6 through the electrode holes to IGF, capacitor and resistor of other unit via the S1(12), S3(15). In this manner, a source or a drain is formed via the S1(12), S2(14) having a channel forming region 9, and a drain or a source is formed via the S3 (15), and a laminated IGF10 in which a gate insulator 16 is formed on the channel forming region side surface and a gate electrode 17 is formed, is constituted.

Description

Detailed Description of the Invention The present invention relates to a semiconductor device in which vertical channel type stacked type insulated gate type semiconductor devices are formed into a matrix on a substrate. The present invention relates to a stacked type insulated gate type field effect semiconductor device on a substrate. The present invention relates to a composite semiconductor device having a capacitor connected to the source or drain of the semiconductor device.

The present invention is characterized in that such a composite semiconductor device is provided on a substrate in a matrix structure, and a liquid crystal display type display device is provided. When a solid-state display device is provided in the present invention, the composite semiconductor device is provided in a parallel glass plate. By providing an electrode, this
A liquid crystal display device in which liquid crystal is injected between WL electrodes is known.

However, in this case, the limit for the number of picture elements in this display section is 20 to 200, and if it is more than that, the number of terminals that extend outside of this display section will be required as many as the number of picture elements. , it could not be put to practical use at all. For this reason, this display section has a plurality of picture elements, which are arranged in a matrix, and in order to control any picture element to turn it on or off, a field effect semiconductor device (referred to as G1) corresponding to that picture element is required. was needed. A control signal is then given to this IGIF to turn on or off the corresponding picture element.

The application of the present invention to Tate Channel Yako ()P and liquid crystal displays is disclosed in the patent application filed under the present invention (Insulated Gate Field Effect Semiconductor Device and Method for Manufacturing the Same) Japanese Patent Application No. 5
No. 6-001761 and Composite Semiconductor Device Patent Application 1973
No. 6-001768 (filed on January 9, 1981) The details are shown. The present invention is a further development of this.O This liquid crystal display section can be represented by a capacitor (hereinafter referred to as 0) as its equivalent circuit.

For this purpose, a book in which GIF and 0 are arranged in a 2×2 matrix structure (40) is shown in FIG.

In Figure 1, matrix 00) is one engineering GF (
10) and one 0 (31) constitute one picture element. 0 is connected to row K (5υ(5i) and the picked line, and the other gate is connected to create column 0υ0. It is something.

Then, for example, (5η(4℃ is "?" and the 6th 0 is 0'
2, it is possible to select only the address (II 1) and turn it on, and selectively turn on the liquid crystal display electrically shown isometrically as O(3]).

The present invention aims to provide another insulated gate type semiconductor device (60) and another inverter (6Φ, resistor (?O) on the same substrate in order to configure a decoder and a driver on the same substrate. By combining the present invention based on its design specifications, it was possible to create a solid-state display device for flat televisions that can replace cathode ray tubes.

Furthermore, a display device for a calculator should use 1♂~10S picture elements (for 'rV, 10~101 [i, for example, 26 x 10' picture elements should be provided on the same board, and around it. It can be seen that the necessary decoder and driver can be made using a GIF, an inverter, and a resistor that are formed at the same time.

The present invention relates to a stacked workpiece gateway necessary for making such a system and nine picture elements connected to the liquid crystal display section.

FIG. 2 shows a vertical sectional view of the stacked IGF of the present invention and its manufacturing process.

In the drawings, a first semiconductor (2) having P or N type conductivity on an insulating substrate, such as a glass or alumina substrate.
(hereinafter simply referred to as 81) was formed. This °81 (2)
This was patterned into an arbitrary shape using the first photomask (2) to form, for example, a lead having a lateral conductivity type. Furthermore, a second intrinsic or N- or P'' type semiconductor (4) (hereinafter simply referred to as 82) was formed on this 81 (2).It further formed a pair with the first semiconductor to form a source and a drain. In order to achieve this, a third semiconductor (5) (hereinafter simply referred to as s3) having the same conductivity type as 81(2) was provided in a stacked manner.

The semiconductor is formed on a substrate using a silane glow discharge method or an arc discharge method at a temperature of room temperature to 500°C, and is amorphous or microscopic with a size of 5 to 100 μm. A so-called non-single crystal conductor in silicon having a crystalline semi-amorphous (semi-amorphous or 60 to 600 μm microcrystalline) structure is used. In the present invention, a semi-amorphous semiconductor (hereinafter referred to as 8
The main focus is on MU S). Regarding this 8A8, patent M (patent application No. 55-02638
Application No. 8853.5.3 Semi-amorphous rapid deformation body)K Detailed examples thereof are shown.

Furthermore, in order to further reduce the parasitic capacitance in Figure 2 (φ) on top of s 3 (5) in which 83 is selected using a photomask ■ using photolithography technology in Figure 1, a thick insulating film is formed using the IIPOVD method (depressurized pressure reduction). A silicon oxide film may be formed to a thickness of 0.3 to 1 μm by vapor phase method) or plasma OVD method. Also on this day, 3rd and 4th CMo,
Add a conductive layer of Si, S1, etc. to W and M by 0.2 to 0.6μ.
It was effective for forming a matrix to improve the 4'Jl ratio of 83 by adding 810 to 0.5 to 1 μm on top of the 810.

In addition, in FIG. 2 CB), the side surface may be formed perpendicularly to the surface of the substrate (1), but the side surface may be formed by tapered etching in a trapezoidal shape.
Furthermore, it was effective to remove the step cut at the step portion of the stacked gate electrodes. S
ji! , an insulating film (6) was formed on the entire surface of the 830. This insulating film has a frequency of 13.56MHg to 2.45GHz
Electromagnetic energy with a frequency of
It was soaked and oxidized to a thickness of 200-2000 µm.

%, if the substrate is made of glass, there is a high possibility that mobile ions such as sodium contained therein will diffuse into the gate insulating film over a long period of time. Therefore, this insulating film is made of silicon nitride (81A, 06xl) t
or silicon carbide (81x(b.

It is extremely important to use O≦x(1), etc.

Therefore, the silicon nitride film was manufactured as follows. That is, to silane ψ1 or BitI9 and microwave (2
, 46 (+HM) K, ionized ammonia or nitrogen is introduced into a reactor maintained at 0.1 to 0.5 torr, and the temperature is set at 200 to 500°C, typically 300＠O. on the heated substrate outside the reactor.
By using a two-stage plasma OVD method in which a second high-frequency plasma of 13.56 MHz is added, this non-single crystal semiconductor is dehydrogenated, especially on the periphery of the 132 (b) side. Low temperature (20
It was possible to form a gate insulating film with a thickness of 200 to 4000 μm. When the nitride gas was sufficiently ionized by heating it with microwaves (50 to 300 W) K, a film was formed on the inside of the associated silane.

Regarding 81xO1, (Ox(1), plasma OvD method is used when making it into an insulator. #, plasma OVD method (
It was possible to form this energy band width of 2.5 to 3.5·V at a substrate temperature of 200 to 40,060°C.

When the substrate is made of glass like this, the forming temperature is set to 200℃.
Considering that the semiconductor and substrate at ~400[deg.] O are not deteriorated, silicon nitride or silicon carbide is an extremely effective gate insulating film using the plasma O'VD method.

This gate insulating film OQ is simultaneously K5xQ4.53(XJ
It was also formed as an isolation film.

Furthermore, as shown in O)), the electrode hole (8) was formed at 83 points for 51 (6) using the third photolithography technique (3).
(Metal or semiconductor layer (P+ or N conductivity type silicon conductor or transparent conductive film such as BnOts) that forms an electrode hole (?) for one and connects to the gate electrode.
were layered again.

Next, this film is selectively etched using the fourth photolithography technique (2), and the gate electrode 071 is laminated in the horizontal direction on the gate insulating layer.
(Gas) and through the p-electrode hole to the other parts of the GF, capacitor, and resistor were closely connected to the substrate surface or the insulator (6).

When viewed from the lateral direction, the mou-7 in the vertical sectional view of FIG. 2(b) can be shown as FIG. 2(6). The numbers correspond to each other.

The semiconductor of the present invention mainly uses an 8A8 (D silicon conductor), which has a conductivity of 10 to 1o (icm), which is higher than that of single crystal silicon, compared to 10 to 10 (ac m)' of mu8. This is because the conductivity is close to that of a substantially intrinsic semiconductor without intentionally introducing impurities. However, the activation energy neutralized by boron is On the other hand, in the case of 818 has lattice strain and hydrogen for neutralization of dangling bonds with 0.1 to 6 molar proportions, prevents degassing of this hydrogen, and protects the substrate, semiconductor, and electrodes. - In order to reduce the stress caused by thermal expansion at the interface between different materials such as leads, all treatments should be carried out at 200-600°C or less, preferably 200-350°C or less, typically 300°C or less.

The gate electrode q may have a multilayer wiring structure in which a semiconductor of the same conductivity type as tl and 83 and a metal such as lICMo are used as a double structure.

In this way, the source or drain is formed by cutting the sg(t4) having the channel forming region (9), and the gate insulator αQ1 is formed on the side surface of the channel forming region, and the gate electrode CI is formed on the outer surface thereof. We were able to create a laminated type G1α0).

In this invention, the channel length is determined by 8 degrees ◆Y thickness, which is typically 0.3 to 3 μm here. The reason is that the mobility of non-single crystal semiconductors is different from that of single crystals, part 11.
5 to 1/1001. IG? This is due to the fact that it has promoted the characteristics of

In 8m8, the bulk mobility of electrons is 10 to 500
0 jV/B and 1/3 to 1/10, while that of the hole is 0.5 to 10001aV/B and 115 to 1/1
It is 100. However, amorphous silicon has electrons
, OWL~1. oom'v/s, *-le is O, O
Considering that it is 10 to 106 times longer than O1cmV/8 or less, we decided to use 8mm 8 having a microcrystal structure with a size of 6 to 100mm in the semiconductor device of the present invention and to make it a stacked type. Since the channel length can be as long as IP, a so-called microchannel structure can be achieved.
This is extremely important for high-speed response.

Furthermore, in the GP of the present invention, the electron mobility is 3 times higher than that of a single crystal, and 6 to 100 times higher than that of a hole, so it is extremely preferable to use an N-channel type.

In addition, since 82 is an N-type intrinsic semiconductor that does not have monovalent impurities such as boron added to its surface, it can be used as a P-type or engineering-type semiconductor by adding 0.1 to IOPPM at the same time when forming 82. Is the ninth N-channel IG that operates the liquid crystal panel of the present invention with a positive voltage? It was effective when

When a substantially intrinsic semiconductor (N-type) is used for the GIF 82 obtained in this way, an achannel IGIF has a double-enhancement type operation, and an N-channel IGIF has a depletion type operation. mode can be obtained.

If 2 is an intrinsic or #iP type semiconductor, then P
In Channel E G1, Depledge”!: / type, N
Channele G? In this case, an enhancement type operation mode can be obtained.

The process for obtaining the liquid crystal display shown in FIG. 1 (1F) is shown for the case where the enhancement type is an easy-to-use round when selecting the picture element, and the simple Cζ enhancement type operation is performed.

Gate 1! When the pole was set at 0° and the source or drain was set at 01°, a current flowed through the channel forming region (9) to create an on state, and if one or both of them were at 0, an off state could be created.

+1°keN? - For Y-channel type IGIF, the positive value is 0.5 to 10.
09 means Ov or a voltage below the threshold voltage.

P channel type engineering G? can be done by changing the polarity of the electrode.

These logic systems are the same in FIGS. 1 and 2 as well as in the embodiments of the present invention shown in FIGS. 3 to 5 below.

Also, when trying to create a peripheral decoder or general logic element in Fig. 1, for example, the resistance 00) is
The resistivity of the 82 bulk components is determined by the directional resistivity of the barrel, independent of the voltage applied to the gate. 81.82.135 may be stacked without providing a gate electrode. Further, this resistance value may be determined according to the design specifications based on the resistivity of 82, its thickness, and the area covered on the substrate.

In the inverter (60) in Fig. 1, the driver (6υ
is shown in Figure 2 (b), and its load (6th place is axo
It may be provided as an enhancement type or depletion type GF that connects n 53 (one of 12 and gate electrode a''/).

Furthermore, the output of this inverter (60) can be obtained by stacking two GIFs separately on this substrate (as shown in (62)), and the input part is connected to the gate electrode (corresponding to 1). Just set it up.

In the vertical channel type structure ( ) F of the present invention, even if light is irradiated from above or below this IGIF,
Since the conductor layer of 81.83 is Pl or t, the so-called 81.83, which has a structure that sufficiently absorbs this light and prevents it from reaching 82, has a light shielding effect at the same time.

Therefore, even if multiple pieces of this IP are manufactured on a glass substrate,
In particular, this 101K light can be turned on even without shielding.
O? ? This effect is IGIF
The shielding effect of this IGF itself is extremely high, since the purpose of the area without the IGF is to display light by transmitting and reflecting light vertically through the entire substrate including the liquid crystal. It has important characteristics.

This is a feature that has never been considered in conventionally known nine-lateral channel type TFTs (thin film transistors).

FIG. 3 shows another embodiment of the invention.

In Figure 3 ■, the conductive layer on the substrate (1) and 81 (2) laminated thereon have their i-lines in the lateral direction, and gay) (lη is also in the lateral direction, while ET1a→ This is the case when the wiring is perpendicular to the drawing.In the drawing, two of xey(1o)αd) are shown. However, it is also possible to form a matrix and arrange 1d to 109 pieces on the same substrate.

In the drawings, the numbers correspond to the embodiment of FIG.

In its manufacture, the photolithography mask may be of three types (■ to ■) with 0-gate conductive layers 071 and 83 (
In order to prevent the generation of parasitic capacitance between the conductive layer and the
Silicon oxide (3o) is laminated on top of the 8x0 to a thickness of 0.3 to 2μ. For manufacturing, this i-oxide (!So) is patterned, and further, using this silicon oxide as a mask, 81 and 82Q41 below it are etched to form 81.82 in the same shape.

FIG. 3 (9) shows an arrangement in which the IGF wiring is connected horizontally in the drawing (to 81 (6) and its conductive layer) and to contact (to 83)! The conductive layer (C) is wired in the horizontal direction, and the gate (B) is wired in the vertical direction perpendicular to the drawing, with the conductive layer spaced apart by the interlayer insulator @ and (C).

In the drawings, the conductive layer on the substrate (1)) was patterned with a mask 2, and B1 (6) was patterned with a mask 2. Further, 8264B3 (G) was laminated and etched using a self-aligned mask (3). After forming the gate insulator (2), the gate electrode (b) and its leads were formed on it (in addition, the interlayer insulator (c) was made of polyimide resin, pIC4, etc.).
o, after forming to a thickness of 5-2μ, contact hole ())
The second conductive layer a4 constituting the electrode/lead connected to the fabrication sheet 83 (c) was fabricated using a mask (2).

Corresponding to this drawing, FIG. 4 shows another embodiment of the present invention using a liquid crystal display. FIG. 3 (0) shows a first conductive layer on a substrate (1) and B1 ( 6) is shown in the horizontal direction (X direction) in the drawing using a mask (2).The ugly gate electrode/lead C1η is shown in the vertical direction (Y direction) in the drawing.

This is made by using the mask 2 for 8g and E13 in the engineering GIF (10), and using the mask 2 for the gate αη which is covered so as to straddle this S2α483 (g).

As described above, the process G1 of the present invention has a gate insulator (a gate electrode a on It has become possible to accept the above elements completely freely and form wiring in one direction, the X direction.This is compared to the conventional IGIF in which channels are formed in the horizontal direction.1. Semiconductor layer 81.82.83 using OVD method as the core
The engineering effect is extremely large.

Fig. 4 is a further development of Fig. 3 (9) and is used in a liquid crystal display. ◎ Fig. 4 shows another embodiment of the present invention, and the two The present invention is applied to a ×2 matrix cell.

In FIG. 4 CB), a first conductive layer (C) is formed on a glass substrate (1) to a thickness of 500-3000 μm in the KX direction. Even if this is a nine-transparent film using Nesa (8nQ), K B2 cough 83α→ is formed in the Y direction. Further, the gate electrode lead leakage is formed in the Y direction, and the electrode (c) of the liquid crystal capacitor (31) is formed of a transparent conductive film in contrast to 183 (g). There is also a transparent conductive film (2) on the lower surface of the upper glass substrate (to). This conductive layer @, 04 has a liquid crystal molecule alignment film or alignment treatment so that the liquid crystals are aligned at right angles to each other. Liquid crystal (C) is filled between these two transparent electrodes (C). For example, (,L
O) CL(0 and the capacitor (5) connected to its output
1) F (31) is shown in FIG. 4 (4) ((9) corresponding to FIG. 1 picture element is xmm'6 ri 1~16
It has become possible to make even 500 x 500 flat displays with 5 to 20 om's.

In Fig. 4, only one liquid crystal capacitor is used for the output of this IGF, but if a canister (32) is made in parallel to display the display time at the same time, as shown in Fig. 6. Become.

In FIG. 6, the liquid crystal part (c), upper electrode (b), and upper glass substrate shown in FIG. do it.

Figure 5 (4) is a plan view of the area corresponding to one picture element;
＠ is a 9-vert cross-sectional view at Muno, and (O) is a vertical sectional view at B-go, with corresponding numbers. Figure 5 (
As is clear from the shape of the GIF (10) in Fig. 0), the orientation to this IGF uses Fig. 3 (4) as the main element.

Capacitor for LCD display? ¥E pole (c) is B1 (6)
The structure is different from the case where it is connected to 83 (b) in Fig. 32) A second transparent conductive film 0''Q is provided on the gate electrode at the same time as the gate electrode to form a middle capacitor 02) in parallel with the electrode, which is part of the method for extending the display time of the liquid crystal display. In terms of the circuit, the capacitor indicated by the broken line in Figure 1 corresponds to the bag. Even if the on-time of the GIF is 10 to 1000/J seconds, the liquid crystal display is 1 to 1000/J seconds. This capacitor can have a so-called afterglow property that extends to -1 second.
This is effective in preventing the viewer's eyes from getting tired when the time reaches 0 microseconds.

Furthermore, since the product capacitor was made of the same material as the gate insulator O, it was possible to manufacture it in the same badge type without requiring any new process. However, in order to increase this capacity in a small area, titanium oxide, instead of silicon nitride,
Tantalum oxide and other ferroelectric materials may also be used.

Another electrode (C) electrically connected to 81α in the present invention is provided through an electrode hole (39).

A glabellar insulator such as polyimide or PIQ is provided on these IGIFs (10) to a thickness of 1 to 3μ, and selectively
It may be provided using photolithography technology. This electrode (the size of one picture element is determined according to the design specifications. In calculators, etc., it corresponds to one segment of 0.1 to 6 m♂ or a square or number. However, as shown in Fig. In the method of creating a scanning matrix structure, for example, 500
It may be set to X500. The liquid crystal display section has a glass plate (e) above the electrodes and a glass plate (e) having a transparent conductor such as a Nesa film on each electrode with a liquid crystal molecule alignment film formed on each electrode.
．． They were placed opposite each other with a gap of 1 to 2 mm, and, for example, nematic liquid crystal (c) was injected therein.

This display may also be displayed in color. Furthermore, for example, these picture elements may be stacked three times. Then, the three elements (red, green, yellow) may be arranged alternately.

As is clear from FIGS. 5 and 6, the present invention is characterized in that a plurality of GFs, capacitors, resistors, or a liquid crystal display flat panel is provided as a sandwich structure on the substrate (1).

Furthermore, as is clear from the drawings, EIS and 8111C automatically prevent light from irradiating the XGIF (10) and leaking when it is in the 9o degree state when the light is irradiated from above. In addition, it is an extremely significant feature that the GF is provided in a stacked manner, completely isolated from other picture elements, on an insulating substrate, which is different from the conventional method. The fact that the stroke can be made at a temperature of 600° or less, particularly 300'' or less, has the great feature that this panel is not easily affected by thermal strain even if it has a large area.

In addition, the semiconductor of the present invention mainly has a non-single crystal structure, and in particular, the semiconductor of the present invention has an intermediate structure between an amorphous and a single crystal called SM8, and is stable against thermal energy up to 600°0. Other characteristics of

In particular, this 81B is a non-single-crystal semiconductor with a large microcrystal structure lattice strain of 10 to 100 μm, and the manufacturing process requires 500 KH1! Even if induction energy of ~3 GHz is used, a temperature of up to 300°0 is sufficient, and in addition, the diffusion length of the electron Φ hole is 100 ~
It has a physical property of being 1d times larger. Due to the structure in which such non-single crystal semiconductors are stacked on a substrate, 918F
In addition, because the current flows in the vertical direction, microchannel type I with a channel length of 0.1 to IP
An extremely significant feature is that GIF can be created without using high-precision photolithography technology.

Furthermore, in the present invention, in view of the characteristics of the engineering GF, its threshold voltage Cv4J
For example, instead of doping by ion implantation,
Another feature is that the amount of impurity added to 2 and the high frequency power applied are controlled.

Therefore, the withstand voltage is 20~30'V%---%~4V ±0.
It was possible to control within the range of 2j. Furthermore, the frequency characteristics are 1/6 to 1/6 that of conventional single-crystal insulated gate type conductor devices because of the microchannel channel length of 0.1 to IP.
Even though a non-single-crystal semiconductor was used, the leakage of this IP junction or PM junction could be reduced by 1on even if K107 was added in the opposite direction. It was below. This was comparable to the reverse leakage of single crystals.0 or 81KFor example, when adding 2 to 20 moles of oxygen or nitrogen, and 5 to 30 moles of carbon, the structure shown in FIG. There was little leakage in the reverse direction, and over-etching of 81 during etching of 82 and 83 was prevented, which was favorable in terms of the process. This low leakage property is 1/1 compared to the case without additives.
The leakage was reduced by a factor of 10 to 1/xo'. It goes without saying that this reduction in leakage is extremely effective when implementing the matrix structure of FIG.

Furthermore, this reverse leak is caused by this laminated type 81.82.8
When both 3 and 3 were made of only amorphous silicon semiconductors, when a reverse bias of 107 was added, the amount was more than 1 mm, but when this was made into Smu8, the value decreased to 6 to 50/Jmu.

This is because the 1P impurity in the Ell, 830F+, or N1 type semiconductor is coordinated in a substitutional manner, and its ionization rate is 4N or higher, the same as in a single crystal, and its activation energy is also 0.1% compared to the amorphous case. 2~0.3・V
The electric conductivity is 10 to 10 of 8 (1 for a e sj).
The reason is that it has become extremely large, 0"-10L (Ac m5").

For this reason, impurities that have once been coordinated do not deviate out during lamination, resulting in clean bonding.

Furthermore, since such a stacked type IGv is used, a plurality of xeys can be formed on a substrate, especially an insulating substrate, without using high-precision photolithography technology as in the past.

It became possible to create resistors and capacitors.

And on the LCD display! , it became possible to develop it.

In the present invention, the semiconductor is silicon, and the insulator is silicon oxide or silicon nitride.However, germanium, ElixGs, (o(xzυ, BP, Ga, etc.) may also be used as the semiconductor.

It goes without saying that non-single-crystal semiconductors may be amorphous or polycrystalline conductors with a crystal grain size of 60 to 6000 μm instead of Bm8.

[Brief explanation of the drawing]

FIG. 1 shows an equivalent circuit of a matrix structure in which an insulated gate semiconductor device according to the present invention, an inverter resistor, a capacitor, or an insulated gate semiconductor device and a capacitor are used as picture elements. FIG. 2 shows a multilayer insulated gate according to the present invention. FIG. 3 shows another semiconductor device of the present invention; FIG. 4 and FIG. 6 show a stacked insulated gate semiconductor device and a capacitor or 1 shows a semiconductor device that constitutes a flat display integrated with a liquid crystal.

Claims (1)

[Claims] 1. A first semiconductor provided on a substrate or a first conductive layer on the substrate, and second and third semiconductors provided on the semiconductor and having approximately the same shape. a gate insulating film provided adjacent to a side portion of the second semiconductor; In an insulated gate type semiconductor device provided with a gate consisting of a gate electrode, the first semiconductor or the first conductive layer, the electrode of the gate, a second conductive layer constituting a lead, and the third semiconductor. Alternatively, a semiconductor device characterized in that the third conductive layers connected to the semiconductor are laminated so as to be separated from each other by a glabellar insulator. 2. A semiconductor device according to claim 1, characterized in that the first conductive layer, the second conductive layer, or the third conductive layer is a transparent conductive layer.