JPS5873232A - Analog-to-digital conversion circuit - Google Patents
Analog-to-digital conversion circuitInfo
- Publication number
- JPS5873232A JPS5873232A JP17167881A JP17167881A JPS5873232A JP S5873232 A JPS5873232 A JP S5873232A JP 17167881 A JP17167881 A JP 17167881A JP 17167881 A JP17167881 A JP 17167881A JP S5873232 A JPS5873232 A JP S5873232A
- Authority
- JP
- Japan
- Prior art keywords
- voltage
- circuit
- output
- input
- comparison
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 238000006243 chemical reaction Methods 0.000 title claims abstract description 11
- 238000001514 detection method Methods 0.000 abstract description 7
- 230000003247 decreasing effect Effects 0.000 abstract 1
- 238000010586 diagram Methods 0.000 description 5
- 238000000034 method Methods 0.000 description 3
- 238000007796 conventional method Methods 0.000 description 2
- 238000013139 quantization Methods 0.000 description 2
- 241000272814 Anser sp. Species 0.000 description 1
- 230000005669 field effect Effects 0.000 description 1
- 239000011159 matrix material Substances 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03M—CODING; DECODING; CODE CONVERSION IN GENERAL
- H03M1/00—Analogue/digital conversion; Digital/analogue conversion
- H03M1/12—Analogue/digital converters
- H03M1/14—Conversion in steps with each step involving the same or a different conversion means and delivering more than one bit
- H03M1/145—Conversion in steps with each step involving the same or a different conversion means and delivering more than one bit the steps being performed sequentially in series-connected stages
- H03M1/146—Conversion in steps with each step involving the same or a different conversion means and delivering more than one bit the steps being performed sequentially in series-connected stages all stages being simultaneous converters
- H03M1/147—Conversion in steps with each step involving the same or a different conversion means and delivering more than one bit the steps being performed sequentially in series-connected stages all stages being simultaneous converters at least two of which share a common reference generator
-
- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03M—CODING; DECODING; CODE CONVERSION IN GENERAL
- H03M1/00—Analogue/digital conversion; Digital/analogue conversion
- H03M1/12—Analogue/digital converters
- H03M1/34—Analogue value compared with reference values
- H03M1/36—Analogue value compared with reference values simultaneously only, i.e. parallel type
- H03M1/361—Analogue value compared with reference values simultaneously only, i.e. parallel type having a separate comparator and reference value for each quantisation level, i.e. full flash converter type
- H03M1/362—Analogue value compared with reference values simultaneously only, i.e. parallel type having a separate comparator and reference value for each quantisation level, i.e. full flash converter type the reference values being generated by a resistive voltage divider
- H03M1/365—Analogue value compared with reference values simultaneously only, i.e. parallel type having a separate comparator and reference value for each quantisation level, i.e. full flash converter type the reference values being generated by a resistive voltage divider the voltage divider being a single resistor string
Landscapes
- Engineering & Computer Science (AREA)
- Theoretical Computer Science (AREA)
- Analogue/Digital Conversion (AREA)
Abstract
Description
【発明の詳細な説明】
本発明はアナログ−ディジタルの（ＡＤ）変換回路に係
シ、特に並列比較方式のＡＤ変換回路に関する。DETAILED DESCRIPTION OF THE INVENTION The present invention relates to an analog-to-digital (AD) conversion circuit, and particularly to a parallel comparison type AD conversion circuit.
並列比較方式のＡＤ変換回路はアナログ量を同時に比較
処理するため高速用に適している反面。On the other hand, the parallel comparison type AD conversion circuit is suitable for high-speed applications because it compares and processes analog quantities at the same time.
量子化のレベル数だけ電圧比較回路な会費とするためビ
ット数の多いＡＤ変換には適さない欠点があつた。Since the voltage comparator circuit costs as much as the number of quantization levels, it has the disadvantage that it is not suitable for AD conversion with a large number of bits.
第１図は従来の並列比較方式のＡＤ変換回路の一例を示
すものである。ｌはアナログ信号入力端子、２〜１７は
任意に抵抗値が設定された分圧回路抵抗％１８〜３２は
分圧回路抵抗により基準電圧＋Ｖが段階的に分圧された
各電圧ｅ１〜ｅｔａとアナログ信号入力端子ｌより受け
た入力電圧との大小を判定する電圧比較回路、３３は電
圧比較回路１８〜３２の出力信号を入力して、アナログ
信号入力端子１に印加されたアナレグ入力電圧に対応し
たディジタル信号を得るデコーダ回路である０第１図に
おいて電圧比較回路１８〜３２は、その一方の入力端子
に１アナログ信号入力端子よシ与えられた電圧ｅ６が他
方の入力端子にそれぞれ与えられた分圧電圧ｅ ＋＃Ｑ
ＩＩよシ大きい時に低い電圧（以下「０」レベルと呼
ぶ）になハ小さい時は高い１′圧（以下「１」レベルと
呼ぶ）に反転するものとすると、ｅ６＞ｅｌの時、電圧
比較回路１８〜３２の出力信号は、「００ｏ・・・・・
・ｏｏ」になる。以下同様Ｋｅｌ＞ｅｏ＞ｅｇｇ ｅｌ
）ｅ、）ｅ、１−。FIG. 1 shows an example of a conventional parallel comparison type AD conversion circuit. l is an analog signal input terminal, 2 to 17 are voltage dividing circuit resistances whose resistance values are arbitrarily set, and %18 to 32 are voltages e1 to eta obtained by dividing the reference voltage +V in stages by voltage dividing circuit resistances. A voltage comparison circuit 33 determines the magnitude of the input voltage received from the analog signal input terminal 1, and a voltage comparison circuit 33 inputs the output signals of the voltage comparison circuits 18 to 32 to correspond to the analog input voltage applied to the analog signal input terminal 1. In FIG. 1, the voltage comparison circuits 18 to 32, which are decoder circuits for obtaining digital signals, have voltage e6 applied to one input terminal of the analog signal input terminal and applied to the other input terminal, respectively. Divided voltage e +#Q
Assuming that the voltage is reversed to a low voltage (hereinafter referred to as "0" level) when it is larger than II, and to a high 1' voltage (hereinafter referred to as "1" level) when it is small, when e6>el, the voltage comparison The output signals of circuits 18 to 32 are "00o...
・It becomes "oo". Similarly, Kel>eo>egg el
) e, ) e, 1-.
ｅｘａ＞ｅｏ＞ｅｔａ、ｕｓ＞ｅｏＯ時、電圧比較回路
の出力コードはそれぞれ「１００・・・・・・ＯＯＪ、
「１１０・・・・・・００」、・・・、［ｔＸ・・・・
ｏｌ １０Ｊ 、 「ｉ １１・・聞１１１」となるの
で、この１６種類の出力状態に応じてデコーダ回路３３
でデコードすると、その出力端子３４，３５，３６．３
７に１０進数でｒＯＪから「１５」までのディジタル信
号を得ることができる。このように並列比較方式のＡＤ
変換回路は。When exa>eo>eta and us>eoO, the output codes of the voltage comparison circuit are "100...OOJ,
"110...00",..., [tX...
ol 10J, "i 11...111", so the decoder circuit 33
When decoded with , its output terminals 34, 35, 36.3
It is possible to obtain a digital signal from rOJ to "15" in decimal notation. In this way, AD using the parallel comparison method
conversion circuit.
アナロタ量を同時に比較処理するために非常に高速用に
適している。反面、量子化のレベル数だけ電圧比較回路
が必要である。上記の例のように４ビツトのディジタル
出力を得るのに１５個の電圧比較回路が必要であり、一
般にｎビットの場合にけ２ｎ−１個の電圧比較回路が必
要である。このため回路が複雑で集積化した場合にはチ
ップサイズが大きくなりコスト高になる欠点があった。Suitable for very high speed processing as analog quantities can be compared and processed simultaneously. On the other hand, as many voltage comparison circuits as the number of quantization levels are required. As in the above example, 15 voltage comparison circuits are required to obtain a 4-bit digital output, and generally 2n-1 voltage comparison circuits are required for n bits. Therefore, when the circuit is complicated and integrated, the chip size becomes large and the cost increases.
本発明の目的は上述の点に鑑みなされたもので、スピー
ド的には従来のとおり陣列処理のため、全くそこなわれ
ることなく、シかも電圧比較回路が従来の半分以下とな
る新規なＡＤ＆換回路を提供することにある。The purpose of the present invention has been made in view of the above-mentioned points, and is a novel AD & converter in which the voltage comparator circuit is less than half that of the conventional one, and the speed is the same as before, so there is no problem at all. The purpose is to provide circuits.
本発明によれは、両端に接続された差率を圧を任急に抵
抗値設定された複数の段階的分圧点Ｃｎ（ｎ＝ｘ、ｚ、
・・・、Ｎ：Ｎは正の整数）を有する分圧回路によ部分
圧し、最初の分圧点Ｃ１には電圧比較回路を、次の分圧
点Ｃ！から分圧点ＣＭ＋１（Ｍは正の整数）までのＭ個
の分圧点は、それぞれスイッチ手段の入力に接続し、さ
らに次の分圧点ＣＭ＋ｚＫは電圧比較回路を、そして次
の分圧点ＣＭ＋１からＭ個の分圧点はそれぞれ他のスイ
ッチ手段の入力に接続し、以下同様に１個の電圧比較回
路とＭ個のスイッチ手段を１組として、それらを最後の
分圧点ＣＮｔで合計Ｐ組（Ｐは正の整数。According to the present invention, a plurality of stepwise voltage dividing points Cn (n=x, z,
..., N: N is a positive integer), a voltage comparator circuit is installed at the first voltage division point C1, and a voltage comparison circuit is installed at the next voltage division point C! The M voltage dividing points from CM+1 (M is a positive integer) to the voltage dividing point CM+1 (M is a positive integer) are each connected to the input of the switch means, and the next voltage dividing point CM+zK is connected to the voltage comparator circuit, and the next voltage dividing point CM+zK is connected to the input of the switching means. The M voltage division points from CM+1 are connected to the inputs of other switch means, and in the same way, one voltage comparator circuit and M switch means are combined as one set, and they are summed at the last voltage division point CNt. P set (P is a positive integer.
また最後の紹は、Ｎの値によってはスイッチ手段がＭ個
そろわないこともある。）接続し、該Ｐ個の１圧比較回
路の他方の入力端子にはアナログ入力端子よシ受けた入
力電圧を共通に与えることによシ前配分圧点との電圧の
大きさを比較し、さらにしＰ個の電圧比較回路の出力信
号を入力して該出力信号の信号が変化する境界点を検出
する、Ｐ本の出力線をもつ、境界検出回路を具え、該境
界検出回路のＰ本の出力線を前記Ｐ組のスイッチ手段の
１閉手段にそれぞれ接続し、該Ｐ組のスイッチ手段の出
力を各組より１本ずつ取り出し、それらを第１の共通出
力端子に接続し以下同様にしてＭ個の共通出力端子を、
新たなＭ個の電圧比較回路にそれぞれ入力し、該電圧比
較回路の他方の入力端子には前記アナログ信号入力端子
を接続することによって前記共通出力端子の電圧の大き
さとを比較し、該電圧比較回路の出力信号と前記境界検
出回路の出力信号を入力とするデコーダ回路とで構成す
ることによシ、該デコーダ回路のディジタル信号出力コ
ードによシ、入力アナログ電圧に対応するディジタル信
号出力を得るＡＤ変換回路が得られる。Also, as a final introduction, depending on the value of N, M switch means may not be available. ) are connected, and the input voltage received from the analog input terminal is commonly given to the other input terminal of the P one-voltage comparison circuits, thereby comparing the magnitude of the voltage with the previous distribution pressure point, Furthermore, a boundary detection circuit is provided, which has P output lines and detects a boundary point at which the output signal of the output signal changes by inputting the output signals of the P voltage comparison circuits; Connect the output lines of each of the output lines to one closing means of the switch means of the P set, take out one output from each set of the switch means of the P set, connect them to the first common output terminal, and do the same. M common output terminals,
By inputting the input into each of new M voltage comparison circuits and connecting the analog signal input terminal to the other input terminal of the voltage comparison circuit, the magnitude of the voltage at the common output terminal is compared, and the voltage comparison is performed. By configuring a decoder circuit that receives the output signal of the circuit and the output signal of the boundary detection circuit as input, a digital signal output corresponding to the input analog voltage is obtained according to the digital signal output code of the decoder circuit. An AD conversion circuit is obtained.
以下に本発明による実施例を用いてその詳細を説明する
。The details will be explained below using examples according to the present invention.
第２図は、本発明の一実施例を示す回路図であり、第１
図の対応する部分は同番号で示しである。FIG. 2 is a circuit diagram showing one embodiment of the present invention.
Corresponding parts in the figures are indicated by the same numbers.
３８〜４４はアナログ信号入力端子ｌに与えられた電圧
Ｃ０と分圧電圧ｅｂ ｅ４ｔ ｅｔａ ｅ１６＋６１１
及び信号線５６．５７の電圧をそれぞれ比較する電圧比
較回路であり、その出力信号は第１図で説明した１圧比
較回路と同じくアナログ信号入力端子１より与えられた
電圧がそれぞれの１゛圧比較回路の他方の入力端子に与
えられた分圧電圧より大きい時ｒＯＪレベルに、小さい
時「１」レベルを出力する特性のものである。また４５
は電圧比較回路３８〜４２の出力信号を入力してそのｒ
ｏＪ ｒｌＪの境界を検出する境界検出回路であり、そ
の出力信号線５８〜６２は例えば電界効果トランジスタ
で構成されたスイッチ４６〜５５を駆動すると同時に、
電圧比較回路４３．４４の出力信号と共にデコーダ回路
６３の入力となる。ところでスイツチ４６〜５５は、信
号＃５８〜６２の駆動信号が「１」レベルの時、導通状
態となシそれぞれ分圧１−「圧ｅ ｌ＊ ｅ ｌ＋ｅ
Ｉｍ” ＠ｐ’ ・―”ｌ＠＠！１１＠ ４！１
１１＊”１４會 ”ｌ藝をスイッチ４６〜５５の共通出
力端子５６及び５７のどちらか一方に伝え、「０」レベ
ルの時、非導通状態となる・
上記のように構成された実施例においてアナログ信号入
力端子ｌに与えられた電圧ｅ・が６・〉ｅｇ、ｅｌ＞ｅ
・＞＠４．ｅ４＞ｅ・〉ｅマ、ｅ！〉ｅｌ〉ｅ１＠ｅ
ｅｇ＞ｅｌ＞Ｊｓ、ｕｍ＞６＊の時、電圧比較回路３８
．３９，４０，４１．４２の出力信号（３８，３９，４
０，４１，４２）はそれぞれ（０００００）。38 to 44 are the voltage C0 applied to the analog signal input terminal l and the divided voltage eb e4t eta e16+611
This is a voltage comparator circuit that compares the voltages of the and signal lines 56 and 57, respectively, and its output signal is the same as the 1-voltage comparator circuit explained in FIG. It has a characteristic that when the divided voltage is larger than the divided voltage applied to the other input terminal of the comparator circuit, the rOJ level is output, and when it is smaller, the "1" level is output. 45 again
inputs the output signals of the voltage comparison circuits 38 to 42 and calculates its r
This is a boundary detection circuit that detects the boundary of oJ rlJ, and its output signal lines 58 to 62 drive switches 46 to 55 composed of field effect transistors, for example, and at the same time,
It becomes an input to the decoder circuit 63 together with the output signals of the voltage comparison circuits 43 and 44. By the way, the switches 46 to 55 are in a conductive state when the drive signals #58 to 62 are at the "1" level.
Im” @p’ ・―”l@@! 11@4!1
11*"14" is transmitted to either one of the common output terminals 56 and 57 of the switches 46 to 55, and when it is at the "0" level, it becomes non-conductive. In the embodiment configured as above, The voltage e applied to the analog signal input terminal l is 6〉eg, el>e
・>@4. e4>e・>ema, e! 〉el〉e1@e
When eg>el>Js, um>6*, the voltage comparison circuit 38
．． 39, 40, 41.42 output signals (38, 39, 4
0, 41, 42) are each (00000).
（１００００）、（１１０００）Ｉ （１１１００）。(10000), (11000) I (11100).
（１１１１０）、（１１１１１）となる。境界検出回路
４５０入力信号（Ａ５．Ａ４．Ａ３．Ａ２．ＡＩ）と出
力信号（Ｂ５ 、 Ｂ４ 、 Ｂ３ 、 Ｂ２ 、 Ｂ
ｌ ’）の関係は第１表の通９であシ、これは例えば第
３図のよ第３図において６８〜７１はインバータ、７３
〜７６はＮＯＲゲートである。第１表より分かるようＫ
ｅ・がｅｌ＞ｅ（、の時、第２図において信号線５８〜
６２のどれか１つが「１」レベルになシ、その信号線で
駆動されるスイッチが導通状態となる。例えばｅｌ＞ｅ
ｌ＞ｅｇの時は、色好紳５８のみ「ｌ」にな〕スイッチ
４６及び４７が導通状態となシ、信号＃５６には電圧ｅ
ｌが信号＃５７には電圧ｅｌが表われる０その時の電圧
比較回路４３及び４４の出力信号（４３，４４）は、ｅ
ｌ＞ｅ。(11110) and (11111). Boundary detection circuit 450 input signals (A5.A4.A3.A2.AI) and output signals (B5, B4, B3, B2, B
The relationship between 68 and 71 is inverter, and 73 is as shown in Figure 3.
-76 are NOR gates. As can be seen from Table 1, K
When e・ is el>e(, in FIG. 2, the signal lines 58~
If any one of the signal lines 62 is at the "1" level, the switch driven by that signal line becomes conductive. For example, el>e
When l>eg, only the sensual man 58 becomes "l"] When the switches 46 and 47 are in the conductive state, the voltage e is applied to the signal #56.
The output signals (43, 44) of the voltage comparison circuits 43 and 44 at that time are e
l>e.
〉６０時（００）ｅｌ＞ｅｌ＞ｅｌの時、（１０）ｅｌ
＞ｅ拳＞ｅｇの時（１１）となる。よってデ−ダ回路６
３０入力信号（Ｃ・ｃ、ｃ、ｃ、ｃ露ＣＩ Ｃｏｔ Ｃ
ｅ１）はｅｌ＞ｅ、＞ｅ４０時３種類の入力状態が考え
られ、即ちｅｌ＞ｅ、＞ｅｌの時（０１００００００）
、・＠ ＞ｅｌ ＞ｅｌの時（０１００００１０）。〉60 o'clock (00)el>el>el, (10)el
>e fist>eg (11). Therefore, the data circuit 6
30 input signals (C, c, c, c, c dew CI Cot C
For e1), three types of input states are possible when el>e, >e40, namely, when el>e, >el (01000000)
,・@>el When >el (01000010).
ｅｌ ＞ｅ、 ＞ｅｇの時（０１００００１１）となる
のでデコーダ回路６３はこの３種類の入力状態に応じて
出力端子６４〜６７に３８類のディジタル出力を得るこ
とができゐ。とζろでデコーダ回路６３は例えば第４図
のような回路で構成される。１４図において７７．７８
はインバータ％７９〜８１はＮＯＲゲート８２〜９６は
ＡＮＤゲート、９７〜１００はマトリクス表示のＮＯＲ
ゲートであシ、ＡＮＤゲート８２〜９６の出力線のうち
丸印のあるのが各ＮＯＲゲートに入力されることを示す
。When el >e, >eg (01000011), the decoder circuit 63 can obtain 38 kinds of digital outputs at the output terminals 64 to 67 according to these three types of input states. The decoder circuit 63 is constituted by a circuit as shown in FIG. 4, for example. 77.78 in Figure 14
is the inverter% 79-81 are NOR gates 82-96 are AND gates, 97-100 are NOR in matrix display
Output lines of the AND gates 82 to 96 with circles indicate that they are input to each NOR gate.
例えばＮＯＲゲート１００は％ＡＮＤゲート８９〜９６
を入力とするＮＯＲゲートである＠ｌｌＡ４図において
ＡＮＤゲート８２〜９６はどれか１つが選択されるとＮ
ＯＲゲート９７〜１００でコード化された信号が出力（
Ｄａ Ｄｓ Ｄｓ Ｄｓ ）に表われる＠例えばＡＮＤ
ＮＯゲートが選択されルト出力（ＤＩ ｒ）ｓ Ｄａ
Ｔｉｔ）は（１１１０）になる。ところで前記の例のよ
うにｅｌ＞ｅｌ＞ｅｇの時、入力Ｃ篇〜ＣＩはＣｓのみ
が「１」になるのでＡＮＴ）ケート８２〜９６１７）５
チ８２ 、８３ 、８４の３つだけがｉＭ択されるがｓ
”１ｋが６９．ｅｌ より大きいか小さいかＫよって
、即ち入力Ｃ０ＩｓＣ＠１の入力値によりてＮＯＲゲー
）７９，８０．８１のどれか１つが「１」になシ、結局
これを入力している、ＡＮＩ）ゲート８２，８３．８４
の１つだけが導通状態となり選択される。例えばｅｌ
＞ｅ６Ｊの時は（Ｃｅｓ Ｃｅ１）は（００）であるの
でＮＯＲゲー）７９，８０，８１のうち７９だけが「１
」になシＡＮＩ）ケート８２が選択され出力（１４ｒ）
ＩＤｓｌ’）ｔ）は（１１１０）となる。同じようにｅ
鵞＞ｅ、＞ｅｌの時ＦｉＡＮＤゲート８３が、ｅｌ＞ｅ
ｇ）ｅｇの時は、ＡＮＴ）ゲート８４が選択され出力（
１１４ＤＩ ＤＩ １１ｘ ）バーｔｔＬソｔＬ（１１
０１）（１１００）となる。入力電圧ｅ６がｅｇ＞ｅｏ
の時も同様にしてＡＮＤゲート８２〜９６のうち１つが
選択され出力（ｒ）４ ｒ）ｓ Ｄａ Ｄｌ）にディジ
タル出力が得られる。即ちＣ４＞ｅ＠＞ｅｌの時は入力
Ｃ１〜ＣＩのうちＣ４だけが「１」になるのでＡＮＴ）
ゲート８５．８６．８７のうちの１つが、 Ｃ４＞ｅ、
＞ｅｌｅの時は、ＡＮＤＮＯゲート、８９．９０のうち
の１つが、Ｃ１６＞ｅ＠＞１１ｍの時は、ＡＮＩ）ゲー
ト９１ｒ９２．９３のうちの１つが、ｅｌｌｌ＞ｅｏの
時は、ＡＮＤケー）９４，９５．９６のうちの１つが、
それぞれ選択され、デコードされた出力（Ｄ４ＤＢ １
１ ｒ）ｘ ）が得られる。また入力電圧ｅ、がｅ、
＞ｅｌの時はＡＮＩＩゲー）８２〜９６はどれも選択さ
れず、その出力は全て「０」であるので出力（Ｄ４ Ｄ
ｓ Ｄａ Ｉ）ｔ）は（１１１１）になる。以上のよう
に出力（Ｄａ Ｄａ Ｄａ Ｄｔ ）には入力電圧ｅ０
の大きさに応じて（１１１１）から（００００）までの
１６通シのディジタル出力を得ることができる。For example, NOR gate 100 is %AND gate 89-96
In the diagram @llA4, which is a NOR gate with an input of
The signals encoded by OR gates 97 to 100 are output (
Da Ds Ds Ds )@For example, AND
NO gate is selected and output (DIr)s Da
Tit) becomes (1110). By the way, as in the above example, when el>el>eg, only Cs becomes "1" in the input C section ~ CI, so ANT) Kate 82 ~ 9617) 5
Only the three jis 82, 83, and 84 are iM selected, but s
``1k is larger or smaller than 69.el (Depending on K, that is, depending on the input value of input C0IsC@1) One of 79, 80.81 is not ``1'', so after all input this ANI) Gate 82, 83.84
Only one of them becomes conductive and is selected. For example, el
> When e6J, (Ces Ce1) is (00), so only 79 out of 79, 80, and 81 (NOR game) is "1".
” (ANI) Kate 82 is selected and output (14r)
IDsl')t) becomes (1110). Similarly e
When Goose>e,>el, FiAND gate 83, el>e
g) When eg, ANT) gate 84 is selected and the output (
114DI DI 11x ) barttL sotL(11
01) (1100). Input voltage e6 is eg>eo
In the same manner, one of the AND gates 82 to 96 is selected and a digital output is obtained at the output (r)4r)sDaDl). In other words, when C4>e@>el, only C4 among the inputs C1 to CI becomes "1", so ANT)
One of the gates 85.86.87 is C4>e,
>ele, one of the gates is ANDNO; one of 89.90 is C16>e@>11m, it is ANI) one of the gates 91r92.93 is ell>eo, then ANDK) One of 94,95.96 is
Each selected and decoded output (D4DB 1
1 r)x ) is obtained. Also, the input voltage e is e,
>el, ANII game) None of 82 to 96 are selected, and their outputs are all "0", so the output (D4 D
s Da I) t) becomes (1111). As mentioned above, the input voltage e0 is used for the output (Da Da Da Dt)
Depending on the size of the signal, 16 digital outputs from (1111) to (0000) can be obtained.
上記の実施例は、ディジタル信号出力が４ビツトの場合
で、従来の方法だと電圧比較回路が１５個必要であった
が、本実施例では７個しか必要としない。そのかわりス
イッチが１０個必要であるがスイッチはトランジスタ１
．２個で実現することができ、電圧比較回路よりはるか
に簡単に構成することができる。また本実施例でけ電圧
比較回路を分圧回路の各分圧点に２個おきに並べ、その
間にスイッチ２個を置く構成をとったが、何個おきに電
圧比較回路を並べるかけ自由である。In the above embodiment, the digital signal output is 4 bits, and the conventional method requires 15 voltage comparison circuits, but this embodiment requires only 7 voltage comparison circuits. Instead, 10 switches are required, but the switch is 1 transistor.
．． It can be realized with two pieces, and can be configured much more easily than a voltage comparison circuit. Furthermore, in this embodiment, the voltage comparator circuits are arranged every second at each voltage dividing point of the voltage divider circuit, and two switches are placed between them, but the voltage comparator circuits can be arranged at any number of intervals. be.
例えば第２図において電圧比較回路を各分圧点に３個お
きに並べると、即ちｅｌｔｅｌ＊ｅ・、ｅｌ、の各点に
電圧比較回路を並べ、その他の分圧点にはスイッチを置
き、スイッチの共通出力端子を入力とする。電圧比較回
路を３個置く構成にすることもできる０その場合、電圧
比較回路は７個、スイッチは１１個必要であ夛、各分圧
点に２個おきに電圧比較回路を並べた本実施例よりスイ
ッチが１つ余分にいる。何個おきに電圧比較回路を並べ
た方が最適であるかどちらかはディジタル信号出力のビ
ット数によって異なり１例えば９ビツトの場合は第２表
に示す通り電圧比較回路を１８個おきに並べると電圧比
較回路は最小の４５個ですむ。For example, in Fig. 2, if voltage comparison circuits are arranged every third at each voltage division point, that is, voltage comparison circuits are arranged at each point eltel*e・, el, and switches are placed at other voltage division points. The common output terminal of the switch is used as input. It is also possible to have a configuration in which three voltage comparison circuits are placed.In that case, seven voltage comparison circuits and 11 switches are required.In this implementation, voltage comparison circuits are arranged every second at each voltage division point. There is one more switch than in the example. Is it best to line up the voltage comparison circuits every 18th or the other? This depends on the number of bits of the digital signal output1. For example, in the case of 9 bits, it is best to line up the voltage comparison circuits every 18th as shown in Table 2. The minimum number of voltage comparator circuits is 45.
第２＆
故に本発明の方式を採用すれば集積化した場合、従来の
ものよりチップ面積を大幅に減少させることができ経済
的効果を高めることができる。2. Therefore, if the method of the present invention is adopted, the chip area can be significantly reduced compared to the conventional method when integrated, and the economic effect can be enhanced.
第１図は従来の並列比較方式のＡＤ＆換回路を示す構成
図、第２図は本発明の一実施例を示す構成図、第３図は
境界検出回路図、第４図はデコーダ回路である。
１・・・・・・アナログ入力端子、２〜１７・・・・・
・分圧回路抵抗、１８〜３２．３８〜４４・・・・・・
電圧比較回路、３３．３６・・・・・・デコーダ回路、
３４〜３７゜６４〜６７・・・・・・ディジタル信号出
力端子、４５・・・・・・境界検出回路、５８〜６２・
・・・・・信号線、６８〜’１１，７７．７８・・・・
・・インノ（−タ、７３〜７６゜７９〜８１ ．９７〜
１００・・・・・・ＮＯＲゲート。
８２〜９６・・・・・・ＡＮＤゲート。Fig. 1 is a block diagram showing a conventional parallel comparison type AD & conversion circuit, Fig. 2 is a block diagram showing an embodiment of the present invention, Fig. 3 is a boundary detection circuit diagram, and Fig. 4 is a decoder circuit. . 1...Analog input terminal, 2-17...
・Voltage divider circuit resistance, 18~32.38~44...
Voltage comparison circuit, 33.36...decoder circuit,
34-37゜64-67...Digital signal output terminal, 45...Boundary detection circuit, 58-62...
...Signal line, 68~'11,77.78...
... Inno (-ta, 73~76°79~81 .97~
100...NOR gate. 82-96...AND gate.
Claims (1)
する分圧回路と、上記分圧出力電圧の値が連続した複数
を単位とし、該単位の内の１つの分圧出力電圧を入力信
号と比較する第１の比較器と、該単位の内の他の分圧出
力電圧の数と同数の比較入力として上記入力信号が供給
された複数の第２の比較器と、上記他の分圧出力電圧を
と第２の比較器との関に接続された複数のトランスファ
ーゲートとを有し、上記館２の比較器は各単位に対して
共通に配されていることを特徴とすゐＡＤ変換回路。A voltage divider circuit that divides a reference voltage and generates multiple divided output voltages of different values, and a unit of multiple consecutive divided output voltage values, and inputs one divided output voltage of the units. a first comparator for comparing the signal; a plurality of second comparators to which the input signal is supplied as comparison inputs, the number of which is equal to the number of other divided output voltages in the unit; It has a plurality of transfer gates connected between the pressure output voltage and the second comparator, and the comparator of the second comparator is arranged commonly for each unit. AD conversion circuit.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP17167881A JPS5873232A (en) | 1981-10-27 | 1981-10-27 | Analog-to-digital conversion circuit |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP17167881A JPS5873232A (en) | 1981-10-27 | 1981-10-27 | Analog-to-digital conversion circuit |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPS5873232A true JPS5873232A (en) | 1983-05-02 |
Family
ID=15927664
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP17167881A Pending JPS5873232A (en) | 1981-10-27 | 1981-10-27 | Analog-to-digital conversion circuit |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPS5873232A (en) |
Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPH01245717A (en) * | 1988-02-12 | 1989-09-29 | Philips Gloeilampenfab:Nv | Electronic circuit for synchronizing transition of bit in digital code |
| JPH0322710A (en) * | 1989-06-20 | 1991-01-31 | Sony Corp | Parallel comparison type a/d converter |
Citations (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS5186957A (en) * | 1975-01-29 | 1976-07-30 | Japan Broadcasting Corp | HEIRETSUFUGO KAKAIRO |
| JPS5623026A (en) * | 1979-08-03 | 1981-03-04 | Nec Corp | Analog-digital conversion unit |
-
1981
- 1981-10-27 JP JP17167881A patent/JPS5873232A/en active Pending
Patent Citations (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS5186957A (en) * | 1975-01-29 | 1976-07-30 | Japan Broadcasting Corp | HEIRETSUFUGO KAKAIRO |
| JPS5623026A (en) * | 1979-08-03 | 1981-03-04 | Nec Corp | Analog-digital conversion unit |
Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPH01245717A (en) * | 1988-02-12 | 1989-09-29 | Philips Gloeilampenfab:Nv | Electronic circuit for synchronizing transition of bit in digital code |
| JPH0322710A (en) * | 1989-06-20 | 1991-01-31 | Sony Corp | Parallel comparison type a/d converter |
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