JPS5874067A - Semiconductor device - Google Patents

Abstract

(57) [Summary] This bulletin contains application data before electronic filing, so abstract data is not recorded.

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a semiconductor device in which a vertical channel type stacked insulated gate type semiconductor device is provided on a substrate, and a method for manufacturing the same.

The present invention relates to a semiconductor device having a capacitor connected to the source or drain of a stacked insulated gate field effect semiconductor device on a substrate, or on the substrate.

The present invention is characterized in that such a composite semiconductor device is provided on a substrate in a matrix structure, and a liquid crystal display type display device is provided.

When a flat solid state display device is provided according to the present invention, a liquid crystal display device is known in which electrodes are provided in parallel glass plates and liquid crystal is injected between the electrodes. However, in this case, the limit for the number of picture elements in this display is 20 to 200, and if it is more than that, you will need as many terminals to take out outside of this display as there are picture elements, so it is completely unnecessary. It could not be put to practical use. For this reason, this display section has a plurality of picture elements, which are arranged in a matrix, and in order to control any picture element to turn it on or off, a field effect semiconductor device (hereinafter referred to as GF) corresponding to that picture element is required. was needed.

This GIFK control signal is then applied to turn on or off the corresponding picture element.

The application of the present invention to the vertical channel type G111' and liquid crystal display is disclosed in the patent application filed by the present inventor (Insulated Gate Field Effect Semiconductor Device and Method for Manufacturing the Same, Japanese Patent Application No. 56-00176'7) and the composite Semiconductor device Patent Application No. 1983-001768 (filed on January 9, 1981)
Details are shown below. The present invention is a further development of this. This liquid crystal display section can be represented by a capacitor (hereinafter referred to as C) K as its equivalent circuit.

For this purpose, a 2×2 matrix configuration (40) of GII' and C is shown in FIG.
In the figure, the matrix α0) is one engineering GF (10
), 0 (31) filled with one liquid crystal, and C (31) provided as necessary to provide afterglow properties.One picture element is composed of three.
) (54) is connected to the bit line, and the other gate is connected to form a column α1) (41).

Then, for example, let (51) (41) be 1″ and 5a)′0
By pressing 0'' and 2, it is possible to select and turn on only the address (1,1), and selectively turn on the liquid crystal display, which is electrically shown isometrically as O(31). .

The purpose of the present invention is not to configure a decoder and a driver on the same substrate, but also to provide another insulated gate type semiconductor device (50), another inverter (60), and a resistor (00) on the same substrate. By combining the present invention based on its design specifications, it was possible to create a solid-state display device for flat televisions that can replace cathode ray tubes.

Furthermore, a display device for a calculator may use 1♂ to ICi picture elements, and for a TV, 10 to 10 picture elements, for example, 2
I installed 5 x 103 picture elements on the same substrate, and formed the necessary decoders and drivers around them at the same time.
C) It turns out that it can be made using F, an inverter, and a resistor.

Examples are shown below.

Example 1 FIG. 2 shows a vertical sectional view of the laminated mold GF of the present invention and its manufacturing process.

Then, a pattern was formed into an arbitrary shape to form, for example, a lead layer serving as a lateral conductive layer. This first conductive layer was etched into an arbitrary shape using a first mask (2). Furthermore, a first semiconductor S of KNt or P is formed on the first conductive layer a′4.
1(3) was formed by plasma vapor phase method. Furthermore, the second intrinsic or N-1fcl on top of S1(S) with
A dP-type semiconductor (4) (hereinafter simply referred to as 82) is formed. Furthermore, a third semiconductor having the same conductivity type as S1 (S) is formed in order to form a pair with the first semiconductor and serve as a source and a drain. Semiconductors (5) (hereinafter simply referred to as S3) were stacked and provided as shown in FIG. 2(B). This first conductive layer is -
Even if it is a transparent conductive film such as SnO□ as shown in 4.
i, Or may be used to promote ohmic contact between the 81α terminal and the first conductive layer.

This semiconductor is formed on a substrate using a silane glow discharge method or an arc discharge method at a temperature of room temperature to 400 degrees, and is either amorphous or microcrystalline with a size of 5 to 100 A. A so-called non-single-crystal silicon semiconductor having a semi-amorphous or microcrystalline (micro-polycrystal) structure of 50 to 500 A is used. In the present invention, a semi-amorphous semiconductor (hereinafter S
(referred to as AS). Regarding this SAS, a patent application (Japanese Patent Application No. 55-02638
8855.3.3 (Semi-Amorphous Semiconductor), a detailed example thereof is shown.

Furthermore, in FIG. 1, S2 and 83 were produced in approximately the same shape using a so-called lithography technique using a screen printing method or a photographic flux method. At this time, it is important to leave the first conductive layer.

At this time, when the first conductive layer has two or more layers,
One layer may be selectively removed.

, 1' In order to further reduce the parasitic capacitance by placing a thick insulating film T, +POVD on top of this El 3(5) as shown in FIG.
method (low pressure gas phase method) or plasma OVD method.
A silicon oxide film may be formed to a thickness of ~1 μm. Also on this Ss K MO, W, MOLSi, wLSi
It was effective to form a matrix by forming a conductive layer of 0.2 to 0.5 μm and further forming 8101 to a thickness of 0.3 to 1 μm on top of the conductive layer to improve the conductivity of S3.

In addition, in FIG. 2 (0), the side surface may be formed perpendicularly to the surface of the substrate (1), but it is possible to form the side surface perpendicularly to the surface of the substrate (1).
Furthermore, it was effective to eliminate the step cut at the step portion of the stacked gate electrodes.

Furthermore, after this, an insulating film (6) was formed on the entire surface of this 81.82.83, especially on the side surface of S2α→ as a gate insulating film αQ.
Activated by electromagnetic energy at a frequency of 5 GHz, 100 to 70
It was oxidized by dipping at 0°0 and formed to a thickness of 200-200 OA.

In particular, when the substrate is glass, there is a high possibility that mobile ions such as sodium contained therein will diffuse into the kneading gate insulating film over a long period of time. Therefore, this insulating film is made of silicon nitride (El 1aNx 04x
< 3) or silicon carbide (81xOI-xO<xcl)
It is extremely important to use

Therefore, the silicon nitride film was manufactured as follows. Namely, Silane (81)! 14 or S 1aH) and microwave (2,45GH 250-500W output) ionized ammonia or nitrogen from K to silicide gas: nitride Af! O0l~o as 1:20~1:5000
, introduced into a reactor maintained at 5 torr, K 200 to 500@O in this reactor, and K 13.56MH on the substrate heated from the outside of the reactor to typically 300 °C.
A two-stage plasma OVD method was used in which a second high-frequency plasma (output of 5 to 50 W) was added.

By doing so, a gate insulating film is formed on the semiconductor, especially around the 82 (1◆) side, at a low temperature (200 to 400"O) at which this non-single crystal semiconductor will not deteriorate due to dehydrogenation, etc. By exciting the nitride gas with microwaves (50 to 300 W) at K, the nitride gas was sufficiently ionized (9), and the associated silane was removed. Since the inside of the film was also impregnated with nitrogen during film formation, the generally-known hysteresis characteristics were not observed, and it was also a preferable insulating film that had masking properties against sodium and the like.

Also, regarding s IX, CI ((0≦x<1) K,
When making an insulator, plasma OVD method is used and TMS (
Silicon carbide (tetramethylsilane) (Si(OH),) or carbon by acetylene (OLHI) was prepared by plasma CVD method ((L'l~1 torr substrate temperature 200
~400°C) K Yoshiko's energy band width 2.5~,
365 eV could be formed.

When the substrate is made of glass like this, the forming temperature is set to 200℃.
Considering that the semiconductor and substrate at temperatures up to 400[deg.] C. are not deteriorated, silicon nitride or silicon carbide formed by plasma OVD is an extremely effective gate insulating film.

The gate insulating film a→ was simultaneously formed as an isolation film of 5IQ4S3αQ.

00) Furthermore, as shown in FIG. A metal or semiconductor layer (silicon semiconductor of p+ or N9 conductivity type or sn) connected to the electrode.

(transparent conductive film) was laminated again.

Next, using a fourth photolithography technique, this film is selectively etched to form a gate electrode a, which is laterally laminated on the gate insulator aQ, and at the same time, an 83(l) layer is formed on S'. The wires were closely connected to the other parts' engineering GF, capacitor, and resistor through the maximum stain on the substrate surface or the insulator (6).

If the vertical sectional view A-A of FIG. 2) is viewed from the lateral direction, it can be shown as FIG. 2 (Ili). number,,,
゛corresponds to each. □ As the semiconductor of the present invention, an 8AS silicon semiconductor was mainly used. This is dark conduction #! l□'- is 1δg, 10' (4(
! This is because it has m5' and has characteristics closer to single crystal silicon than 10 to 10 (JLOm) of As.

This dark conductivity was obtained in a substantially intrinsic semiconductor with no intentionally introduced impurities. However, in the intrinsic state (when the activation energy neutralized by boron is Eg/2), on the contrary, the hole mobility is extremely large.
These could be combined to create enhanced or depleted N- or P-channel GFs. This SAS has a lattice strain of 0.1 to 5
It contains hydrogen for neutralizing dangling bonds with a concentration of 100%, prevents degassing of this hydrogen, and protects the substrate and semiconductor.
In order to reduce the stress caused by thermal expansion at the interface between different materials such as electrodes and leads, all treatments are carried out at 200~600℃.
0'O preferably 200-350°01 typically 3o
I wish it was o@c.

Also, the gate electrode a is 1'8 of the same conductivity type as 81.83.
,.

A multilayer wiring structure in which a semiconductor and a metal such as Mo may be used as a double structure may be used.

Thus 4'i! In this mask, the source or drain is S2α with 81α turtle channel formation region (9).
A surface drain or source is formed in a polygon of 8300 mm,
It was possible to fabricate a stacked type engineered GF (10) in which a gate insulator 0O1 was provided on the side surface of the channel forming region and a gate electrode αη was provided on the outer surface thereof.

In this invention, the channel length is determined by the thickness of 5204, which is typically 0.3 to 3μ and typically 1μ. One reason is that the mobility of non-single crystal semiconductors is different from that of single crystals.
Since the channel length is 15 to 1/100 times shorter, the channel length is shortened to promote the characteristics as an engineered GF.

In SAS, the bulk mobility of electrons is 10 to 500
c mV/S and 1/3 to 1/1o, while that of the hole is 0.5 to 100 c mV/S and 115 to 1/1o.
It is 100. However, amorphous silicon has 0 electrons.
．． 01-1. Oc resistance V/F3-, hole is O,0O1c
Considering that it is 10 to 10 times longer than V/s, it is possible to use a SAS having a microcrystal structure with a size of 5 to 100 A in the semiconductor device of the present invention, and to make it a stacked type. Since the length is about 1 μ, it can be formed into a so-called microchannel structure, which is extremely important for high-speed response.

Furthermore, in the engineered GF of the present invention, it is extremely preferable to use an N-channel type because the electron mobility is 3 times higher than that of a single crystal, and 5 to 100 times higher than that of a hole.

In addition, S2 is an N-type intrinsic semiconductor that does not have monovalent impurities such as boron added to its surface, so when forming 82, 0.1~'IOPPM is added at the same time to use it as a P-type or engineering-type semiconductor. In other words, it may be an N-channel IGF for operating the liquid crystal panel of the present invention with a positive voltage.

When a substantially intrinsic semiconductor (N-type) is used for S2, the thus obtained GF can be of the enhancement type in the P-channel GF, and of the depletion type in the N-channel GF. You can get the operating mode.

Further, if this 82 is made of an intrinsic or i-type semiconductor, a depletion type operation mode can be obtained in the P channel GF', and an enhancement type operation mode can be obtained in the N channel EGIF.

Since the enhancement type IGF' for obtaining the liquid crystal display shown in FIG. 1 is easy to use when selecting the picture element, a case where the enhancement type operation is performed will be briefly described.

When the gate electrode was set to 0 and the source or drain was set to #1, a current flowed through the channel forming region (9) to create an on state, and if one or both of them were O, an off state could be created.

#f' is positive 0.5~IO for N-channel type GII'
For the current of V, 0 means OV or a voltage below the threshold voltage.For the OP channel heavy industry GF, the polarity of its electrodes can be changed.

These ring systems are the same in FIGS. 11 and 2 as well as in the embodiments of the invention shown in FIGS. 3 to 5 below.

Also, when trying to create a peripheral decoder or general logic element in Fig. 1, for example, the resistor (70) is
I)), (E) is determined by the vertical resistivity of the bulk component of 82, regardless of the voltage applied to the gate. That is, 81.82. without providing a gate electrode.
S'3 may be laminated. Further, this resistance value may be determined according to the design specifications based on the resistivity of S2, its thickness, and the area covered on the substrate.

In the inverter (60) in Fig. 1, the driver (61
) is shown in Figure 2 (D), and its load (No. 6) is 5.
Enhancement type or depression type engineering GF that connects one side of IQ4ssQ→ with gate electrode α force.
You can set it as

Furthermore, the output of this inverter (60) (62) can be obtained by laminating two GF's separated on this substrate and combining them.
It is good if it is provided correspondingly.

In the vertical channel type GF of the present invention, even if light is irradiated from above or below the GF, the semiconductor layers of Ell and EI3 will be P' or Nth.
Therefore, the so-called 81.83, which has a structure that sufficiently absorbs this light and prevents it from reaching 82, has a light shielding effect at the same time.

Therefore, even if a plurality of IGI+'s are fabricated on a glass substrate, it will not work even if this IGI+' is not particularly shielded from light.
N, 0 LIPF operation can be performed, and the purpose of this effect is to perform display by allowing the area without IGF to transmit and reflect light in the vertical direction to the entire substrate including the liquid crystal. Therefore, the shielding effect of the GF itself is extremely important.

This is a feature that was completely unthinkable in the conventionally known channel type GF' (thin film transistor).

FIG. 3 shows another example of the present invention produced according to the same manufacturing method as Example 1 shown in FIG. 2. Example 2 FIG. 3 (4) shows a conductive layer α on the substrate (1) This is the case where the wiring is made for the pier in the horizontal direction, the gate α force is also made in the horizontal direction, and the wire for B3 (g) is made in the vertical direction in the drawing. In the drawing, Engineering GF (10) 00) 2
Although these are shown, 10 to 10 may be arranged in a matrix on the same substrate. In the drawings, the numbers correspond to the embodiment of FIG. 2.

In its manufacture, lithography masks are
Only three types are required. Gate conductive layer af) and S3θ→
In order to prevent the generation of parasitic capacitance between the conductive layer and the silicon oxide (3o) shown in Example 1, the silicon oxide (3o) shown in Example 1 is
, 3 to 2 μm thick, the silicon oxide (30) is patterned, and using this silicon oxide as a mask, the 81 moth s44 s1α field underneath is etched to roughly form 81, 82, and s3. It is sufficient if they are formed into the same shape.

Example 3 FIG. 3(B) shows another embodiment of the present invention.

In the drawing, the first conductive layer α where the wiring of the engineering GF (10) is connected to 81α1 is lateral, and the contact 83αr)
01) After the connection, the third conductive layer wiring (material) is provided in the horizontal direction, and the second conductive layer θ connected to the gate electrode is provided in the vertical direction perpendicular to the drawing. The wiring is separated by interlayer insulators (6) and (c).

In the drawing, the conductive layer α on the substrate (1) is patterned using a mask 51(l and 82(1483αυ)).
were laminated and etched using a self-aligned mask. Further, after forming the gate insulator αQ, a gate electrode a and its lead α'I) were formed thereon. In addition, after forming an interlayer insulator (c) with polyimide resin, P-type Q, etc. to a thickness of 0.5 to 2 μm, the contact hole (7) is connected to the fabrication plate 5300 to form an electrode/lead. A third conductive layer α◆ is prepared using a mask ■, and 3
This shows that layer wiring can be produced using five types of masks.

Corresponding to this embodiment, FIG. 4 shows the liquid crystal display shown in FIG.
) shows other embodiments of the present invention. In other words, the first conductive layer α is placed on the substrate (1) using a mask in the lateral direction (X
Direction) K shown in an extended shape. Further, S3α→ and gate electrode/lead α are shown in the vertical direction (Y direction) in the drawing.

This is the result of making 82.83 in the mask 2 in the channel formation region and on this day 2α, so leads were made on the S3 (c) using the mask 2.

As shown in Examples 2 and 3.4 above, the GF of the present invention constitutes a source or a drain.
The gate electrode αη on the gate insulator aQ forming the channel formation region in s3 (T) and S2α◆, which constitute the S1 Korean drain □・take source, is arbitrarily selected based on its design elements. It is now possible to form wiring in the X and Y directions with complete freedom.This is because the plasma CvD method is the center of attention, compared to the conventional GFK technology in which channels are formed in the horizontal direction. It has a structure in which semiconductor layers 81, 82, and 83 are sequentially stacked, and
2. S3 was made possible for the first time because it has a substantial self-line structure, and its industrial effects are extremely large.

Embodiment 5 FIG. 4 shows another embodiment of the present invention, which is a further development of FIG. 3(B), and is used in a liquid crystal display.

FIG. 4 shows the present invention applied to the 2×2 matrix cell shown in FIG. 1.

In the drawings, (A) is a part of the plan view, (g)) is A
A vertical sectional view on the h1 plane is shown.

In FIG. 4 φ), a first conductive layer (c) is formed in the X direction on a glass substrate (1) to a thickness of 500 to 3000 Å. This is Nesa (S n O,) or Engineering T.

A transparent film using (NLO, +SnO, (5%)) may also be used. Furthermore, KS2α483 (g) is formed above this in the Y direction. Also, the gate electrode lead (
1'/) is formed in the Y direction, and the electrode (c) of the capacitor (31) filled with liquid crystal is formed of a transparent conductive film in contrast to Ip and 83α. There is also another transparent conductive film on the lower surface of the upper glass substrate (c). to this conductive layer)
, (c) are subjected to a liquid crystal molecule alignment film or an alignment treatment so that the liquid crystals are aligned at right angles to each other. A liquid crystal screen is filled between these two transparent electrodes.

For example, (10
) (Capacitor (31) connected to cφ and its output) (31) is shown in FIGS. 4(A) and 4(B) corresponding to FIG. 1.

By doing this, one picture element, that is, a picture element made of the capacitor electrode (c), has a thickness of 1 mm" (1 to 16 mm).
It has also become possible to produce 500 x 500 flat displays using 5 to 20 qm.

Figure 4 shows that only one capacitor filled with liquid crystal was connected in series to the output of this GF, but at the same time a capacitor (3
If two are made in parallel, the result will be as shown in Fig. 5.

Example 6 Figure 5 shows the liquid crystal section (C) and upper electrode (B) shown in Figure 4.
Although the upper glass substrate (c) has been omitted for the sake of simplification of the drawing, this portion may be manufactured by a known method as in FIG. 4.

Figure 5 (A) is a plan view of the area corresponding to one picture element;
(9) is a vertical sectional view at A-A', (0) is B-
The vertical sectional view at B' is shown with corresponding numbers. The orientation of the GF (10) in FIG. 5(C) and the Q-shape is determined by using FIG. 3(4) shown in Example 2 as the main element. □It's what I had.

One electrode (c) of the capacitor for liquid crystal display is connected to (b) sJI, and its structure is different from the case where it is connected to 5sit) in the case of FIG.

A capacitor (32) is formed in parallel with the electrode obtained by providing the second transparent conductive film (3) at the same time as the gate electrode α, and this circuit helps to extend the display time of one liquid crystal display. Specifically, the capacitor (
32).

The on time of this capacitor GF is 10 to 100
Even if the duration is μ seconds, the liquid crystal display can have a so-called afterglow property that makes it as long as 1 to 100 m seconds. This capacitor has a picture element number of 10 to 10, and a scanning speed of 0.
This is effective in preventing the viewer's eyes from becoming strained when the time is 1 to 100 μsec. :i.

In addition, one capacitor of the storage capacity of Jin was able to be made using the same material as the gate insulator α-peak and the same badge method without requiring any new process. However, in order to increase this capacitance in a small area, titanium oxide, tantalum oxide, or other ferroelectric material may be used instead of silicon nitride.

Another electrode (c) electrically connected to s IQl in the present invention is provided through an electrode hole (39). An interlayer insulator such as polyimide or P-type Q may be provided on these GFs (10) to a thickness of 1 to 3 μm, and then selectively formed by lithography.

This electrode (c) determines the size of one picture element according to the design specifications. In calculators etc., 0.1
~5mn? It corresponds to one segment of a square shape or number. However, in the scanning type matrix structure shown in Fig. 1, the 1st to 6th ops may be arranged in a matrix form, for example, 500x500. A liquid crystal molecule alignment film was formed on each electrode, and the electrodes were placed opposite each other, and a nematic liquid crystal (c), for example, was injected therein.

This display may also be displayed in color. Furthermore, for example, these picture elements may be stacked three times. Then, the three elements of red, green, and yellow may be arranged alternately.

As is clear from FIG. 541 and FIG.
The device is characterized in that a plurality of GFs, capacitors, resistors, or a liquid crystal display flat panel is provided at the same time as a sandwich structure on top.

Furthermore, as is clear from the drawing, when the light is irradiated from above, leakage in the #o# state due to the irradiation of the GFI00)K light is automatically prevented. In addition, an extremely significant feature is that the GF is provided in a stacked manner, completely isolated from other picture elements on an insulating substrate, which is different from the conventional method. Especially this whole process e o o'
The fact that it can be manufactured at a temperature of 300"C or less has the great feature that even if the panel has a large area, it is not easily affected by thermal distortion.

In addition, the semiconductor of the present invention mainly has a non-single-crystal structure, and has a special structure called EIA8, which is an intermediate structure between amorphous and single crystal, and is stable against thermal energy up to 600'O. Another feature of the invention.

In particular, this 8A8 is a non-single crystal semiconductor with a large microcrystal structure lattice strain of 10 to 100 A, and even if induction energy of 500 KHz to 3 GHz is used for its manufacture, a temperature of 300°04 is sufficient. In addition, the electron/hole diffusion length of amorphous silicon is 100~
It has physical properties and physical characteristics that are 10" times larger.The structure in which such non-single crystal semiconductors are stacked on a substrate makes it possible to
By providing F' and in addition, because the current flows in the vertical direction, microchannel IGF' with a channel length of 0.1 to 1 μm can be produced without using high-precision photolithography technology. This is an extremely important feature. 1. ,.

Furthermore, in the present invention, the characteristics of the engineered GF are 5AEI
Considering the characteristics of, its threshold voltage CV,
& ) is also characterized in that, for example, doping is not performed by ion implantation, but is controlled by the amount of impurity added to 82 and the high frequency branch power applied.

Therefore, withstand voltage 20~30■, V, -4~4V ±0.2
It was possible to control within the range of V. Furthermore, since the frequency characteristics are microchannels with a channel length of 0.1 to 1μ, the frequency characteristics are 115 to 115 compared to conventional single crystal insulated gate semiconductor devices.
0 could be obtained even though a non-single crystal semiconductor was used.

Regarding reverse leakage, by inserting silicon nitride (S) (04xc4) between SL and 82 to a thickness of 10 to 40A as shown in Fig. 1, this N-type P
Junction or P"N-junction leakage is in the opposite direction K 10'
Even when V was added, it was less than 1μ8. This was comparable to the reverse leakage of a single crystal. □ Also, for Sl or □, for example, add 2 to 2 of oxygen or nitrogen to S3.
0 molt, and when adding 5 to 30 molt of carbon, the second
Similarly, in the structure shown in the figure, there is little leakage in the opposite direction, and when etching the matte 82.83, the Sl is replaced with oat (
- Prevents etching and is also favorable in terms of process O This low leakage property is 1/1 compared to the case without additives.
The leakage was reduced by a factor of 0 to 1/10'. It goes without saying that this reduction in leakage is extremely effective when implementing the matrix structure of FIG.

Furthermore, this reverse leak is caused by this laminated type 81.82.8
3 are both made of amorphous silicon semiconductor only, in the opposite direction) (When IOV was applied to IAS, it was more than 1 mA, but if this was 8 AEl, it was 5 to 5 opAK t. It is P or N of Sl, S3 The B and P impurities in the type semiconductor are coordinated in a substitutional manner, and the ionization rate is 4N or more, the same as in the single crystal, and the activation energy is 1.0.2 to 0 in the case of amorphous.
3eV! DO, became small to 005 to 0.001 eV, and the electrical conductivity also became extremely large at 1o to 1o (n cm) compared to IC1 to 10 (JLOm) of A8. This is because the impurities that were added did not outdiffusion during lamination, resulting in a clean bond.

Furthermore, because of the multilayer type Gml+, a plurality of GGFs can be formed on a substrate, especially an insulating substrate, without using high-precision photolithography technology as in the past.

It became possible to create resistors and capacitors.

It was then developed into a liquid crystal display.

In the present invention, silicon was used as the semiconductor, and silicon oxide or silicon nitride was used as the insulator. But as a semiconductor, Ge/I/?
= , :L-mu1.5ixGe, , (0<xcl), B
P%GaAa or the like may also be used.

It goes without saying that the non-single crystal semiconductor may be an amorphous semiconductor or a so-called polycrystalline semiconductor with a large crystal grain size of 50 to 5000 Å instead of SAS.

(3■

[Brief explanation of the drawing]

FIG. 1 shows a matrix-structured circuit having an insulated gate semiconductor device, an inverter resistor, a capacitor, or an insulated gate semiconductor device and a capacitor as picture elements according to the present invention. FIG. 2 is a vertical sectional view showing the stacked insulated gate type semiconductor device of the present invention and its manufacturing process. FIG. 3 shows another semiconductor device of the present invention. FIGS. 4 and 5 show a semiconductor device constituting a flat display in which the stacked insulated gate type semiconductor component of the present invention is integrated with a capacitor or a liquid crystal. (31) , 1°・1)□. 1:1° 1 Sendanman 3 figures

Claims (1)

[Scope of Claims] 1. A first semiconductor, a second semiconductor, and a third semiconductor provided on a first conductive layer on a substrate are stacked and have approximately the same shape, and a third semiconductor is provided constituting a pair of source and drain of the same conductivity type, and a gate made of a gate insulating film and a gate electrode is provided adjacent to the side of the second semiconductor. 1. A semiconductor device comprising at least one insulated gate type semiconductor device. 2. A semiconductor device according to claim 1, further comprising a capacitor or a capacitor filled with liquid crystal connected to the source or drain. 3. In claim 1, the first conductive layer on the substrate, the second conductive layer connected to the gate electrode, and the third semiconductor or the third conductive layer connected to the third semiconductor, A semiconductor device characterized in that both layers are arranged in directions orthogonal to each other.