JPS5875123A - Information setting device of camera - Google Patents

Abstract

PURPOSE:To prevent an erroneous setting exceeding a threshold value, by detecting that a set digital signal to be updated has reached the threshold value, and shifting the digital singal to its initial value. CONSTITUTION:Through a switch SW1, an up-down counter 2 is controlled as to its up-counting when the initial value is the highest speed second in accordance with aperture priority and shutter second time priority, or is an initial value of the minimum opening value, and a digital set value through the counter 2 is updated in order. When this updated value reaches the lowest speed second time or the maximum opening, etc., it is detected by a counter controlling circuit 4, the counter 2 is preset to the initial value, and a digital set signal circulates and does not exceed the threshold value. In case when the digital signal is counted and set by setting the lowest speed second time or the maximum opening value as the initial value, and executing the down-counting, the constitution is same, and a setting error exceeding the threshold value is prevented.

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a device for setting photographing information such as shutter speed and aperture value in a camera, etc. Settings and changes are made electrically by operating a pushbutton switch or the like using a photographic information setting device Kll.

In a camera equipped with an exposure control circuit, conventionally, in order to set photographing information in the variable elements of the circuit, the variable elements linked to these are manually operated, for example, on a mechanical information setting mechanism such as a shutter dial, aperture ring, etc. I was changing positions. Therefore, when taking a picture, it is necessary to separately operate the information setting mechanism as described above provided on the camera body or the lens, which is inconvenient when taking pictures quickly.

The present invention enables photographing information such as the shutter speed and aperture value as described above to be obtained by operating a push button or the like distributed at an appropriate location on the camera, without using mechanical setting means such as a shutter dial or aperture ring. II.
IPK If the above set value reaches the upper limit of the camera's controllable exposure value while the operating means such as the above push button is being operated, the camera's controllable set value is changed from the above upper limit value. The exposure value is preset to the lower limit value, and if the set value reaches the lower limit value of the camera's controllable exposure value while operating the operating means, the set value is preset from the lower limit value to the upper limit value. and k, the information is quickly set and the setting is prevented.

The present invention will be explained in detail with reference to the drawings below. Fig. 1 is a block circuit diagram showing an embodiment of an electronic photographing information setting and display method according to the present invention. Fig. 1 is a device for setting and displaying photographing information in the camera. is shown in block form, and each input and output terminal in the figure indicates a transmission terminal for input signals and output signals from each part of the digitally controlled camera. In the figure, the Vc attached to each terminal indicates one pole of the camera's power supply, and the other terminals are connected to the part indicated by the ground mark. □Ia indicates the direction to increase or decrease the set value. When the switch Swl is turned on at the input terminal of the circuit to be switched, a logic "1" is sent to the transmission path 9,
When it is off, it sends out 'θ''. This input from 9 causes it to go up.
When the down counter 2 is '1', it is 1 in the up direction. N
When the count is ``O'', step counting is performed in the down direction.The terminal Ib is a terminal for controlling the clock pulse for the counting, and when the switch SW2 is on, an ``O'' signal is sent to the transmission path 17, and when it is off, a ``ln signal is sent to the transmission path 17. is sent. Clock pulses are generated by a clock pulse generator of 7, and set values and other values are changed in a state-of-the-art manner at the cycle of the clock pulses. The clock pulses generated at '7' are applied to the CP input of the up/down counter 2 via the clock input controller 'i' and are counted in steps according to the up/down direction instructions from the line 9. The clock input control signal from i9Ib is also transmitted to the counter controller 4 and the display controller 5 through line 17. Terminal I
c constitutes the power supply circuit of up/down counter 2,
Due to the self-maintaining action of the timer 8 inserted therein, the power supply to the counter 2 is maintained for a certain period of time even if the power to the device is turned off. 3 is the central control unit (
The brightness information from the photometry device including the light receiving element, the priority command signal from the terminal Id, and the output signal 15 of the counter 2 are inputted to the CPU), and the brightness information and the counter 2
Performs exposure calculations based on the exposure information set in , and controls the shutter as the output.

A control signal to the aperture control section and various signals as shown are sent to the display control device 5. Note that the switch S of the Id circuit
W3 is a priority mode changeover switch. 8 When w3 is on, the camera operates in shutter priority mode, and when it is off, the camera operates in aperture priority mode. Of the signals sent from the CPU 3 car to the display control device 5, the shutter digit signal passes through lines 10 and 11. The aperture digit signal is transmitted through a gate controlled by a signal from the terminal Ie, and the display is stopped or blinked by turning 8w4 on or off. Note that a warning signal (1" signal) for displaying various warnings such as that the calculated output value has reached the control limit for the exposure value of the camera is sent directly to the display control device 5 via the line 12, and the display segment signal is sent directly from the C'PU to the display device 6.The output 15 of the up/down counter 2 is input to the CPU as well as to the counter control circuit 4, which in turn is sent to the clock input control device l. A clock control signal 17 is applied to its output to output a counter control signal, which is sent to the parallel presettable input terminal of the up/down counter 2.The output 1.6 of 4 is also connected to the clock input control device l and It is also sent to the display control device 5,
Turn these control operations on and off. As shown in the figure, the display control device 5 receives the clock pulse from the clock pulse generator 7, the signal 16 from the counter control device 4, and the signal from the line 17, and receives each command 1 from the CPU.
0,11. and 14 perform control functions for various display units, and output -f: / time signal 18
．． Aperture signal 19 is output. These display signals are input to the display device 6, and various information displays are displayed in, for example, a finder according to display segment commands from the CPU. The display device is constituted by a combination of known segment and digit drivers, 7-segment LEDs, and other display elements.

The configuration and operation of the electronic photographing information setting and display device according to the present invention have been explained above with reference to FIG. 1, and FIG. This will be explained in detail below.

In the following drawings, the same parts as in FIG. 1 are designated by the same reference numerals.

FIG. 2 is a circuit diagram showing an embodiment of the clock input control device l in FIG. 1, and FIG. 3 is a curve diagram showing an example of a timing chart of the device shown in FIG. In the figure, the pulse from the clock pulse generator 7 has a waveform as shown in FIG. 3(A). Reference numeral 23 denotes a frequency divider composed of a circuit such as a flip-flop, and a signal having a waveform as shown in FIG. 3(b) is obtained at its output. All the clocks are synchronized with the falling edge of the pulse, and the output Q of the counter 21 is returned to the AND gate 24 via the inverter 27, so that at the same time 21 outputs % Q4,
Disable clock input. FIG. 3(c) shows the input of the clock input control device l, and when the switch Sw2 is off, "1"
"," becomes "0" when turned on. This signal also becomes the CP large input of the up/down counter 2 via the reset input of the counter 21 and the OR gate 25 and the AND gate 26. The q output of the counter 21 is ANDed. The second output of the gate 22 is ANDed with the branch output of the clock and inputted to the CP of the up/down counter 2 via the 0R25/AND26.
Change the count by i steps. The control signal from the counter control device shown in FIG. (E) in FIG. 3 shows a case where the off time of the clock input control switch S w 2 is long, and at this time, the Q4 output of the counter 21 is "1" (Fig.
(g)), the up/down counter immediately starts counting 20, as shown in FIG. 3 (g). This shortens the time between each step after the second step when continuing to operate the set value.

FIG. 4 is a circuit configuration diagram showing one embodiment of the counter control device 4 in the first embodiment. In the figure, the outputs C1 to C1 of up/down counter 2 are connected to CP by line 15.
It is input to U3 and sent to OR gate 28, 29 of the counter controller. OR game) 28. The output of 29 is KOR with the up/down direction switching signal from line 9.
The outputs of the OR gates 30 and 31 are ANDed by an AND gate 33 and output to the line 16 as a counter control output via an OR gate 34. Note that a clock input control signal (FIG. 3 (c) or (e)) is input from the line 17 to the 0R34. Now the output of up/down counter-2 is l'-000
00J, that is, the upper limit of the setting range has been reached, and if the direction command from track 9 is "0" indicating down, then 0
The output of R28 is 60'', and the output of oR29 is 1''.

At this time, the signals input to 0R30 and 31 are o" and 0" for 3o.

31 becomes 1", "1", and the output of 0R30 becomes θ", and the output of 0R31 becomes 1", so the output of AND33 becomes 0", and when the signal from the line 17 becomes lOB, the counter control output 16 becomes "0", which is sent to the clock input control device 1, and input to the Kubik up/down counter 2 is stopped. Further, when the output of the counter 2 reaches I-1, 0, 0, 0, IJ, that is, the lower limit of the setting range, and the command from the line 9 is l'' indicating up, the output of the OR gate 28 is 1. ”,2
The output of the counter 9 becomes 0'', and the counter control output 16 becomes 0'' and the clock is stopped in the same way as in the above case. In other cases, the counter control output is '1'', and the clock is changed by the up or down command from track 9. Table 1: Corresponding up/down counter outputs in the CPU Shutter priority Aperture priority 05 C4C3C2C1 Table 1 is the up/down counter This shows the correspondence between the output of 2 and the control output of shutter priority or aperture priority in CPH.It uses 18 of the combinations of 5-bit counter outputs C3 to C1 to determine the shutter speed or aperture value required for actual shooting. You're getting a step change.

FIG. 5 is a circuit diagram showing an embodiment of the display control device 5 in FIG. 1. As shown in the figure, the device is AND, OR,
Consists of a NAND gate and an inverter,
Clock pulses from clock pulse generator 7, line 1
From 6 is the counter control output, from 17 is the clock input controller, from lines 10, 11, 12 and 14 is the CP
Each command signal from U for single digit, aperture digit, warning, and priority setting is input to device 5, and the output from 5 is transmitted to the display device via lines 18 and 19 to display the shutter speed and aperture value. etc. will be displayed.

To explain an example of the operation of the device shown in the figure, the CPU 3 in FIG.
When the counter output inputted to is within the appropriate exposure setting range, the input from 16 is '1'', and the warning manual input from the CPU 12 is 0''. Now considering the case where the priority setting is set to shutter priority mode, the track 14 becomes "l",
With these inputs, the outputs of AND gates 30 and 31 are both '0°', and the output of AND gate 34 is 'O'.
Since line 16 is '1', NAND gate 3
The output of 3 is '1'', which is 0, and the output of the NAND gate 32 is also 1'', and the inputs of the AND gate 36 are all l'', except for the shutter digit signal 10, so the output of the AND 35 is 1.8, which is the shutter digit of the CPU. Signal ゛10 is output f
L% This is sent to the display device 6 and the shutter time is displayed. Similarly, in the case of aperture priority mode, the inputs of the AND gate 46 are all 61'' except for the aperture digit signal 11, and the output of the AND gate 45 is 1.
An aperture digit signal 11 from the CPU is outputted to 9.

Next is the setting value of up/down counter 2.

When the limit value of the setting range is reached, 16 becomes '0'.
0. Since the output of the R circuit 50 changes to "0" and "1" with the output of the clock generator 7, that is, the clock cycle, the signals of the outputs 18 and 19 of the display control device also change to "0" and "1" accordingly.
1'' is periodically repeated, the display on the display device 6 repeatedly blinks.As described above, each input line in the display control device of FIG. When the value changes in various ways, the shutter digit signal 10 or the aperture digit signal from the CPU is controlled in various ways by the display control device 5 and is generated at the output 18 or 19. The display changes in various ways.

2nd Table In the figure, the numbers in the output 18 and 190 columns are 1 shutter digit.
0 and the aperture digit are indicated by 11. The number surrounded by a circle indicates continuous lighting, and the number surrounded by a table mark indicates blinking. Note that "0" indicates off.

Next, a few examples of the various operations of the display control device shown in FIG. 5 shown in Table 2 will be explained.

Logic r0011J shown in the second and third rows of Table 2
rooloJ indicates control of information display during setting of priority setting information, and JOOIIJ indicates a case where setting values and calculation results during setting of shutter priority are both within the control range. In this case, each input signal in FIG. 5 is 0'' for 17, 0'' for 12, and 1'' for 16.

14 becomes '1'. The output of NAND33 is '1''.

NAND32 is '1' if clock 7 outputs 1''
Since the output of 0R50 is also '1', all other inputs of AND36 except shutter digit signal 10 are '1', and signal lO passes through 36. oAND35 also has an input of '1'.

1", so the signal 10 is sent to the output 18 of the device. Next, the NAND 43 outputs "0", and the NAND 42
outputs "l". As a result, AND46 passes the aperture digit signal, but since AND45-6 is turned off, signal 11
does not appear on output 19. Therefore, the display in this case is 1
Only the shutter digit signal 10 (setting value) from 8 is displayed, and the aperture digit signal 11, which is the calculation result, is not displayed.

Next, the setting of the priority setting information is stopped, and if both the set value and the calculated value at this time are within the control range, the logic "lO1x" shown in the first row of Table 2 is obtained. × can be set arbitrarily, so if we take the case where the information is set to shutter priority, the logic becomes “10 '11 J,
In this case, both NAND33 and NAND43 are '1
Furthermore, even if the input from the clock 7 is '1' or '10', both NAND32 and NAND42 output '1'. Therefore AND36°35 and AN
'D46, 45 are all on, and the shutter digit signal 10 (setting value) and aperture digit signal 11 (
The calculated values) will both be sent to the display device at outputs 18 and 19, and these two pieces of information will be displayed.

Next, the logic “000
1" and "0000" are cases where the set value exceeds the control range during setting of priority information, and in this case, the second. Input 16 of the third line logic becomes 0''. Shutter digit signal lO and aperture digit signal 11 both output 18.19
AND 36 and 46 repeat on and off states when the input from the clock 7 is 1" and when the input is O", so the display at 18°19 becomes a blinking display. That is, in this case, both the set value (limit value) and the calculated value are displayed blinking.

Next, the logic ro1tt in the 7th and 9th rows of Table 2,
, 1, l'-0110J is a case where the calculated value from the calculation result exceeds the limit value of the control range while setting priority information, and at this time, the warning signal 12 from the CPU becomes 1". Shutter priority is now set. In the case of "0111", NAND3
3 and 43 both output 1".Although the NAND 32 always outputs 1", the NAND 42 outputs 1" when the output of the clock 7 is "L", and O when the output is '0".

Therefore, the set value (shutter digit signal) that passes through AND36.35 always appears at output 18, but the calculated value (aperture digit signal) that passes through AND46.45 blinks at the cycle of clock 7.

As described above, by providing each logic as shown in Table 2 to the display control device of FIG. 5, various changes can be made as shown in the display of the display device.

Figures 6a and 6b illustrate the configuration of a logic circuit for a specific operation among the various operations in the display control device in Figure 5. With such a configuration, the display control output in Figure 6a is set as a display control output. 1, when the set value reaches the set limit value, the set limit value and the calculated value are displayed by continuous lighting, unlike the embodiment shown in Fig. 5. In this case, at least an example of the set value is displayed by flashing seven segments. 6th
In figure a, the signal on line 16 that warns that the set value has reached the limit value becomes the O'' signal, so s NAND3
3 and 43 both have an output of 71'', and 9, a shutter digit input of ``10'' from the CPU, and an aperture invitation input of 11 are all sent to the display device 6 as an output of 18.19. That is, since one of the inputs 10.11 is a set value and the other is a calculated value, this circuit configuration outputs both the set limit value and the calculated value.

Figure 6: 16 is '0'' when the set value reaches its limit value
, 17 become '1' through the inverter 52, and since the on/off signal from the clock signal generator 7 is input to this 160 line through the OR gate, 14 becomes l.
”In other words, in the case of shutter priority, AND35 in 70 cycles
The output of ' is turned on and off, the set value from the line 10 is displayed blinking, and the calculated value from the other line 11 is turned off by the AND gate 45'.

Next, FIG. 7 is a circuit configuration diagram showing another embodiment of the counter control device in FIG.
0, that is, a signal can be sent to the parallel preset input enable terminal of up/down counter 2.

In the figure, counter 2 is now [1,0,0,0,IJ
Assuming that the set limit value of line 9 has been reached, line 9
is the up count command ``'1'', then in the next state [
1, 0, 0, 1, OJ, the output of the NAND gate 62 is 60'', and the output of 0R64 is also '0''. Since the clock input control signal from line 17 is 0'', the output of N0R66 becomes 1, which is sent to the reset terminal of counter 2, and all counters are reset.

Contrary to the above < cow y turf 5f now J0,0,0,0.
Assuming that the OJ is at the set limit value, a down command "0" is input from 9, and in this state, the counter counts down by 1 pulse, and the output of N0R65 is 1".
This is input to the parallel preset input enable terminal of counter 2, and counter 2 inputs the preset manual power P,
~value of pS lx, 0. o, o, tJ are input.

FIG. 8 is a block circuit diagram showing another embodiment of the photographing information setting display method according to the present invention, in which the same parts as in FIG. 1 are indicated by the same symbols, and switches of each input circuit are omitted. . In the embodiment shown in the figure, the difference from Fig. 1 is that the CP
Warning signal 1 when the calculated value from U3 exceeds the control range
2 is transmitted to the display control device 5 and the clock input control device 1 via the inverter 71 and the AND gate 72. According to the circuit arrangement as shown in the figure, the warning 12 indicating that the calculated value is out of the control range can be considered to be completely equivalent to the signal 16 when the set value reaches the limit value range. In other words, when the calculated value is out of the control range, the warning output 12 of the CPU 3 is "1", which is output to the AND gate 72 via the inverter 71.
When "-" is input, the output of the AND 72 becomes 0, which is input to the display control device 5 to display a warning. The operations of the other circuits have been explained in detail with reference to FIG. 1 and the detailed drawings in and after FIG. 2, and will therefore be omitted here. If the circuit shown in FIG. 6a is used as the display control device in FIG. 8, the priority setting value and the calculated value will be displayed simultaneously, and the circuit shown in FIG. This can be done by blinking the value and both values. In this case, the clock input control signal 17 must always be kept at 1'', and since the outputs of the NAND circuits 30' and 40' are 1'', 16' becomes 0'', which causes the clock input control signal 17 to have a period of 10 , and 11 are output as blinking signals at 18.19, respectively.

Next, FIG. 9 is a main block circuit diagram showing another embodiment of the photographing information setting display method according to the present invention. In the embodiment shown, the subject brightness information is converted into digital information by an A-D converter, and is input to the CPU 3 at the same time as input to the preset manual inputs P, .about.P1 of the up/down counter 2.

In this way, when the device is powered on, the digital information from the photometric circuit is immediately preset to counter 2. The monostable multivibrator circuit shown in the figure operates only when the power is turned on, and the input is made to the counter's parallel preset input enable terminal.

FIG. 10 is a block circuit diagram of the main part according to another embodiment of the present invention, and in this circuit, the preset manual power P, ~P, of the up/down counter 2 is in a state of [0°0.1, 0, 0]. is set to . In other words, when the power of the device is turned on in the state of this circuit, if the parallel preset input enable signal is input to counter 2, the above logic value [0
゜0.1.0. A counter will be automatically preset in OJ. In other words, in the case of shutter priority, this preset value [0, 0, 1, 0, OJ is 1/125 seconds, and in the case of aperture priority, it is Fil, so according to the circuit in Figure 10, when the device is powered on, The frequently used shutter speed or aperture value can be preset in the counter 2.

FIG. 11 is also a main block circuit diagram showing another embodiment of the system according to the present invention, and in the circuit shown in the figure, the output R3 of the CPU 3
~R8 is sent to the preset inputs P and ~P of the up/down counter 2, respectively, and a signal is also input from the priority switching signal circuit to the parallel preset input enable terminal of the counter 2 via the monostable circuit. When this circuit is used, the CPU calculates the calculated value according to the setting value set manually to the counter 2, and the calculated value is transferred to the CPU's calculation output terminals R, -R, From the counter's preset input terminal P
, ~P, and the set value of counter 2 is replaced with the calculated value from the CPU at the time of priority switching. In other words, if you use the camera in shutter priority mode and want to take the next shot in aperture priority mode using the aperture value obtained from information from the photometry circuit, etc., this circuit will simply switch the priority selector switch SW. By switching 3, the previously obtained aperture value is automatically set on the counter, making it possible to quickly switch the priority mode. This is a block circuit diagram showing an example of an application of the method, and is an example in which a nonvolatile memory is used as a counter memory of the device. As the non-volatile memory, a recently developed MNOS (semiconductor device using metal nitride/oxide) is used. In the figure, 2' is a non-volatile counter memory constructed using MNOS, and a clock signal to this is inputted from the clock input control device 1 through line a-.

This human clock drives an external pulse generator through a delay circuit, which delivers a +25V pulse to line vM when the counter transient is over and a safe condition is established. This pulse sets the threshold of the memory transistor 2 in the counter to -2V. Then, the pulse voltage of VM returns to -25V. At this time, corresponding to the state of the binary counter, some of the memory transistors have a threshold of 11ov.
Changes to As a result, the count value of the counter is held in the memory transistor. The other circuit configurations and operations are the same as those described in FIG. 1 and subsequent figures, so their explanation will be omitted.

Next, FIG. 13 is a perspective view illustrating the appearance of an embodiment of the camera using the photographing information setting display method according to the present invention.
4 is arranged on the top and front surface of the camera body, and it is desirable that the arrangement be optimal for photographing operations.

FIGS. 14 and 15 are perspective views showing one embodiment of the configuration of the operation button (or lever) provided on the camera body and each switch inside the camera body in the method of the present invention. In the figure, reference numeral 101 denotes an operation button for setting information, which is rotatably supported by a switch board 102 by a mechanism not shown. S w 1 and S w 2
1 is the up/down direction command switch and clock input control switch shown in FIG. 1, and by pressing the right or left protrusion of button 101, setting information is stepped up or down. Reference numeral 103 is a push button for operating the display control switch S w 4. In the arrangement shown in Fig. 15, this display control switch S w
4 can be operated either by operating the button 103 or by operating the setting button 101. The first stroke of the button 101 turns on the display switch Sw4, and the second stroke of the button 101 turns on the display switch Sw4. And Sw
1, 8w2 is turned on.

As described above, in the shooting information setting display method according to the present invention, the setting information is changed stepwise by the operating means such as a button located at an appropriate location on the camera, and is displayed together with the calculated value obtained from the calculator. It is possible to display appropriate operation information such as various priority shooting modes, setting operations and warning displays when the control operation range is out of range. is a great thing.

[Brief explanation of drawings]

FIG. 1 is a block circuit diagram showing an embodiment of the photographing information setting display method according to the present invention, FIG. 2 is a circuit configuration diagram showing an embodiment of the clock input control device in FIG. 1, and FIG. A curve diagram showing an example of a timing chart of the circuit shown in the figure, Fig. 4 is a circuit configuration diagram showing an example of the counter control device in Fig. 1, and Fig. 5 is an example of the display control device in Fig. 1. FIG. 6 is a circuit configuration diagram showing a logic circuit for a specific operation of the display control device in FIG. 5, FIG. 7 is a circuit configuration diagram showing another embodiment of the counter control device, and FIG. 9 is a block circuit diagram showing another embodiment of the method of the present invention, and FIGS. 9, 10, and 11 are block circuit diagrams showing other embodiments of the method of the present invention, in particular, the key points for causing the counter to perform a specific operation. 12 is a partial circuit configuration diagram, FIG. 12 is a block circuit diagram showing an example of application of the method of the present invention, FIG. 13 is a perspective view showing the external appearance of a camera according to the method of the present invention, and FIG.
FIG. 15 is a perspective view showing an embodiment of the configuration of operation buttons and changeover switches provided on the outer surface of the camera. 1... Clock input control device, 2... Up/down counter-13... Central control unit (CPU). 4. Counter control device, 5... display control device. 6. Display device, 7. Clock signal generator. 8. Self-maintenance timer. Patent Applicant: Canon Co., Ltd., 1 CP 8U Procedural Amendment (Spontaneous) 10/9/1980, Mr. Wakasugi Wakasugi, Commissioner of the Japan Patent Office 1, Indication of Case Patent Application No. 110727 of 1975 Patent Application (8) 2 filed on September 10, 1988, which is a divisional application, Name of the invention Camera information setting device 3, Relationship with the case of the person making the amendment Patent applicant address 3- Shimomaruko, Ota-ku, Tokyo 30. −． 2-
,,,,-Name (100) Canon Co., Ltd.
...Representative: Ryu Kaku Sanbe 4, Agent Address: 3-30-26 Shimomaruko, Ota-ku, Tokyo 146
Full text of the specification subject to amendment Drawing 7 Contents of amendment (1) The specification is corrected as shown in the attached sheet. (2) Correct Drawing 1, Figure 1, and Figure 2 as shown in the attached sheet. . (8) Drawings, Figures 4, 5, 6 (a), 6
Figure (b), Figure 8, Figure 9, Figure 10, Figure 11. Figures 12, 13, 1'4, and 15 are deleted. (4) Correct the drawings and Figure 7 as shown in red ink on the attached sheet.0 Description 18'' Name of the invention Camera information setting device 2, Claims determining device.Digital for forming and updating a digital signal Signal. 3. Detailed Description of the Invention The present invention relates to a shutter speed in a camera, etc. A device for setting photographing information such as an aperture value, in particular, setting and changing information electrically by operating a push button switch, etc. In a camera equipped with an exposure control circuit, conventionally, in order to set photographing information in variable elements of the circuit, mechanical information setting such as a shutter dial, aperture ring, etc. is used. This was done by manually operating the mechanism to change the position of the variable element that interlocked with these elements.Therefore, the conventional force type had drawbacks such as not only being not very easy to operate, but also taking up a lot of space. A method to overcome the above drawback is to supply pulses to a digital signal forming means such as a counting circuit by operating a push button or the like located at an appropriate location on the camera, and to perform a counting operation in the counting circuit. One possible method is to simultaneously form and update a digital signal and set the exposure information as the count value (digital value) of the counting circuit.However, according to this method, as long as the push button is pressed, the contents of the counting circuit are is updated, there is a risk that a digital value corresponding to a value exceeding the exposure value that can be set in the counting circuit may be set.In other words, if a 5-bit counter is used as the counting circuit, the counting circuit is r O, 0, 0, 0, OJ ~ r 1.-1.1.1.
It is possible to set digital prices corresponding to 32 different exposure values from I to J. Now, assuming that r O, 0, 0, 0, OJ are digital values representing head seconds, we can divide the 32 digital values into shutter seconds for each step.
It is possible to set extremely long seconds from - seconds to 120 hours. However, the camera has its controllable limits, for example, its maximum speed is in seconds, In addition, if the minimum speed per second is 60 seconds, there are 18 digital values from r O, O, O, O, O, J to r 1, 0, 0.0. l J. It is sufficient if the value can be set, and it is not possible to execute -L.The present invention has been made in view of the above matters, and the digital signal is updated by the digital signal forming means by pressing the push button. , when the digital signal reaches the upper limit of the settable exposure Qti of the camera representing the minimum speed per second or maximum aperture, the digital value is automatically changed to the camera representing the maximum speed per second or the minimum aperture. The exposure value is shifted to the lower limit value, and from this state the digital value continues to be updated in the direction of the above lower limit value, and while the push button is operated, the set digital value is always the above minimum seconds or maximum aperture value. (upper limit value) and the maximum second or minimum aperture value (lower value).In the above case, the digital signal is frequently updated from the lower limit value to the upper limit value, but the upper limit value When the value is updated in the direction of the lower limit value, when the digital signal reaches the lower limit value, the digital value is automatically shifted to the upper limit value to prevent setting. Detailed Description of the Invention: Figure 1 is a block circuit diagram showing an embodiment of the camera information setting system of the present invention.The figure is a block diagram of a camera information setting and display device. In the figure, each human power and output terminal indicates a transmission terminal for input signals and output signals from each part of the digitally controlled camera. In the figure, Vc attached to each terminal indicates one pole of the camera's power supply, The other pole is connected to the part indicated by the ground symbol.Ia is the input terminal of the circuit for switching the direction of increasing or decreasing the set value, and when the switch SW1 is turned on, logic "11" is sent to the transmission path 9. The switch SW1 is connected to an up/down mode switching means (not shown).Up/down counter 2, which constitutes a digital signal forming means, receives the input from this switch 9. When it is "l", move in the up direction, "
When the count is 0'', step counting is performed in the down direction.The terminal Ib is a terminal for controlling the clock pulse for the counting, and when the switch SW2 is on, a 0'' signal is sent to the transmission path 17, and when it is off, a 1'' signal is sent. The 5th SW will be
. turns on when the operation button is pressed. Clock pulses are generated by a clock pulse generation circuit 7, and set values and other values change stepwise at the cycle. The clock pulse generated at this point 7 is the clock input control circuit t'6.
The signal is applied to the CP input of the up/down counter 2 via the line 9, and is counted in steps according to the up/down force direction instructions from the line 9. The clock input control signal from Ib is also transmitted to the counter control circuit 4 and the display control circuit 5 through the line 17. Terminal Ic is up.
Due to the self-holding action of the timer 8 inserted into the power supply circuit of the down counter 2, the supply to the counter 2 is maintained for a certain period of time even if the power to the device is turned off. There is. 3 is a central control unit (CPU) serving as an exposure calculation circuit, and a priority command signal from a brightness information % terminal Id from a photometer including a light receiving element and an output signal 15 from a counter 2 are sent to it.
The brightness information and counter 2 are input and set in n.
Exposure calculations are performed on the exposure information obtained, and control signals to the shutter control and aperture control sections as well as various signals as shown in the drawings are sent to the display control circuit 5 as outputs. The switch SW in the Id circuit is a priority mode changeover switch, and when 8w3 is on, the camera operates in shutter priority mode, and when it is off, the camera operates in aperture priority mode. Among the signals sent from the 0PU3 to the display control circuit 5, the set value and the shutter digit signal of the shutter time and the aperture value as the calculated value and the shutter digit signal of the aperture value are controlled by the signal from the terminal Ie. The display is stopped or blinked by turning on or off Vζ of n, sw, which is transmitted through the gate. Note that a warning signal ("1'" signal) for displaying various warnings such as that the calculated output value has reached the control limit for the exposure value of the camera is sent directly to the display control circuit 5 via the line 12, and the display segment The signal is sent directly from the CPU to the display circuit 6. The output 15 of the up/down counter 2 is input to the CPU and also to the counter control circuit 4.
Further, the circuit 4 is applied with the clock control signal 17 to the clock input control circuit 1, and outputs a counter control signal to its output, which is sent to the parallel presettable input terminal of the up/down counter 2. As shown in the figure, the display control circuit 5 receives clock pulses from a clock pulse generator 7' and signals from a line 17, and performs control operations for various displays according to various commands 10, 11 and 14 from the CPU. Shutter seconds and hours digit signal 10 as a set value and calculated value to its output. Aperture girder, signal 11
Output. These display signals are input to the display circuit 6, and various information displays are displayed in, for example, a finder according to display segment commands from the CPU. The display circuit is composed of a combination of known segment and digit drivers, 7-segment LEDs, and other display elements. The configuration and operation of FIG. 1, which shows an overview of the system, have been explained above, but examples of the circuits constituting the main blocks of FIG. 1 will be explained in detail with reference to FIG. In the following drawings, the same parts as in FIG. 1 are designated by the same reference numerals. FIG. 2 is a circuit diagram showing an embodiment of the lock input control circuit l in FIG. 1, and FIG. 3 is a curve diagram showing an example of a timing chart of the device shown in FIG. In the figure, the pulse from clock pulse generator 7 is
The waveform will be as shown in Figure (a). 23f''i For example, a frequency divider consisting of a circuit such as a flip-flop has a signal having a waveform as shown in Fig. 3 (b) at its output. All clocks are synchronized at the falling edge of the pulse. The output Q of the n1 counter 21 is ANDNed via the inverter 27.
Since it is returned to the O gate, 21 outputs sQ4 and at the same time inhibits clock input. FIG. 3(C) shows the input of the clock input control circuit 1, which is "1" when the switch SW2 is off, and "O" when it is on. This signal also becomes the CP input of the up/down counter 2 via the reset input of the counter 21 and the OR gate 25. The Q4 output of the counter 21 becomes the second input of the ANDNO gate, and is ANDed with the divided output of the clock and ORed.
, 25' to the CP of the up/down counter 2, and converts the 20 counts of the up/down counter into 1 step &. (E) in Figure 3 shows the case where the clock input control switch SW2 is on for a long time. In this case, when the output of the counter 21OQ becomes "l" (Figure (E))K, as shown in Figure 3 (G). The up/down counter 2 immediately starts counting. As a result, when continuing to operate the set value, the time between each step after the second step is shortened, and the operation switch SW2 is kept in the operated state (on).
If K is held, the contents of the counter as a digital signal forming means will be sequentially updated, and the digital value as its output will be sequentially updated. FIG. 4 is a circuit diagram showing an embodiment of the counter control circuit in FIG.
．． 62 is a NAND gate that detects the contents of counter 2, 63, 64, and 67 are OR gates and inverters.
These OR gates and inverters constitute selection means for selecting one of the NAND gates in response to an up or down command from the line 9. 65° and 66 are NOR gates, and the output of the NOR gate 65' is connected to the parallel preset input enable terminal of the counter;
Information on the preset human power P, ~P, VC applied to the counter 2 is preset by "l IIK" from the gate 65. Also, the output of the NOR gate 66 is connected to the reset terminal of the counter 2, 1'' from 66 resets the counter. The operation shown in FIG. 4 will be explained using Table 1 showing the correspondence between the contents of the counter 12 and the shutter speed value or aperture value. It is now assumed that the switch SW2 in FIG. 2 is on, a clock is being supplied to the counter 2, and information is being set. ? It is assumed that io1 and switch SW are set on, an up-count command "'l" is output from line 9, and the counter is in up-count mode. Table 1 Up/down counter output Shutter value Aperture value 05 04 C30201 00000200022 00001100019 o o o i o soo
160 0 0 1 1
250 130 0 1 0 0
125 11da0010160 9.5 oo,tto 30
s. Nno 010111 3.5p
011002- 2.8011014-
2.5 011108- 2.0 0 1 1 1 1 15-
1.81 0 0 0 0 30-
1.41000160-1.2 In the process of setting the above information, the contents of counter 2 indicate the camera's lowest controllable shutter speed of 60 seconds or the maximum aperture value PI,2 (upper limit value) r 1 ．．
0.0,0. l Assume that JK has been reached 0 As mentioned above, the counter is in up-counting mode, so when the next count following the above upper limit value is counted, the contents of the counter will be [1° As mentioned above, the switch SW is turned on. [N] resets counter 2]
The contents of the counters sent to the child are reset, and the contents of the two counters become r 0.0. O, 'O, Oj and the parent nucleus "
0゜0, O, 0, OJ means the maximum shutter speed is 2000 seconds and the minimum aperture value F22, and the reading value indicates the lower limit of the controllable value of the camera.
After the count value of the counter is counted up to the upper limit value, the counter moves to the lower limit value, and the count value is increased from this state. Also, contrary to the above, switch SW1 is set to OFF,
When the down count command "0" is output from the counter 9, the counter 2 counts down the clock by turning on the switch SW, and sets information in the countdown mode. In this state, rO as the above lower limit
, 0, 0, O, OJ, in the next countdown operation, this is input to the parallel preset input enable terminal of counter 2, and counter 2 applies a signal r to the preset human power P, ~P, 1.0. O, O, l
J is input and the count is counted down from this state. Above r 1,0,0,0. Since lJ indicates the upper limit value, in the down count mode, after the count value of the counter reaches the lower limit value, it shifts to the upper limit value, and from this state, the count value starts counting down. In this way, in the present invention, when setting information, the contents of the counter cycle between the upper and lower limit values.
The photographer can set the information value to a value within the settable range by simply keeping the switch SW2 on without worrying about the limit of the information setting value of the camera. In the same example, the upper limit shutter value is 60 seconds, the aperture Fl is 2
and the lower limit values are □sho and F22, 000. However, it goes without saying that the upper and lower limits are not limited to these. Also, the counter is reset as a lower limit setting method. Connect the signal source for the upper limit value and the signal source for the lower limit value to the preset input terminal, select the signal source for the upper limit value in the down count mode (by "O" K from 9), and select the signal source for the lower limit value. The upper or lower limit value may be set by connecting a source to the upcal lamp reset input enable terminal. As described above, in the information setting device according to the present invention, a digital value is formed by pressing the button. By sequentially updating the digital value while the push button is pressed, the information setting operation is performed, and when the digital value as the setting information reaches the upper or lower limit of the setting limit, the above-mentioned value is automatically updated. Since the digital value is shifted to the lower limit or upper limit and the update operation is performed from this state, the photographer can cover the whole country in which information can be set, and the information can be set quickly as shown in Figure 1. A block circuit diagram showing an embodiment of the photographing information setting device according to the present invention, FIG. 2 is a circuit configuration diagram showing an embodiment of the clock input control circuit in FIG. 1, and FIG. 3 is a timing diagram of the circuit in FIG. 2. A curve diagram showing an example of a chart, and FIG. 4 is a circuit configuration diagram showing an example of the counter control circuit in FIG. 1. l... Clock input control circuit, 2... Up/down counter-13... Central control unit (CPU). 4...Counter control circuit, 5...Display control circuit. 6...Display circuit, 7...Clock signal generator, 8.
...Self-maintenance timer.

Claims (1)

[Scope of Claims] A digital signal forming means that forms a digital signal by operating an operating switch IIK for setting exposure information and a second switch, and sequentially updates the digital signal when the switch is in an operating state. and a detection circuit that detects the digital signal formed by the digital signal forming means and outputs a signal of setting exposure 2 corresponding to the digital signal, and from the detection IfIn path? II' In response to the signal of 1, the digital signal of the digital signal forming means is changed to a digital signal corresponding to the lower limit value, and in response to the second signal, the digital signal is changed to a digital signal corresponding to the upper limit value. An information setting device for a camera, characterized in that it is equipped with a control circuit for changing the information.