JPS5877331A - Logical circuit - Google Patents
Logical circuitInfo
- Publication number
- JPS5877331A JPS5877331A JP56175670A JP17567081A JPS5877331A JP S5877331 A JPS5877331 A JP S5877331A JP 56175670 A JP56175670 A JP 56175670A JP 17567081 A JP17567081 A JP 17567081A JP S5877331 A JPS5877331 A JP S5877331A
- Authority
- JP
- Japan
- Prior art keywords
- resistor
- terminal
- voltage
- field effect
- gate
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
Classifications
-
- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03K—PULSE TECHNIQUE
- H03K19/00—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits
- H03K19/02—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits using specified components
- H03K19/08—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits using specified components using semiconductor devices
- H03K19/094—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits using specified components using semiconductor devices using field-effect transistors
- H03K19/0952—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits using specified components using semiconductor devices using field-effect transistors using Schottky type FET MESFET
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- Engineering & Computer Science (AREA)
- Power Engineering (AREA)
- Physics & Mathematics (AREA)
- Computer Hardware Design (AREA)
- Computing Systems (AREA)
- General Engineering & Computer Science (AREA)
- Mathematical Physics (AREA)
- Logic Circuits (AREA)
Abstract
Description
【発明の詳細な説明】
本発明は、メタルショットキバリア電界効果トランジス
タ（以下ＭＥＳＦＥＴと称す）の論理回路に関するもの
である。DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a logic circuit of a metal Schottky barrier field effect transistor (hereinafter referred to as MESFET).
ＭＥＳＦＥＴ の論理回路方式がいくつか提案さｎてい
るが、その１つに、直接接続論理回路方式（以下にＤＣ
ＦＬと称すンがめる。第１図にそのｎチャネルの基本と
なる回路を示す。１と２Ｆｉ、ゲート入力Ｏｖｏ時は電
流がｍれないエンハンスメ／）ＭＥＳＦＥＴ−１（以下
に１ＭＥ８と称す）である。３と４は、負荷で抵抗やゲ
ート入力Ｏｖ。Several MESFET logic circuit systems have been proposed, one of which is the direct connection logic circuit system (hereinafter referred to as DC
The game is called FL. FIG. 1 shows the basic circuit of the n-channel. 1 and 2Fi are enhanced MESFET-1 (hereinafter referred to as 1ME8) in which no current flows when the gate input is Ovo. 3 and 4 are loads such as resistance and gate input Ov.
暗でも電流が流れるデプレションＭＥＳＦＥＴのゲート
とソースを接続したものが用−られる。入力瑠子１００
に入力が印加されるとＥＭＢＢ１が入力に応じてオン、
オフして負荷３を流れる電流を変化させ、出力端子１０
１の電圧を変える。A depletion MESFET with the gate and source connected, which allows current to flow even in the dark, is used. Input Ruko 100
When an input is applied to , EMBB1 turns on according to the input,
turns off and changes the current flowing through load 3, output terminal 10
Change the voltage of 1.
この回路方式の欠点ＦｉＭ子１０１の電圧が制限される
ことである。ＭＥＭ８のゲートとソースはショットキダ
イオードとなって−るため、ＥＭＢＢがオフしても電電
流が負荷３とＥＭＢＢ２のゲートソースダイオードに流
れ、出力１０１ｙｉＡ子はダイオードの立ち上がり電圧
付近となる。このようにＤＣＦＬ回路の振幅は％ＭＥＳ
１がオンになった時のＯｖ付近と、ダイオードの立ち上
がシミ圧付近となる。このように論理振幅が小さいので
ＤＣＦＬは雑音に弱い欠点があった。A drawback of this circuit system is that the voltage of the FiM element 101 is limited. Since the gate and source of MEM8 are Schottky diodes, even if EMBB is turned off, current flows to the load 3 and the gate-source diode of EMBB2, and the output 101yiA becomes close to the rising voltage of the diode. In this way, the amplitude of the DCFL circuit is %MES
It is near Ov when 1 is turned on, and near the rising stain pressure of the diode. Since the logic amplitude is thus small, the DCFL has the disadvantage of being susceptible to noise.
またこのことはＤＣＰＬ回路の自由度を制限している。This also limits the flexibility of the DCPL circuit.
同じ電界効果型ＦＥＴの１つであるＭＯ８（％ｅｔａ１
％Ｑｘｉｄｅ −５ｅｍｉｃｏｎｄｕｃｔｏｒ ） ２
）！多用されているトＩ）／スファーグートを利用した
論理を応用しにくい。One of the same field effect FETs, MO8 (%eta1
%Qxide-5emiconductor) 2
)! It is difficult to apply logic using the frequently used
第２図にｎチャネルトランスファーゲートを示す、ＭＥ
８ＦＥＴｌ＃ｉＥＭＥ８である制御端子１０５が低くＭ
Ｅ８ＰＥＴがオフであれば、入力端子１０５の入力が変
化しても出力端子１０６のｂ力には影響しない。制御基
子１０５か高レベルの場合は、入力端子１０４の入力が
低ければ、端子１Ｏ９４の入力をソースとするソース接
地回路となり、電流が１０６から１０４へ流れる。逆に
入力端子１０４０入力が高い場合は、１０４をドレイン
とするドレイン接地となり、１０４から１０６へ充電す
る。この充電の時１０６は１０５の電圧からＥＭＥ８１
（ＤＬ！い電圧（＞０Ｖ）ｔ−引イタものより高くなら
ない。このことより、１０６の論理出力は１０５の論理
入力よシさらに小さくなる。Figure 2 shows an n-channel transfer gate, ME
The control terminal 105, which is 8FETl#iEME8, is low
If the E8PET is off, even if the input to the input terminal 105 changes, the b force at the output terminal 106 will not be affected. When the control base 105 is at a high level and the input to the input terminal 104 is low, the circuit becomes a common source circuit with the input of the terminal 1094 as the source, and current flows from 106 to 104. On the other hand, when the input to the input terminal 1040 is high, the drain is grounded with 104 as the drain, and 104 is charged to 106. During this charging, 106 is EME81 from the voltage of 105.
(DL! Voltage (>0V) will not be higher than that of the t-inverter. From this, the logic output of 106 becomes even smaller than the logic input of 105.
このように、ＤＣＦＬで論理出力を大きくする必要がめ
ることが多い。本発明はこれを実現する回路を提供する
ことにるる。As described above, it is often necessary to increase the logic output of a DCFL. The present invention consists in providing a circuit that realizes this.
Ｉ！３図に本発明の一実施例であるｎチャネルの基本回
路を示す。Ｅ Ｍ Ｅ Ｓ ｄ！：オンの時の電圧関係
は第１図の場合とほぼ同一である。１０１と１０２がＯ
ｖ近くなる。これに対し％ＥＭＥＳ１がオフの時は、電
流は、負荷３と抵抗６、ＥＭＥ８２のゲート・ソース間
のダイオードＷＥれる。このため、１０２はダイオード
の立ち上がり電圧となる。I! FIG. 3 shows a basic n-channel circuit according to an embodiment of the present invention. E M E S d! :The voltage relationship when turned on is almost the same as in the case of FIG. 101 and 102 are O
It gets closer to v. On the other hand, when %EMES1 is off, the current flows through the load 3, the resistor 6, and the diode WE between the gate and source of the EME82. Therefore, 102 becomes the rising voltage of the diode.
しかし、端子１０１の論理出力は、端子１０３電源の電
圧を負荷３と抵抗６で分圧した電圧となる。However, the logic output of the terminal 101 is a voltage obtained by dividing the voltage of the power source of the terminal 103 by the load 3 and the resistor 6.
１０３の電源電圧と負荷３、抵抗６を適当に選べば、論
理振幅音大きくできる。By appropriately selecting the power supply voltage 103, load 3, and resistor 6, the logic amplitude sound can be increased.
第４図にｎチャネルトランスファーゲートに応用した本
発明の他の実施ｆＩｌｔ示す。第２図に抵抗２を付加し
ておる。これは、１つの駆動回路で２つ以上のトランス
ファゲートを動作させる時利点がある。第５図に従来の
抵抗を付加していない場合を示す。もし、１０４がＯｖ
とすると、ＥＭＥ８４０１がオフの時も、負荷４０２と
ＥＭＥ８１のゲートソースダイオード管電流が流れ端子
３０Ｇはダイオードの立ち上がシミ圧となり、端子２０
２の振幅が小さくなる。第６図は第５図に対応する本発
明の他の実施例回路を示す。１０４がＯｖとしても端子
３００は、電源５００とダイオード立ち上がり電圧を負
荷４０２と抵抗３で分割した電圧となる。もし端子２０
４が高レベルであれば、端子２０６は端子３００の電圧
からＥＭＥ８のし・きい電圧を引いたものに近くなる。FIG. 4 shows another embodiment of the invention applied to an n-channel transfer gate. A resistor 2 is added to Fig. 2. This is advantageous when operating two or more transfer gates with one drive circuit. FIG. 5 shows a case where no conventional resistance is added. If 104 is Ov
Then, even when the EME8401 is off, the load 402 and the gate-source diode tube current of the EME81 flow, and the voltage at the terminal 30G becomes the diode rise voltage, and the voltage at the terminal 20G increases.
2 becomes smaller. FIG. 6 shows another embodiment of the present invention, which corresponds to FIG. Even if 104 is Ov, the voltage at the terminal 300 is obtained by dividing the power supply 500 and diode rise voltage by the load 402 and the resistor 3. If terminal 20
If 4 is high, terminal 206 will be close to the voltage at terminal 300 minus the threshold voltage of EME8.
こうして、端子２０６の振幅を大きくすることができる
。In this way, the amplitude of the terminal 206 can be increased.
更に他の実施例でめる論理回路でよく用いられるバスを
第７図に示す。７７がバスでるる。７１はバスの負荷で
める。７２がバスへの出力、７４と７６がバスから双安
定回路への入カドランスファーゲート、ＥＭＥＳ７３と
抵抗７５はバスを直接論理ゲートへの入力である。ＥＭ
Ｅ８７２がオフの時電流は負−７１、抵抗７５とＥＭＥ
Ｓ７３のゲート・ソースダイオードを流れ、バス７７は
抵抗７５がない時よシ大振幅となる。FIG. 7 shows a bus often used in logic circuits included in other embodiments. 77 is the bus ride. 71 is determined by the bus load. 72 is an output to the bus, 74 and 76 are input quadrature transfer gates from the bus to the bistable circuit, and EMES 73 and resistor 75 are inputs from the bus directly to the logic gates. E.M.
When E872 is off, the current is negative -71, resistor 75 and EME
The signal flows through the gate and source diode of S73, and the bus 77 has a larger amplitude than when the resistor 75 is not present.
第８図は２つのトランス７アゲート入力の双安定回路管
示す。ＥＭＥ８１０．１１と負荷１２゜１３と抵抗１４
．Ｉｓからなる双安定回路と、ＥＭＥ８２０，２１と負
荷２２．２３と抵抗２４゜２５からなる双安定回路ｔ”
、ＥＭＥＳ５０、負荷５１と抵抗５２からなる共通の駆
動回路で駆動されるトランスファートー）３０，４０の
入力で動作させている。FIG. 8 shows a bistable circuit with two transformer 7 agate inputs. EME810.11 and load 12゜13 and resistance 14
．． A bistable circuit consisting of Is and a bistable circuit consisting of EME820, 21, load 22.23 and resistor 24゜25 t"
, EMES 50, transfer toes (30, 40) driven by a common drive circuit consisting of a load 51 and a resistor 52.
このように、入力のＭＥ８ＦＥＴのゲートに抵抗を付加
することによシ、多数のトランスファーゲートを駆動で
き、論理振幅を上げることができる。また、抵抗を付加
しない回路との整合もよく、密度を上げたいところなど
では抵抗を付加しなくともよい。In this way, by adding a resistor to the gate of the input ME8FET, a large number of transfer gates can be driven and the logic amplitude can be increased. In addition, it matches well with circuits that do not include a resistor, and there is no need to add a resistor where density is desired to be increased.
以上のごとく本発明は、工／ハ／スメ／ト型メタルショ
ットキバリア電界効果ト２ンジスタについて、前段のド
レイ／と後段のゲート間を抵抗器を介して接続したので
、雑音に対して安定な動作をする論理回路を提供できる
。As described above, the present invention has a metal Schottky barrier field effect transistor of the metal Schottky barrier field effect transistor of the metal Schottky barrier field effect transistor of the metal Schottky barrier field effect transistor of the metal Schottky barrier field effect transistor of the metal Schottky barrier field effect transistor. It is possible to provide a logic circuit that operates.
＠１図、第２図、および第５図は夫々本発明の従来的、
第３図、第４図、第６図、第７図および第８図は夫々本
発明の実施例を示す。
１．２・・・工ンハ／スメント型ＭＥＳＦ’ＥＴ、３゜
Ｉｔ 図
１ＦＪＺ図
／ＩＩ
第 ３Ｓ
罫 ４ 后
箔 ５ 図
）〒 ６ 図
第 ７ 図
￥Ｊ 「 目@Figure 1, Figure 2, and Figure 5 are the conventional,
3, 4, 6, 7 and 8 each show an embodiment of the present invention. 1.2...Engine/sment type MESF'ET, 3゜It Figure 1FJZ Figure/II 3rd S Rule 4 Back foil 5 Figure)
Claims (1)
リア電界効果ト２ンジスタの前段のドレインと後段のゲ
ートを抵抗器を介して接続した論理回路。1. I [Logic circuit in which the drain of the front stage and the gate of the rear stage of eight enhancement type metal Schottky barrier field effect transistors are connected through resistors.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP56175670A JPS5877331A (en) | 1981-11-04 | 1981-11-04 | Logical circuit |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP56175670A JPS5877331A (en) | 1981-11-04 | 1981-11-04 | Logical circuit |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPS5877331A true JPS5877331A (en) | 1983-05-10 |
Family
ID=16000172
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP56175670A Pending JPS5877331A (en) | 1981-11-04 | 1981-11-04 | Logical circuit |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPS5877331A (en) |
Cited By (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US6593906B2 (en) | 2000-03-13 | 2003-07-15 | Seiko Epson Corporation | Display apparatus and information display system using the same |
| JP2010231116A (en) * | 2009-03-28 | 2010-10-14 | Watanabe Kk | Projection screen device |
| US10045448B2 (en) | 2014-10-29 | 2018-08-07 | Shenzhen Royole Technologies Co., Ltd. | Flexible screen module and electronic device having the module |
-
1981
- 1981-11-04 JP JP56175670A patent/JPS5877331A/en active Pending
Cited By (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US6593906B2 (en) | 2000-03-13 | 2003-07-15 | Seiko Epson Corporation | Display apparatus and information display system using the same |
| JP2010231116A (en) * | 2009-03-28 | 2010-10-14 | Watanabe Kk | Projection screen device |
| US10045448B2 (en) | 2014-10-29 | 2018-08-07 | Shenzhen Royole Technologies Co., Ltd. | Flexible screen module and electronic device having the module |
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