JPS5878451A - Semiconductor device - Google Patents
Semiconductor deviceInfo
- Publication number
- JPS5878451A JPS5878451A JP56176803A JP17680381A JPS5878451A JP S5878451 A JPS5878451 A JP S5878451A JP 56176803 A JP56176803 A JP 56176803A JP 17680381 A JP17680381 A JP 17680381A JP S5878451 A JPS5878451 A JP S5878451A
- Authority
- JP
- Japan
- Prior art keywords
- transistor
- layer
- region
- type
- epitaxial layer
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 239000004065 semiconductor Substances 0.000 title claims description 9
- 239000000758 substrate Substances 0.000 claims description 8
- 239000004020 conductor Substances 0.000 claims description 2
- 230000003071 parasitic effect Effects 0.000 description 11
- 230000004888 barrier function Effects 0.000 description 5
- 230000007423 decrease Effects 0.000 description 2
- 239000000969 carrier Substances 0.000 description 1
- 230000015556 catabolic process Effects 0.000 description 1
- 238000010586 diagram Methods 0.000 description 1
- 238000010438 heat treatment Methods 0.000 description 1
- 238000009413 insulation Methods 0.000 description 1
- 238000002955 isolation Methods 0.000 description 1
- 150000004767 nitrides Chemical group 0.000 description 1
- 229920006395 saturated elastomer Polymers 0.000 description 1
- 238000000926 separation method Methods 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
- H10D84/00—Integrated devices formed in or on semiconductor substrates that comprise only semiconducting layers, e.g. on Si wafers or on GaAs-on-Si wafers
- H10D84/60—Integrated devices formed in or on semiconductor substrates that comprise only semiconducting layers, e.g. on Si wafers or on GaAs-on-Si wafers characterised by the integration of at least one component covered by groups H10D10/00 or H10D18/00, e.g. integration of BJTs
- H10D84/65—Integrated injection logic
- H10D84/658—Integrated injection logic integrated in combination with analog structures
Landscapes
- Bipolar Integrated Circuits (AREA)
- Bipolar Transistors (AREA)
Abstract
(57)【要約】本公報は電子出願前の出願データであるた
め要約のデータは記録されません。(57) [Summary] This bulletin contains application data before electronic filing, so abstract data is not recorded.
Description
【発明の詳細な説明】 本発明は特に半導体装置の構造に関する。[Detailed description of the invention] The present invention particularly relates to the structure of a semiconductor device.
近年、半導体集積回路、特にバイポーラ論理集積回路は
その集積化と高速化が着しいが、新しい論３１素子とし
てＩ８Ｌ（Ｉｎｔｅｇｙａｔｅｄ ５ｃｈｏ−ｔｔｋ
ｅｙ ］［、ｏｇｉｃ）が提案されている。In recent years, semiconductor integrated circuits, especially bipolar logic integrated circuits, have become more integrated and faster.
ey][, otic) has been proposed.
これは、第１図にその基本等価回路を示すように％電流
源Ｉが接続されたスイッチングＮＰＮ）う、ンジスタＴ
１のベースに久方端子ＩＮｔ−介して入力信号を供給し
、そのコレクタから複数（３個）のショットキーダイオ
−ＶＤにょ〉絶縁した複数（，３個）の出力を出力端子
ＯＵＴから取〕出すものである。ｔた、この素子の構造
的特徴から、ＮＰＮ）ランジスタＴ１に寄生するＰＮＰ
）ランジスタＴ！が存在する。それ故、この素子は、ト
ランジスタＴ１が飽和した時、トランジスタＴ１のベー
スを工電、タ、コレクタｔベース、そして基板をコレク
タとする寄生ＰＮＰ）ランジスタＴ２が働き、コレクタ
層に蓄積された過剰キャリヤを基板へ逃がす仁とによっ
てＮ、ＰＮ）ランジスタの飽和を浅くシ、スイッチング
特性が改善されるという利点含有する。This is a switching NPN to which a current source I is connected as shown in Fig. 1, its basic equivalent circuit.
An input signal is supplied to the base of 1 through the terminal INt-, and the outputs of a plurality of (3) Schottky diodes (VD) isolated from the collector are taken from the output terminal OUT. It is something to put out. In addition, due to the structural characteristics of this element, PNP parasitic to the NPN transistor T1
) Langista T! exists. Therefore, in this device, when the transistor T1 is saturated, the parasitic PNP (PNP) transistor T2 whose collector is the base of the transistor T1 and the base of the transistor T1 acts to remove excess carriers accumulated in the collector layer. This has the advantage that the saturation of the N, PN (N, PN) transistors can be reduced shallowly by allowing the conductor to escape to the substrate, and the switching characteristics can be improved.
第２図にこのＩ８Ｌの基本構造を示す、す表わち、Ｐ形
基板１上に形成されたＮ形エピタキシカル層４表面から
ベース５及び工電、夕（ｌ形成し、コレクタに複数個（
図では２個）のし、ットキーバリャ電極ｉｏ、ｔｔｔ−
形成して第１図のシヨ。The basic structure of this I8L is shown in FIG. (
In the figure, there are 2 electrodes), ttt key barrier electrode io, ttt-
Formed as shown in Figure 1.
トキーパリャダイオードＤを形成し、また、Ｐ形基板ｌ
とＮ形エピタキシャル層４界面のエミ、り６直下とショ
ットキーバリヤダイオード１０．１１直下にのみ高濃度
のＮ形埋込層２を有し、そして外部ペース領域５′直下
にはＰ形基板ｌが相対している構造である。通常のバイ
ポーラ集積回路は、Ｎ形埋込層２が外部ペース領域５′
直下まで形成されているが、Ｉ８Ｌでは一上述のごとく
外部ペース領域５′直下にはＰ型基板ｌが相対している
ため一外部ベース領域５を二電、タ、エピタキシャル領
域４をペース基板１をコレクタとする寄生ＰＮＰ）ラン
ジスタが存在する。A P-type substrate l is formed.
The N-type buried layer 2 has a high concentration only directly under the emitter layer 6 and the Schottky barrier diode 10, 11 at the interface between the N-type epitaxial layer 4 and the N-type epitaxial layer 4. This is a structure in which the two are opposite to each other. A typical bipolar integrated circuit has an N-type buried layer 2 in an external space region 5'.
However, in I8L, as mentioned above, the P-type substrate 1 is located directly below the external base region 5', so the external base region 5 is connected to the external base region 5, and the epitaxial region 4 is connected to the space substrate 1. There is a parasitic PNP transistor whose collector is
上記の特徴をもつＩ８Ｌのスイッチング時間では次式で
表わせる。The switching time of I8L having the above characteristics can be expressed by the following equation.
ここでｆｙ（νＮｒ）は寄生ＰＮＰ）ランジスタＴ３の
し中断周波数、Ｆはファンアウト数をそれぞれ示す。Here, fy(νNr) represents the interruption frequency of the parasitic PNP transistor T3, and F represents the fan-out number.
上式に示すように、ＩＬＬのスイッチング時間は寄生Ｐ
ＮＰ）ランジスタｆテに逆比例する。従って％Ｉ８Ｌの
スイッチング時間を小さくするには、寄生ＰＮＰ トラ
ンジスタのｆｔｔ−上げる、すな′わち１１２図のエピ
タキシャル層４の厚さを小さくしてベース幅を小さくす
ればよいことがわかる。As shown in the above equation, the switching time of ILL is determined by the parasitic P
NP) is inversely proportional to transistor f. Therefore, it can be seen that in order to reduce the switching time of %I8L, the ftt- of the parasitic PNP transistor can be increased, that is, the thickness of the epitaxial layer 4 shown in FIG. 112 can be reduced to reduce the base width.
しかしながら、エピタキシャル層４會薄くすればＮＰＮ
）ランジスタの耐圧が下がる。特にＩ８Ｌとアナログト
ランジスタを共存させる場合、アナログトランジスタの
十分な耐圧を取ることができない、逆に、アナログトラ
ンジスタの耐圧を取る２Ｊ６のエピタキシャル厚４ｔ−
厚くすると寄生ＰＮＰトランジスタの７１が下がって、
スイッチツクスピードが上がらないという欠点があった
。However, if the epitaxial layer is made 4 times thinner, NPN
) The withstand voltage of the transistor decreases. In particular, when I8L and analog transistors coexist, it is not possible to obtain sufficient breakdown voltage for the analog transistor; conversely, the epitaxial thickness of 2J6, which is 4t-
When it becomes thicker, 71 of the parasitic PNP transistor decreases,
The drawback was that the switching speed did not increase.
本発明の目的は、かかる従来のＩ８Ｌの欠点を解決し、
アナログトランジスタと共存できる高耐圧、高速のＩ８
Ｌの構造を提供するものである。The purpose of the present invention is to solve the drawbacks of the conventional I8L,
High-voltage, high-speed I8 that can coexist with analog transistors
This provides the structure of L.
本発明による構造は、外部ペース領域直下にＰ屋置込層
を有することを基本とする。The structure according to the present invention is based on having a P-layer placement layer directly below the external pace area.
以下、本発明の一実施例管図面を用いて詳細に説明する
。第３図に本発明の一実施例の構造を示す、すなわち、
Ｐ形基板ｌ上にＮ形エピタキシャル層４ｔ−形成し、エ
ピタキシャル層４表面からペース領域５およびニオツタ
領域６ｅ形成する。エピタキシャル層４でなるコレクタ
領域には複数個のショットキーパリヤ電極１０，１ｌｔ
−形成してシ、、トキーバリャダイオード管形成しそい
る。EMBODIMENT OF THE INVENTION Hereinafter, one embodiment of the present invention will be explained in detail using pipe drawings. FIG. 3 shows the structure of an embodiment of the present invention, namely:
An N-type epitaxial layer 4t is formed on a P-type substrate 1, and a space region 5 and a nitride region 6e are formed from the surface of the epitaxial layer 4. A plurality of Schottky parry electrodes 10, 1lt are provided in the collector region formed by the epitaxial layer 4.
- Forming a barrier diode tube.
エピタキシャル層４′ｔ′基板１との界面にはＮ形埋込
層２がエミッタ領域６とショットキーパリヤ直下に形成
されている。そして、上述した目的のために外部ペース
領域５′直下にＰ形墳込層７を形成するものである。こ
のＰ型埋込層７は工さ、り領域６直下を除くペーメ領竣
直下に形成している。At the interface with the epitaxial layer 4't' substrate 1, an N-type buried layer 2 is formed directly below the emitter region 6 and the Schottky parier. For the above-mentioned purpose, a P-shaped buried layer 7 is formed directly below the external space area 5'. This P-type buried layer 7 is formed directly under the finished area except for the area directly under the recessed area 6.
尚、３は絶縁分離領域である。Note that 3 is an insulation isolation region.
寄生ＰＮＰ）ランジスタは、ＮＰＮ）ランジスタのペー
ス５を工電、夕、エピタキシャル層４ｔ−ペース、そし
てＰ形堀込層７をコレクタとして形成される。このＰＮ
Ｐ）ランジスタのベース幅ハ、Ｐ形埋込層１とＮＰＮ）
ランジスタのペース５０間の距離で決定され、エピタキ
シャル層１の厚さに依存しない。従って、熱処理時間を
適当に設定すれば、エピタキシャル層４の厚さを十分厚
くし、かつＰＮＰ）ランジスタのベース幅も小さくテキ
る。従って、スイッチング時間も小さくできる。The parasitic PNP transistor is formed by using the NPN transistor's base 5 as a base, an epitaxial layer 4 as a base, and a P-type digging layer 7 as a collector. This PN
P) Base width of transistor C, P type buried layer 1 and NPN)
It is determined by the distance between the transistor paces 50 and does not depend on the thickness of the epitaxial layer 1. Therefore, by appropriately setting the heat treatment time, the thickness of the epitaxial layer 4 can be made sufficiently thick, and the base width of the PNP transistor can also be made small. Therefore, switching time can also be reduced.
尚、エピタキシャル層４の厚さｔｌＯ〜１５μ程度にす
れば、ア。ナログトランジスタの耐圧として２０〜ＳＯ
Ｙ程度得られる。一方、寄生ＰＮＰ）ラノジスタのベー
ス幅は、Ｐ型埋込層７によって１〜５μ程度に設定でき
る。Incidentally, if the thickness of the epitaxial layer 4 is set to about tlO~15μ, A. 20~SO as the withstand voltage of analog transistor
About Y can be obtained. On the other hand, the base width of the parasitic PNP (parasitic PNP) lano resistor can be set to about 1 to 5 μm by the P-type buried layer 7.
以上説笥したように、本発明によって、Ｉ８Ｌトー存す
るアナログトランジスタの耐圧を十分高くすることがで
き、かつＩ８Ｌのスイッチング時間も十分小さくするこ
とができる０本発明は、各領域の導電Ｗをすべて入れ換
えてもよいものである。As explained above, the present invention makes it possible to sufficiently increase the withstand voltage of the analog transistors present in the I8L, and also to sufficiently reduce the switching time of the I8L. It can be replaced.
第１図はＩ８Ｌの基本等価回路図、第２図は従来のＩ８
Ｌの構造断面図、第３図は本発明の一実施例の構造断面
図である。
Ｔト・・・・・スイッチングＮＰＮ）ランジスタ、Ｔト
・・・・・寄生ＰＮＰ）ランジスタ、Ｄ・・・・・・シ
ョットキーバリヤダイオード、■・・・・・・電流源、
ＩＮ・・・・・・入力端子、ＯＵＴ・・・・・・出力端
子、ｌ・・・・・・Ｐ型基板、２・・・・・・Ｎ形埋込
層、３・・・・・・絶縁分離層、４・・・・・・Ｎ型エ
ピタキシャル層、５・・・・・・ペース領域、６・・・
・・・工さツタ領域、７・・・・・・Ｐ型埋込層、８・
・・・・・ベース電極、９・・・・・・エミッタ電＆、
１０．１１・・・・・・ショットキーバリヤ電極。
Ｘ７ 図
篤？図Figure 1 is the basic equivalent circuit diagram of I8L, Figure 2 is the conventional I8
FIG. 3 is a structural cross-sectional view of an embodiment of the present invention. T: Switching NPN) transistor, T: Parasitic PNP) transistor, D: Schottky barrier diode, ■: Current source,
IN...Input terminal, OUT...Output terminal, l...P-type substrate, 2...N-type buried layer, 3...・Insulating separation layer, 4...N-type epitaxial layer, 5...Pace region, 6...
... Engineered ivy region, 7 ... P-type buried layer, 8.
...Base electrode, 9...Emitter electrode &,
10.11... Schottky barrier electrode. X7 Zuatsu? figure
Claims (1)
体層と、誼半導体層に形成された一導電型の半導体領域
とを有してなる半導体装置において、上記手導体領域下
に一導電型の第１ｍ込層と反対導電型の第２１１込層と
が並設して形成されていることを特徴とする半導体装置
。In a semiconductor device comprising a semiconductor layer of an opposite conductivity type formed on a semiconductor substrate of one conductivity type, and a semiconductor region of one conductivity type formed on an opposite semiconductor layer, one conductivity type is formed under the first conductor region. A semiconductor device characterized in that a first m-type layer and a 211-th layer of an opposite conductivity type are formed in parallel.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP56176803A JPS5878451A (en) | 1981-11-04 | 1981-11-04 | Semiconductor device |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP56176803A JPS5878451A (en) | 1981-11-04 | 1981-11-04 | Semiconductor device |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPS5878451A true JPS5878451A (en) | 1983-05-12 |
Family
ID=16020108
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP56176803A Pending JPS5878451A (en) | 1981-11-04 | 1981-11-04 | Semiconductor device |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPS5878451A (en) |
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US6573582B2 (en) * | 2001-07-23 | 2003-06-03 | Mitsubishi Denki Kabushiki Kaisha | Semiconductor device |
-
1981
- 1981-11-04 JP JP56176803A patent/JPS5878451A/en active Pending
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US6573582B2 (en) * | 2001-07-23 | 2003-06-03 | Mitsubishi Denki Kabushiki Kaisha | Semiconductor device |
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