JPS6068627A - Semiconductor integrated circuit device - Google Patents

Abstract

(57) [Summary] This bulletin contains application data before electronic filing, so abstract data is not recorded.

Description

DETAILED DESCRIPTION OF THE INVENTION Field of the Invention The present invention relates to a semiconductor integrated circuit (hereinafter referred to as LSI), and particularly to the structure of a high-speed LSI.

Conventional Structures and Problems Semiconductor devices are becoming faster and faster. In particular, when bipolar LSIs are used in digital circuits, high speed performance is increasingly required.

Generally, the operating speed of a bipolar transistor circuit is mainly determined by the base time constant τB and the collector time constant τC.

τB is the product of the transistor base resistance rbbl and collector-base junction capacitance CcB, and τC is the load resistance R
It is mainly determined by the product of L and collector-substrate junction capacitance CcB.

The structure of a conventional bipolar NpNl-transistor will be explained below with reference to FIG. In Figure 1a, 1 is a P-type semiconductor substrate, 2 is a heavily doped collector N+ buried layer, 3 is an N- type epitaxial layer, 4 is an isolation insulator, and 6 is a heavily doped collector layer. N ten area,
6 is a P type region, 7 is a heavily doped N0 region, 8 is an insulator, 9 to 11 are electrodes, 9 is a base electrode, 1o
is an emitter electrode, and 11 is a collector electrode.

FIG. 1 is a symbolic representation of the transistor structure shown in FIG.

Here, 008 of 12 is shown in FIG. 1a by joining the 10P type semiconductor substrate and the collector N+ buried layer of 2.
It is something that is formed.

Incidentally, the operating speed of a bipolar transistor is determined by the base time constant and the collector time constant as described above, and reducing the parasitic capacitance is an effective means for increasing the speed. In particular, an element structure such as an SOS in which an element is formed on an insulating substrate has been proposed as a means for reducing the junction capacitance between collector substrates, but this has the problem of high manufacturing costs.

OBJECTS OF THE INVENTION In view of these conventional problems, it is an object of the present invention to provide an LSI suitable for increasing speed without significantly changing the conventional manufacturing method.

Structure of the Invention The present invention provides a high-resistance layer of one conductivity type between a buried collector layer of one conductivity type and a semiconductor substrate of the other conductivity type, thereby reducing the delay due to the collector-substrate junction capacitance of a bipolar transistor to almost zero. and high-speed bipolar L
It is possible to realize SI.

DESCRIPTION OF EMBODIMENTS FIG. 2 shows a bipolar NpN in one embodiment of the present invention.
) The structure of the transistor is shown, and in order to facilitate the explanation, the first
Components common to the figures are numbered the same as in FIG.

In FIG. 2a, 1 is a P-type semiconductor substrate, 13 is an N-
2 is a heavily doped collector N+ buried layer, 3 is an N- type epitaxial layer, 4 is an element isolation insulator, 5 is a heavily doped N+ region 6 is a P type region, 7 is a heavily doped N0 region, 8 is an insulator, 9-
11 is an electrode.

FIG. 2 shows the transistor structure shown in FIG.
This is the collector-substrate junction capacitance C681 formed by the junction between the N-type semiconductor substrate and the thirteen N-type high-resistance layers. Here, in C861, since 13 is the N-high resistance layer, it is smaller than the conventional collector-substrate capacitance Ccs in FIG. In addition, 14 is the resistance due to the 13ON-high resistance layer, and the resistance component from the junction surface of 1 and 13 mentioned above to the interface between 13 and the N+ buried layer of 2 (hereinafter referred to as collector-substrate resistance) r
This indicates as.

In the transistor having the structure of the present invention described above, the delay due to li on the collector-substrate junction capacitance Ct will be explained with reference to FIG. Figure 3a is a switching circuit diagram with 16 constant current transistors and 17 transistors.
Replace the switch with a constant voltage source ■ via the 18 load resistor R1. . It is connected to. Here, 11 is the collector electrode 14, the above-mentioned collector-substrate resistance rcB,
15 is the collector-substrate capacitance C6s/.

FIG. 3 shows the voltage response waveforms of the eleven collector terminals of the circuit of FIG. 3a. The solid line 1 indicates the resistance r between the collector and substrate according to the present invention. This is the response waveform with 6 inserted,
When switch 17 is turned off, the rising waveform of ■1 is ■1r, and when it is turned on, the falling waveform of ■1i is (,) (
2) Ccsl(RL+rCs). That is, in the logic amplitude RL, the voltage at zero changes depending on whether the switch 17 is turned on or off, and is then charged and discharged with a time constant of C, t (RL0rcs). Therefore, the aforementioned collector-substrate resistance "C"
If B is made larger than the load resistance RL, the delay due to the collector-substrate capacitance C68/ will become so small that it can be almost ignored.

In addition, the dotted line v2 in Figure 3 indicates the collector-substrate resistance r
. This is a response waveform when S is set to zero, which is the same as that of the conventional transistor shown in FIG. 1, and shows how it is charged and discharged with a time constant of Cc8·RL, illustrating the effect of the present invention.

In the embodiment of the present invention shown in FIG. 2a, the elements are isolated by the element isolation insulator 4, but it goes without saying that commonly used junction isolation may also be used. It is obvious that the structure of the emitter region can be changed. Furthermore, a PNP transistor using the present invention can also be constructed.

Effects of the Invention As described above, the present invention provides a high resistance layer of one conductivity type, which is larger than the load resistance, between the collector buried layer of one conductivity type and the semiconductor substrate of the other conductivity type, thereby reducing the delay due to the junction capacitance between the collector substrates. Accordingly, it is possible to realize an excellent semiconductor integrated circuit device that can achieve the effect of eliminating the noise and increasing the speed.

[Brief explanation of the drawing]

Figures 1a and 1b are a structural diagram and an equivalent circuit diagram of a conventional bipolar NpN transistor, respectively, and Figure 2a is a diagram. b are each bipolar NpN according to an embodiment of the invention.
A structural diagram of a transistor, an equivalent circuit diagram, and FIGS. 3a and 3b are a switching circuit diagram and a response waveform diagram, respectively, for explaining the present invention. 1... P-type semiconductor substrate, 2... Highly doped collector N-buried layer, 13... N- type high resistance layer, 18... Load resistance. Name of agent: Patent attorney Toshio Nakao and 1 other person @1
Figure 2

Claims (1)

[Claims] Between the highly doped collector buried layer of one conductivity type and the semiconductor substrate of the other conductivity type, a resistance up to the junction surface between the high resistance layer of one conductivity type and the semiconductor substrate of the other conductivity type is connected to the collector. A semiconductor integrated circuit device characterized by high resistance.