JPS5878497A - Multilayer printed circuit board - Google Patents

Multilayer printed circuit board

Info

Publication number
JPS5878497A
JPS5878497A JP17677481A JP17677481A JPS5878497A JP S5878497 A JPS5878497 A JP S5878497A JP 17677481 A JP17677481 A JP 17677481A JP 17677481 A JP17677481 A JP 17677481A JP S5878497 A JPS5878497 A JP S5878497A
Authority
JP
Japan
Prior art keywords
layer
clearance
signal
multilayer printed
signal wiring
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
JP17677481A
Other languages
Japanese (ja)
Other versions
JPS643354B2 (en
Inventor
大前 憲一
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
NEC Corp
Original Assignee
Nippon Electric Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Nippon Electric Co Ltd filed Critical Nippon Electric Co Ltd
Priority to JP17677481A priority Critical patent/JPS5878497A/en
Publication of JPS5878497A publication Critical patent/JPS5878497A/en
Publication of JPS643354B2 publication Critical patent/JPS643354B2/ja
Granted legal-status Critical Current

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  • Production Of Multi-Layered Print Wiring Board (AREA)

Abstract

(57)【要約】本公報は電子出願前の出願データであるた
め要約のデータは記録されません。
(57) [Summary] This bulletin contains application data before electronic filing, so abstract data is not recorded.

Description

【発明の詳細な説明】 本発明は電子部品の実装およq#i!、線等に使用され
る少なくとも2層以上の導体層から構成された多層プリ
ント配線基板に関するものである。
DETAILED DESCRIPTION OF THE INVENTION The present invention relates to electronic component mounting and q#i! The present invention relates to a multilayer printed wiring board composed of at least two or more conductor layers used for wires and the like.

夕な(とも2層以上の導体層で―成された多層プリン)
配線基板の1例をjlllll(1、(1に示す。
Yuna (also known as multilayer pudding made of two or more conductor layers)
An example of the wiring board is shown in (1, (1).

絶縁体1の片側に帯状にのびたan層2償漫l!1が設
置され、絶縁体1の他方の片側の両区電源層またはグラ
ンド層3が形成され【いる。とのようなプリント配線基
板で**インピーダンスを変えるには信号配線の幅、間
隔あるいは絶縁体1の厚みなどを変えなければならない
、どの不便な震決す^り、I!来、多層プリント配線基
板に8いて、七〇゛層間の厚さ、材質、信号線の幅1間
隔などの賭条伸を変えずに、その豐性イシビーダンスを
変化S−るものとして、1m2図(1,QIJで層重よ
うに信号層2と肉かいあうグランド層または電源層3に
、信号配線に対応量るよう円形状に導体部分をくり抜い
たものが知られている。この導体をくり抜いた部分をク
リアランス4と称しているが、従来のプリント配線基板
では上述の−(円形状のり讐アツンスであるため、嬉5
IIK示すとおり、信号配線2(υ、3(2)、−2−
とクリアランス4の位置関係によ4てそれぞれの重なる
画一がか謙り異Ik−pているため、信号配線の特性イ
ンに’ −/ )/ Xに大きなげ一つきが生じ、加え
て、信号配線とりψアラyス4の位置のずれにようても
1舟配線の畳倫イyビーダンスは変化するととになる。
An an layer 2 extending in a band shape on one side of the insulator 1! 1 is installed, and both power supply layers or ground layers 3 on the other side of the insulator 1 are formed. To change the impedance on a printed wiring board such as **, you have to change the width and spacing of the signal wiring or the thickness of the insulator 1, which is an inconvenient decision.I! Now, assuming that a multilayer printed wiring board is used, and its characteristic Ishibi dance is changed without changing the thickness, material, signal line width, etc. between 70 layers, the 1m2 figure is (1. It is known that in QIJ, a circular conductor part is cut out to correspond to the signal wiring in the ground layer or power supply layer 3 that is in contact with the signal layer 2 like a layered layer. This area is called clearance 4, but in conventional printed wiring boards, it is the circular clearance mentioned above.
As shown in IIK, signal wiring 2 (υ, 3(2), -2-
Due to the positional relationship between the clearance 4 and the clearance 4, the uniformity of each overlap is slightly different Ik-p, so there is a large difference in the characteristic of the signal wiring '-/)/X, and in addition, Even if the position of the signal wiring line ψ array 4 is shifted, the tatami line resistance of the single wiring line changes.

また。Also.

114■に示すよ5に、円形状のクリアランス4を複数
個組みあわせて各信号配線2 (1)、2 (2) −
2(2)の特性インピーダンスのばらつきを小さくしよ
うとしても、前記信号配線とクリアランス4の位置ずれ
による4I性インピーダンスの変“化&1改曽すること
はできない。
As shown in 114■, each signal wiring 2 (1), 2 (2) - is made by combining multiple circular clearances 4 at 5.
Even if an attempt is made to reduce the variation in the characteristic impedance of 2(2), it is not possible to change the 4I impedance due to the positional deviation between the signal wiring and the clearance 4.

本発明の目的は、グランド層またも1電源層のクリアラ
ンスを多角形にすることにより前記欠点な解決し、すべ
【の信号配線の特性インピーダンスのはもつきを小さク
シ、かつ、クリアランスと信号配線のずれによる特性イ
ンピーダンスの変化をなくした多層プリンシ配線基板を
提供するととに島る。
It is an object of the present invention to solve the above-mentioned drawbacks by making the clearance of the ground layer or one power layer polygonal, to reduce the characteristic impedance of all signal wiring, and to reduce the increase in the characteristic impedance of all signal wiring. It is our goal to provide a multilayer printed wiring board that eliminates changes in characteristic impedance due to misalignment.

本発明は、少1kくとも1層以上の導体層から構成され
かつ信号層とグランド層又−1信号層と電1層が隣りあ
りている多層プリンシ配線基板にS%I%も前記領置層
内の信号配線と対向する前記グランド層又は′@源層内
の位置に、多角形状のクリアランスを規則的に設けたも
のである。
The present invention provides a multilayer printed wiring board that is composed of at least one conductor layer and in which a signal layer and a ground layer or a -1 signal layer and a conductor layer are adjacent to each other. Polygonal clearances are regularly provided at positions within the ground layer or source layer that face the signal wiring within the layer.

次に1本発@wt、 ml−を参照して、実施例につき
詳秦帆ll!―する。
Next, please refer to @wt, ml- for details on the examples! -do.

第5図〜第10図は本発明の各1の実施例を模謄的に示
したものでありて%符号Sはグ13/)板上に設けられ
た格子であり、との格子にようてプlj)/)基板は、
同じ面積なもつ正方形の部分に分−される、2は信号層
内における信号配線である。
5 to 10 schematically show each embodiment of the present invention, and the % symbol S represents a lattice provided on a board, and the lattice shown in FIG. The board is
2 is a signal wiring in the signal layer, which is divided into square parts having the same area.

図中の斜線部分4はグランド層および111LIIII
J1に設けられた長方形ないし正方形のクリアランスを
示し、前記格子内すべてに設けられる。
The shaded area 4 in the figure is the ground layer and 111LIII
It shows a rectangular or square clearance provided in J1, provided throughout the grid.

第Sa!llは本発明の亀1の実施例である。クリアラ
ンスを長方形にし、信号配線5とクリアランス4の重な
る面積を一定にすることによりて、各信号配線2(支)
、2@、−1(2)の特性インピーダンスのばらつきを
小さくし、かつ信号配線とり讐アラyス4の位置ずれに
よる特性インピーダンスの変化をなくすように構威しで
ある。mailはlI2の実施例で、長方形のクリアラ
ンス4を図示のように楊子上へ設けたもので、効果は第
1の実施例の鳩舎帆加えて、1s6■の符量・のようK
Is子内で成る備4#配線意−が−がうて走る場舎でも
、4)償漫起纏20譬愉インビー〆ンスのは&)*は小
さい。第711はwi3の実施例で、クリプラン 。
Chapter Sa! ll is an embodiment of turtle 1 of the present invention. By making the clearance rectangular and making the overlapping area of the signal wiring 5 and clearance 4 constant, each signal wiring 2 (support)
, 2@, -1(2), and eliminates changes in the characteristic impedance due to positional deviation of the signal wiring array 4. The mail is an example of lI2, and a rectangular clearance 4 is provided on the toothpick as shown in the figure, and the effect is that of the pigeon house sail of the first example, and the code size of 1s6■.
Even in a place where the preparation 4 # wiring intention - which is formed within the Is child runs -, the 4) redemption of 20 parables is small. The 711th is an example of wi3, and is a Crypran.

正方形にすることによ一5″C1縦、横両方−の信号配
線2の特性インピーダンスの&fらつきを小さくし、か
つ%信4!配線2とクリアランス4の位置ずれに対して
も4I性インビ一メンス 第8図は、第一〇実施例で、クリ 長方形にし、かつ格子上の四辺にすべてに設けるもので
、この効果は、縦、横真方向の各信号配線2に対して特
性インビーダン  。
By making it square, it is possible to reduce fluctuations in the characteristic impedance of the signal wiring 2 in both the vertical and horizontal directions, and also to reduce the 4I impedance against misalignment between the wiring 2 and the clearance 4. Figure 8 shows the 10th embodiment, which is made into a rectangular shape and provided on all four sides of the grid, and this effect has a characteristic impedance for each signal wiring 2 in the vertical and horizontal directions.

く、かつ信号層とクリアランス4の位置ずれに対して*
*インビーダ/スの変化が亀−1のに加え、格子内で信
号配線が曲がうても特性インピーダンスのばらつきは小
さくできるという効果がある。
and against misalignment between the signal layer and clearance 4*
*In addition to the change in impedance, the variation in characteristic impedance can be reduced even if the signal wiring is bent within the lattice.

第9図は第Sの実施例で、長方形のクリアランス4を斜
めに設けたものである。効果は籐7116籐3の実施例
の鳩舎と同じで、それに加え【導体層の部分を多くとる
ことが!き、グツンドドーf1や電源電圧ドーツイを小
さくすることができる。
FIG. 9 shows an S-th embodiment, in which a rectangular clearance 4 is provided diagonally. The effect is the same as the rattan 7116 rattan 3 example pigeon coop, and in addition [more conductive layer parts can be taken! Therefore, it is possible to reduce the power supply voltage f1 and the power supply voltage difference.

j11G111第・の実施−で、j1方形のクリアラン
ス4を信号配線2と格子の交わる部分に設けたもので、
第8図の17h4の実施例の効果に加えて、導体層の部
分な多くとることができ、グランド°ドロップや電ll
Al1に圧ドーツプを小さくすること力1できる。
In the j11G111th implementation, j1 rectangular clearance 4 is provided at the intersection of the signal wiring 2 and the grid,
In addition to the effects of the embodiment 17h4 in Fig. 8, a large portion of the conductor layer can be used to reduce ground drop and electric current.
It is possible to reduce the pressure dope in Al1 by a force of 1.

本発明は以上Wm明したように、クリアランスを多角形
状にするととによりてJ信号配線の特性インピーダンス
のばらつきを小さクシ、力・つ信号配線とクリアランス
の位置ずれによる特性インピーダンスの変化な傘くすと
いう効果がある。
As explained above, the present invention reduces variations in the characteristic impedance of the J signal wiring by making the clearance polygonal, and prevents changes in characteristic impedance due to positional deviation between the force/signal wiring and the clearance. effective.

【図面の簡単な説明】[Brief explanation of the drawing]

第1a1(姉、(至)は少なくとも2層以上の導体層で
構成されている従来のプリント基板の斜視図、mzli
(〜、(2)は、クリアランスを有する鳩舎の従来のプ
リント基板の斜man%籐3−および第411従来の円
形クリアランスをもつプリン)基板の信号層偶からみた
透視−、$15園な−し第10114i本弗明の多層プ
リン)配線基板の各撫実施例を示し麩透manである。 l−飴縁体、  2−(1号層の信号配線。 s−tg層(グランド層)、 4・・・クリアランス、  5−格子。 代理人  弁理士  東 川 利 吉 第1図(a) 第1図(b) 第2図(a) 第2図(b) 第3図 第4図 第5図 第6図 第7図 第8図 2 しyJ 第9図
1a1 (older sister, (to)) is a perspective view of a conventional printed circuit board composed of at least two or more conductor layers, mzli
(~, (2) is the diagonal man% rattan 3- of the conventional printed circuit board of the pigeon house with clearance and the 411th conventional printed circuit board with circular clearance) Perspective from the signal layer of the board-, $15 garden- The 10114th edition of this book (multilayer print) shows examples of each of the wiring boards. l-candy body, 2-(Signal wiring of layer 1. S-TG layer (ground layer), 4... Clearance, 5- Lattice. Agent Patent attorney Rikichi Higashikawa Figure 1 (a) Figure 1 (b) Figure 2 (a) Figure 2 (b) Figure 3 Figure 4 Figure 5 Figure 6 Figure 7 Figure 8 Figure 2 ShiyJ Figure 9

Claims (1)

【特許請求の範囲】[Claims] 少くとも2層以上の導体層から構成されかつ信号層とグ
ランド層又は信号層と電源層が隣りあうている多層プリ
ント配線基−に寞いて、前記備考層内の信号配線と対向
する前記グランド層内または電源層内の位置に、多角形
状に導体をくり抜いたクリアランス部分を11L−釣に
設けたことを特徴とする多層プリント配線基板。
In a multilayer printed wiring board that is composed of at least two or more conductor layers and in which a signal layer and a ground layer or a signal layer and a power supply layer are adjacent to each other, the ground layer faces the signal wiring in the above-mentioned layer. 1. A multilayer printed wiring board characterized in that a clearance portion in which a conductor is hollowed out in a polygonal shape is provided at a position inside or within a power supply layer.
JP17677481A 1981-11-04 1981-11-04 Multilayer printed circuit board Granted JPS5878497A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP17677481A JPS5878497A (en) 1981-11-04 1981-11-04 Multilayer printed circuit board

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP17677481A JPS5878497A (en) 1981-11-04 1981-11-04 Multilayer printed circuit board

Publications (2)

Publication Number Publication Date
JPS5878497A true JPS5878497A (en) 1983-05-12
JPS643354B2 JPS643354B2 (en) 1989-01-20

Family

ID=16019588

Family Applications (1)

Application Number Title Priority Date Filing Date
JP17677481A Granted JPS5878497A (en) 1981-11-04 1981-11-04 Multilayer printed circuit board

Country Status (1)

Country Link
JP (1) JPS5878497A (en)

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS6047496A (en) * 1983-08-26 1985-03-14 日立化成工業株式会社 Ceramic board
JPH0529772A (en) * 1991-07-19 1993-02-05 Oki Electric Ind Co Ltd Circuit substrate for high-speed signal transmission

Citations (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS5098666A (en) * 1973-12-29 1975-08-05
JPS5172160U (en) * 1974-12-03 1976-06-07

Patent Citations (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS5098666A (en) * 1973-12-29 1975-08-05
JPS5172160U (en) * 1974-12-03 1976-06-07

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS6047496A (en) * 1983-08-26 1985-03-14 日立化成工業株式会社 Ceramic board
JPH0529772A (en) * 1991-07-19 1993-02-05 Oki Electric Ind Co Ltd Circuit substrate for high-speed signal transmission

Also Published As

Publication number Publication date
JPS643354B2 (en) 1989-01-20

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