JPS5882321A - Generating circuit for absolute temperature proportional current - Google Patents
Generating circuit for absolute temperature proportional currentInfo
- Publication number
- JPS5882321A JPS5882321A JP56180597A JP18059781A JPS5882321A JP S5882321 A JPS5882321 A JP S5882321A JP 56180597 A JP56180597 A JP 56180597A JP 18059781 A JP18059781 A JP 18059781A JP S5882321 A JPS5882321 A JP S5882321A
- Authority
- JP
- Japan
- Prior art keywords
- transistor
- collector
- emitter
- circuit
- transistors
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Granted
Links
Classifications
-
- G—PHYSICS
- G05—CONTROLLING; REGULATING
- G05F—SYSTEMS FOR REGULATING ELECTRIC OR MAGNETIC VARIABLES
- G05F3/00—Non-retroactive systems for regulating electric variables by using an uncontrolled element, or an uncontrolled combination of elements, such element or such combination having self-regulating properties
- G05F3/02—Regulating voltage or current
- G05F3/08—Regulating voltage or current wherein the variable is DC
- G05F3/10—Regulating voltage or current wherein the variable is DC using uncontrolled devices with non-linear characteristics
- G05F3/16—Regulating voltage or current wherein the variable is DC using uncontrolled devices with non-linear characteristics being semiconductor devices
- G05F3/20—Regulating voltage or current wherein the variable is DC using uncontrolled devices with non-linear characteristics being semiconductor devices using diode- transistor combinations
- G05F3/26—Current mirrors
Landscapes
- Engineering & Computer Science (AREA)
- Physics & Mathematics (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Nonlinear Science (AREA)
- Electromagnetism (AREA)
- General Physics & Mathematics (AREA)
- Radar, Positioning & Navigation (AREA)
- Automation & Control Theory (AREA)
- Amplifiers (AREA)
- Control Of Electrical Variables (AREA)
Abstract
Description
【発明の詳細な説明】
この発明は半導体素子の電流がその絶対Y晶糺に依存す
る現象を利用した絶対温度比例電流発生回路に関するも
ので夕)る。DETAILED DESCRIPTION OF THE INVENTION The present invention relates to an absolute temperature proportional current generation circuit that utilizes the phenomenon that the current of a semiconductor element depends on its absolute Y crystal strength.
第1図は従来のこの柚の回路を示す接続図で図において
Ql 、Q2.Q3.Q5.Q6 はそれぞれ塔・l
、第2゜第3.第5.オ6の各トランジスタ、IJli
jダイオード、R1,R2,R3,R4はそれぞれ抵抗
、Vccは直流電源、GNDは接地を示す。図に示すと
おりトランジスタQl、Q3.Q6 U第1の極性の
トランジスタで、トランジスタQ2 、Qsは第2の特
性のトランジスタである。また抵抗R1,トランジスタ
Ql、Q2. 抵抗R2の回路を仮にオlの回路と称
し、トランジスタQ5 、抵抗R4の回路全第3の回路
という。トランジスタQl 、Qs、Qsのベースは並
列に接続され仮にこれをオlの共通ペース回路という。FIG. 1 is a connection diagram showing a conventional circuit of this type. In the figure, Ql, Q2. Q3. Q5. Q6 is tower/l respectively
, 2nd degree, 3rd degree. Fifth. Each transistor of O6, IJli
j diode, R1, R2, R3, and R4 are resistors, Vcc is a DC power supply, and GND is ground. As shown in the figure, transistors Ql, Q3. Q6U is a transistor with a first polarity, and transistors Q2 and Qs are transistors with a second characteristic. Also, resistor R1, transistor Ql, Q2 . The circuit including the resistor R2 is tentatively referred to as the first circuit, and the circuit including the transistor Q5 and the resistor R4 is collectively referred to as a third circuit. The bases of transistors Ql, Qs, and Qs are connected in parallel, and this is called a common pace circuit.
ダイオードDIのアノードはトランジスタQ2のベース
に接続される。The anode of diode DI is connected to the base of transistor Q2.
この回路に直流電源Vccを接続すると、■Cc→R3
→Q3のベース→Q5のベース→R4→GNDの電流が
流れてQsはオンとなり、Vcc −+ Qsのコレク
タ→Q5のベース→Q3のベース→Q3のコレクタ→D
1→GNDの電流が流れてQsがオンとなりQ2のベー
ス→R2の電流が流れてQ2がオンとなりQ6 のベー
スに電流が流れてQ6がオンとなり、Ql がオンと
なる。この状態で、トランジスタQ2とダイオードDi
とにカレントミラーを構成する。When a DC power supply Vcc is connected to this circuit, ■Cc→R3
→ Base of Q3 → Base of Q5 → R4 → GND current flows and Qs turns on, Vcc −+ Collector of Qs → Base of Q5 → Base of Q3 → Collector of Q3 → D
1→GND current flows, Qs turns on, the base of Q2→R2 current flows, Q2 turns on, current flows to the base of Q6, Q6 turns on, and Ql turns on. In this state, transistor Q2 and diode Di
Configure a current mirror.
トランジスタQ3 のコレクタ電流kIとし、そのコレ
クタ重信をVc 、エミッタ甫1位をVE 、ダイオー
ドDiのアノード電位k VFとすれば、Vc = V
cc−R3I、Vg = VrからVc −VE: V
c c ((3I −Vp、・、 tt+の関係で電流
■が定まる。VFはDiがQ2とカレントミラーを構成
している関係でほぼ一定に保たれるが、Vccが変動す
ると式(1)の関係に従ってVc Vgが変動する。Let the collector current of the transistor Q3 be kI, its collector current be Vc, the emitter voltage 1 be VE, and the anode potential of the diode Di be kVF, then Vc = V
cc-R3I, Vg = Vr to Vc-VE: V
c c ((3I - Vp, ., Current ■ is determined by the relationship tt+. VF is kept almost constant because Di forms a current mirror with Q2, but when Vcc changes, Equation (1) Vc Vg varies according to the relationship.
一般的に知られているトランジスタのアーリー効果(E
arly effect ) により、トランジスタ
の(Vc−VE)が変化するとコレクタ市、流も変化す
る。The generally known early effect (E) of transistors
Due to early effect), when the (Vc-VE) of the transistor changes, the collector voltage and current also change.
すなわち、電流IはトランジスタQ3の絶対温度だけで
な(Vccの変動によっても変動するため、安定した電
流が得られ力いという欠点があった。That is, since the current I varies not only due to the absolute temperature of the transistor Q3 but also due to variations in Vcc, there is a drawback that it is difficult to obtain a stable current.
この発明は従来の回路における上述の欠点を除去するた
めになされたもので、′電流発生の基準となるトランジ
スタのV(! VEが電源電圧の変動により影舎されな
いような回路を提供することを目的としている。This invention was made in order to eliminate the above-mentioned drawbacks in conventional circuits, and aims to provide a circuit in which V(!VE) of a transistor, which is a reference for current generation, is not affected by fluctuations in power supply voltage. The purpose is
以下図面によりこの発明の詳細な説明する。The present invention will be explained in detail below with reference to the drawings.
第2図はこの発明の一実施例を示すブロック図で、第1
図と同一符号は同−又は相当部分を示し同様に動作する
。Q4は第2の極性の第4のトランジスタ、Qlはオl
の極性のオフのトランジスタである。FIG. 2 is a block diagram showing one embodiment of the present invention.
The same reference numerals as in the figures indicate the same or corresponding parts and operate in the same way. Q4 is the fourth transistor of the second polarity, Ql is the
It is an off transistor with a polarity of .
トランジスタQ4のコレクタはトランジスタQ3のコレ
クタと接続されそのエミッタは接地と接続される。抵抗
R3、トランジスタQ3.Q4の回路を仮に第2の回路
と称し、Q4のベースとQ2のベースは接続されて第2
の共通ベース回路を構成し、トランジスタQ7のベース
はトランジスタQ5のエミッタに接続され、そのエミッ
タはトランジスタQ3のコレクタに、そのコレクタは第
2の共通ベース回路にそれぞれ接続される。トランジス
タQl。The collector of transistor Q4 is connected to the collector of transistor Q3, and its emitter is connected to ground. Resistor R3, transistor Q3. The circuit of Q4 is temporarily called the second circuit, and the base of Q4 and the base of Q2 are connected to form the second circuit.
The base of transistor Q7 is connected to the emitter of transistor Q5, the emitter is connected to the collector of transistor Q3, and the collector is connected to a second common base circuit. Transistor Ql.
Q6(!:I−ランジスタQ3 とはカレントミラー
を構成し、かつトランジスタQ2とトランジスタQ4
rQ7とはカレントミラーを構成する。Q”+Q4vC
よって構成される第3の回路が起動回路として動作する
ことは第1図の場合と同様である。Q6 (!:I- The transistor Q3 constitutes a current mirror, and the transistor Q2 and the transistor Q4
rQ7 constitutes a current mirror. Q”+Q4vC
The third circuit constructed in this way operates as a starting circuit in the same way as in the case of FIG. 1.
Qsのコレクタ電位をVc 、そのエミッタ電位會VE
とし、Qs、Qs、Qlのペースエミッタ間電圧をそれ
ぞれVBE(Qs)I VBE(Qli) l VB
g(Ql) トすればV、−vBE(q7) −”E
”BE(Qs)−vBE(Qs)であるがvB[Q
s)=vBE(Qs)”vBE(Li2) ””Cア
ル(D”’CVc−VEキーVBg(qs)−t21と
々すVc−VEの値がVccに依存せず常に−VBE(
Qs) (”IIE(Qs)又は−■B06,7、と
同じ)で動作し、したがって電流■はトランジスタQ3
の温度だけによって定まることになる。The collector potential of Qs is Vc, and its emitter potential VE
The pace emitter voltages of Qs, Qs, and Ql are respectively VBE(Qs)I VBE(Qli)l VB
g(Ql) then V, -vBE(q7) -”E
``BE(Qs) - vBE(Qs) but vB[Q
s)=vBE(Qs)"vBE(Li2)""CAl(D"'CVc-VE key VBg(qs)-t21 The value of Vc-VE does not depend on Vcc and is always -VBE(
Qs) (same as "IIE(Qs) or -■B06,7,"), so the current ■ is the same as transistor Q3
It is determined only by the temperature of
また、第2図の回路は第1図の回路に比し実質的に増加
する素子はQlだけであり、かつトランジスタQ7は通
常のPN接合素子であるため集積回路化し易いという利
点がある。Further, the circuit of FIG. 2 has the advantage that Ql is the only element that is substantially increased compared to the circuit of FIG. 1, and since the transistor Q7 is a normal PN junction element, it can be easily integrated into an integrated circuit.
また、第2図においてR1、R3を短絡した場合も同様
に動作する。Further, the same operation occurs when R1 and R3 are short-circuited in FIG. 2.
第1図は従来の回路を示す接続図、第2図tまこの発明
の一実施例を示す接続図である。
Ql・・・オlのトランジスタ、Q2・・・第2のトラ
ンジスタ、Qs・・・第3のトランジスタ、Q4・・・
第4のトランジスタ、Qs・・・第5のトランジスタ、
Q6・・・オ6のトランジスタ、Ql・・・オフのトラ
ンジスタ。
なお、図中同一符号は同−又は相当部分を示す。
代理人 葛 野 侶 −
(7)
第1図FIG. 1 is a connection diagram showing a conventional circuit, and FIG. 2 is a connection diagram showing an embodiment of the present invention. Ql...Ol transistor, Q2...second transistor, Qs...third transistor, Q4...
Fourth transistor, Qs...fifth transistor,
Q6...O6 transistor, Ql...Off transistor. Note that the same reference numerals in the figures indicate the same or equivalent parts. Agent Tsutomu Kuzuno - (7) Figure 1
Claims (1)
性の第2のトランジスタのコレクタに接続し上記オlの
トランジスタのエミッタは抵抗を介して直流電源に上記
第2のトランジスタのエミッタは抵抗を介して接地にそ
れぞれ接続して構成したオlの回路と、上記第1の極性
の第3のトランジスタのコレクタを上記第2の極性の第
4のトランジスタのコレクタに接続し上記第3のトラン
ジスタのエミッタは抵抗を介して上記直流電源に上記第
4のトランジスタのエミッタは接地にそれぞれ接続して
構成した第2の回路と、上記第2の極性の第5のトラン
ジスタのコレクタを上記直流電源にそのエミッタ全抵抗
ケ介して接地にそれぞれ接続して構成した第30回路と
、上記オl、第3、及び第5の各トランジスタのベース
を並列に接続するオlの共通ベース回路と、上記第2及
び第4のトランジスタのベースを接続する第2の共通ベ
ース回路と、上記刈・lの極性を有しそのエミッタは上
記′171の共通ベース回路にそのコレクタは接地にそ
のベースは上記第2のトランジスタのコレクタにそれぞ
れ接続されるオ6のトランジスタと、上記オlの極性を
准しそのエミッタは上記第3のトランジスタのコレクタ
にそのコレクタは上記第2の共通ベース回路にそのベー
スは上記第5のトランジスタのエミッタにそれぞれ接続
されるオフのトランジスタとを備えた絶対71 tJJ
j比例電流発生回路。The collector of the transistor with the opposite polarity is connected to the collector of the second transistor with the second polarity, and the emitter of the transistor with the polarity is connected to the DC power supply via the resistor. the collector of the third transistor of the first polarity is connected to the collector of the fourth transistor of the second polarity, and the third transistor a second circuit configured by connecting the emitter of the fourth transistor to the DC power supply via a resistor and grounding the emitter of the fourth transistor, and connecting the collector of the fifth transistor of the second polarity to the DC power supply; A 30th circuit configured by connecting the emitters to the ground through all the resistors, an 30th common base circuit in which the bases of the 1st, 3rd, and 5th transistors are connected in parallel; a second common base circuit connecting the bases of the second and fourth transistors, and having the polarity of the above-mentioned transistors, its emitter is connected to the common base circuit of the above-mentioned '171, its collector is grounded, and its base is connected to the above-mentioned second common base circuit; 6 transistors are connected to the collectors of the transistors of 6 and 6, respectively, and their emitters are connected to the collectors of the third transistors, their collectors are connected to the second common base circuit, and their bases are connected to the second common base circuit, and their emitters are connected to the collectors of the third transistors. Absolute 71 tJJ with off transistors connected to the emitters of the 5 transistors, respectively.
jProportional current generation circuit.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP56180597A JPS5882321A (en) | 1981-11-10 | 1981-11-10 | Generating circuit for absolute temperature proportional current |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP56180597A JPS5882321A (en) | 1981-11-10 | 1981-11-10 | Generating circuit for absolute temperature proportional current |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| JPS5882321A true JPS5882321A (en) | 1983-05-17 |
| JPH0259485B2 JPH0259485B2 (en) | 1990-12-12 |
Family
ID=16086038
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP56180597A Granted JPS5882321A (en) | 1981-11-10 | 1981-11-10 | Generating circuit for absolute temperature proportional current |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPS5882321A (en) |
Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US4578633A (en) * | 1983-08-31 | 1986-03-25 | Kabushiki Kaisha Toshiba | Constant current source circuit |
| JP5942175B1 (en) * | 2015-02-27 | 2016-06-29 | Simplex Quantum株式会社 | Current source circuit |
-
1981
- 1981-11-10 JP JP56180597A patent/JPS5882321A/en active Granted
Cited By (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US4578633A (en) * | 1983-08-31 | 1986-03-25 | Kabushiki Kaisha Toshiba | Constant current source circuit |
| JP5942175B1 (en) * | 2015-02-27 | 2016-06-29 | Simplex Quantum株式会社 | Current source circuit |
| WO2016136948A1 (en) * | 2015-02-27 | 2016-09-01 | Simplex Quantum株式会社 | Current source circuit |
Also Published As
| Publication number | Publication date |
|---|---|
| JPH0259485B2 (en) | 1990-12-12 |
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