JPS5882570A - Semiconductor device - Google Patents
Semiconductor deviceInfo
- Publication number
- JPS5882570A JPS5882570A JP56180478A JP18047881A JPS5882570A JP S5882570 A JPS5882570 A JP S5882570A JP 56180478 A JP56180478 A JP 56180478A JP 18047881 A JP18047881 A JP 18047881A JP S5882570 A JPS5882570 A JP S5882570A
- Authority
- JP
- Japan
- Prior art keywords
- layer
- group compound
- compound semiconductor
- semiconductor
- semiconductor device
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
Classifications
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
- H10D64/00—Electrodes of devices having potential barriers
- H10D64/60—Electrodes characterised by their materials
- H10D64/602—Heterojunction gate electrodes for FETs
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
- H10D30/00—Field-effect transistors [FET]
- H10D30/80—FETs having rectifying junction gate electrodes
- H10D30/801—FETs having heterojunction gate electrodes
Abstract
Description
【発明の詳細な説明】
本発明は、低温に於て半導体基板の主面上に絶縁層が形
成されて構成を有する、低温に於て機能する半導体装置
に関する。DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a semiconductor device that functions at low temperatures and has a structure in which an insulating layer is formed on the main surface of a semiconductor substrate at low temperatures.
M種半導体装置としてm−■族化合物半導体基板を用い
たMISIJ電界効果トランジスタかあるが、斯るMI
8型電界効果トランジスタに化法、熱醸化法、熱窒化法
により、形成されてなる絶縁層でなるものが提案されて
いる。然し乍ら斯る方法によって形成された絶縁膜の場
合、それが■−■族化合物半導体基板との間で表面準位
の少ない界面を形成せるものとして良好に形成されてい
るも、熱安定性が悪かったり、縮装の比較的大なる厚さ
を有するものとして形成されなかったりする欠点を有し
ていた。There is a MISIJ field effect transistor using an m-■ group compound semiconductor substrate as an M type semiconductor device;
An 8-type field effect transistor comprising an insulating layer formed by a chemical conversion method, a thermal fermentation method, or a thermal nitridation method has been proposed. However, in the case of an insulating film formed by such a method, although it is well formed to form an interface with few surface states with the ■-■ group compound semiconductor substrate, it has poor thermal stability. However, it has the disadvantage that it cannot be formed with a relatively large thickness.
又従来、MlS型電界効果トランジスタに於て、そのゲ
ート絶縁膜として作用する絶縁層が、真空蒸着法、スパ
ッタリング法に形成されてなる絶縁層でなるものも提案
されている。然し乍ら斯る方法によって形成された絶縁
膜の場合、それが熱的に安定なものともて形成されるも
、m−v族化合iy4半導体基板とは異なる材料でなる
為、nt−v族化合物半導体基板との間で表面準位密度
の少ない界面を形成せるものとして形成され離いという
欠点を有していた。Conventionally, it has been proposed that the insulating layer serving as the gate insulating film of the MlS type field effect transistor is formed by vacuum evaporation or sputtering. However, in the case of an insulating film formed by such a method, although it is thermally stable, it is made of a material different from that of the m-v group compound IY4 semiconductor substrate. It has the disadvantage that it is formed to form an interface with a low surface state density between the substrate and the substrate, and is separated from the substrate.
依って本発明は上述せる欠点のない新“規な斯種半導体
装置を提案せんとするもので、以下詳述する所より明ら
かとなるであろう。Therefore, the present invention aims to propose a new type of semiconductor device free from the above-mentioned drawbacks, which will become clear from the detailed description below.
wJ1図は本発明による半導体装置の第1の実施例を示
し、半絶縁性半導体基板本体1上にN形半導体712が
形成されてなる構成の■−■族化合物半導体でなる半導
体基板6を有し、その半導体基板3の主i14上にソー
ス電極5及びドレイン電極6がオーミックに附され、又
土面4上にソース電極5及びドレイン電極6間に於て、
低温に於て絶縁性を呈する、深い単位を形成するF・、
Cr10等の不純物の添加されてなるm−■族化合物半
導体でなる層7を介してゲート電極8が配されてなる、
MIa型電界効果トランジスタ構成を有する。この場合
、半導体層2が単結晶InP又は単結晶GaAg でな
り、又層7が、半導体層2がInPでなる場合、単結晶
InP又はそれと格子定数が略々勢しい例えばI nA
gAs P系の1ll−v族化合物半導体でなり、又半
導体層2がGaAs でなる場合単結晶GaAs
又はそれと格子定数か略々等しい例えばG1A/AsP
系のm−■族化合物半導体でなる。Figure wJ1 shows a first embodiment of a semiconductor device according to the present invention, which has a semiconductor substrate 6 made of a ■-■ group compound semiconductor having a structure in which an N-type semiconductor 712 is formed on a semi-insulating semiconductor substrate body 1. A source electrode 5 and a drain electrode 6 are ohmically attached to the main i14 of the semiconductor substrate 3, and between the source electrode 5 and the drain electrode 6 on the soil surface 4,
F. forms a deep unit that exhibits insulating properties at low temperatures.
A gate electrode 8 is arranged through a layer 7 made of an m-■ group compound semiconductor doped with impurities such as Cr10,
It has an MIa type field effect transistor configuration. In this case, the semiconductor layer 2 is made of single-crystal InP or single-crystal GaAg, and when the semiconductor layer 2 is made of InP, the layer 7 is made of single-crystal InP or a material having a substantially stronger lattice constant, such as InA.
gAs P-based 1ll-v group compound semiconductor, and when the semiconductor layer 2 is made of GaAs, single crystal GaAs
Or the lattice constant is approximately equal to that, for example, G1A/AsP
It is made of an m-■ group compound semiconductor.
以上が本発明による半導体装置の第1の実施例であるが
、斯る構成によれば、その層7が低温(液体窒素温度)
に於て高い絶縁性を呈することにより低温に於て作用す
るものであるが、この場合層7が深い準位を形成する不
純物でなる川−■族化合物半導体であるので、冒頭にて
前述せる欠点を有しないものである。The above is the first embodiment of the semiconductor device according to the present invention. According to such a structure, the layer 7 is kept at a low temperature (liquid nitrogen temperature).
It works at low temperatures by exhibiting high insulating properties, but in this case the layer 7 is a Kawa-II group compound semiconductor made of impurities that form a deep level, so as mentioned at the beginning It has no drawbacks.
次に第2図及び第S図を伴なって本発明による半導体装
置の#I2の実施例を述べるに、第2図は例えば半絶縁
性半導体基板21上に、半導体層22が形成され、その
半導体層22上及び基板21の半導体層22@とは反対
側に電極25及び24が夫々オーミックに附されてなる
MI8ダイオード構成を有し、又第5図はInAsでな
る半絶縁性半導体基板31内にN+型でなるソース領域
52及び33が形成され、又基板31上〈深い準位を形
成する不純物の添加され極38及びS9が附されてなる
構成を有する。Next, embodiment #I2 of the semiconductor device according to the present invention will be described with reference to FIG. 2 and FIG. It has an MI8 diode structure in which electrodes 25 and 24 are ohmically attached on the semiconductor layer 22 and on the side of the substrate 21 opposite to the semiconductor layer 22@, and FIG. 5 shows a semi-insulating semiconductor substrate 31 made of InAs. Source regions 52 and 33 of N+ type are formed within the substrate 31, and electrodes 38 and S9 doped with impurities forming a deep level are attached on the substrate 31.
仁の場合、第2図の基板21がIoAa でなり、一層
22がAjab 又はそれと格子定数の略々等しれと
格子定数の略々等しい璽−■族化合物半導体でなる。In the case of a semiconductor substrate, the substrate 21 in FIG. 2 is made of IoAa, and the layer 22 is made of Ajab or a lattice constant of Ajab or a compound semiconductor having a lattice constant substantially equal to that of Ajab.
第1図、第2図及び第3図は本発明による半導体装置の
実施例を示す図である。
第1図
第2図
第3図
り一!−−十31
手続補正書
昭和86年11月24日
特許
昭和 年 願第 最明の名称 半
導体装置
3、 補正をする者
事件との関係 特許出願人
理 人
5、補1
6、補1
7、補
明 細 書 (全文訂正)
1、発明の名称 半導体装置
2、特許請求の範囲
1、 第1の■−■族化合物牛導体でなる半導体基板の
主面上に、低温に於て絶縁性を呈する、深い準位を形成
する不純物の添加されてなる第2の■−■族化合物半導
体でなる層が、低温に於ける絶縁層として形成されてな
る構成を有する事を特徴とする半導体装置。
2、特許請求の範囲第1項所載の半導体装置に於て、上
記第1の■−■族化合物半導体がInPでなり、上記第
2の凪−v族化合物半導体がInP又はそれと格子定数
が略々勢しい謙−V族化合物半導体でなる事を特徴とす
る半導体装置。
五 特許請求の範囲第1項所載の半導体装置に於て、上
記第1の一一■族化合物半導体がGaAs でなり、
上記第2の嵐−■族化合物半導体がGaAs 又はそ
れと格子定数が略々等しい■−■族化合物牛導体でなる
事を%黴とする半導体装置。
4.4I許請求の範囲路1項所載の半導体装置に於て、
上記第1の思−■族化合物半導体がI aim でなり
、上記第2の虱−■族化合物半導体がA/8b 又はそ
れと格子定数か略々等しいl−V族化合物半導体でなる
事を特徴とする半導体装置。
5.41許請求の範囲第1項所載の半導体装置に於て、
上記第1の門−■族化合物半導体がlm8b でなり、
上記第2の門−■族化合物半導体がAJPsb 又は
それと格子定数が略々等しいシー■族化合物半導体でな
る事を特徴とする半導体装置。
3、発明の詳細な説明
本発明は、低温に於て半導体基板の主面上に絶縁層が形
成されて構成を有する、低温に於て機能する半導体装置
に関する。
斯種半導体装置としてl−■族化合物半導体基板を用い
たMI8Il電界効果トランジスタがあるが、斯るMI
8瀝電界効果トランジスタに於て、従来、そのゲート絶
縁層として作用する絶縁層が、m−v族化合物半導体基
板に対する陽極酸化法、熱酸化法、熱窒化法により形成
されてなる絶縁層でなるものが提案されている。
然し乍ら、斯る方法によって形成された絶縁層の場合、
その絶縁層が朧−v族化合物半導体基板を構成せる材料
の酸化物又は窒化物でなるので、nl−v族化合物半導
体基板との間で表面準位の少ない界面を形成せるものと
して良好に形成されているも、熱安定性が惑いという欠
点を有していた。又絶縁層をFfr喪の比較的大なる厚
さを有するものとして形成することが出来ないという欠
点を有していた。
又従来、M18型電界効果トランジスタに於て、そのゲ
ート絶縁層として作用する絶縁層が、真空蒸着法、スパ
ッタリング法により形成されてなる、1t−v族化合物
半導体基板を構成せる材料以外の職化物、例えば8i0
. 、 U、O,等でなる絶縁層でなるものも提案され
ている。
然し乍ら、斯る方法によって形成された絶縁層の場合、
熱安定性が良いものとして形°成されているも、その絶
縁層がm−■族化合物半導体基板を構成せる材料とは異
なる材料の酸化物でなる為、1−■族化合物半導体基板
との間で表面準位密度の少ない界面を形成せるものとし
て形成されていないという欠点を有していた。
依って本発明は上述せる。欠点のない新規な斯檀牛導体
装置を提案せんとするもので、以下詳述する所より明ら
かとなるであろう。
第1図は本発明による半導体装置の第1の実施例を示し
、半絶縁性半導体基板本体1上にN形半導体層2が形成
されてなる構成の■−■族化合物半導体でなる半導体基
板3を有し、その半導体基板3の主面4上にソース電極
5及びドレイン電極6がオーンツクに附され、又主面4
上にソース電極5及びドレイン電極6間に於て、低温に
於て絶縁性を呈する、深い単位を形成する。F・、Or
、0等の不純物の添加されてなるm−■族化合物半導体
でなる層7を介してゲート電極8が配されてなる、MI
81を電界効果トランジスタ構成を有する。
この場合、半絶縁性半導体基板本体1が107〜10Ω
・備の高比抵抗を有する単結晶1nPでなり、又半導体
層2が10 〜101m のキャリア濃度を有する単
結晶InP又は単結晶GaAsでなる。又深い単位を形
成する不純物の添加されてなる一一■族化合物半導体で
なる層7が、半導。
体層2が単結晶InPでなる場合、深い単位を形成する
不純物の添加された単結晶1nP又はそれと格子定数が
略々等しい例えばIn)hlAs P系の単結晶門−■
族化合物半導体でなり、又半導体層2が単結晶()&A
lでなる場合、深い単位を形成する不純物の添加された
単結晶GaAs又はそれと格子定数が略々等しい例えば
GaMhP系の単結−晶■−v族化合物半導体でなる。
以上が本発明による半導体装置の第1の実施例であるが
、斯る構成によれば、その層7は、それが■−■族化合
物半導体でなるとしても、その■−■族化合物半導体に
は深い準位を形成する不純物が添加されているので、常
温に於て高比抵抗を呈し半絶縁性を呈しているものであ
るが、低温(液体窒素温度)に於てm−■族化合物半導
体中に於ける活性な電子濃度が減少することにより、常
温に於ける場合に比し格段的に大なる比抵抗を呈し、従
って高い絶縁性を呈するものである。この為第1図にて
上述せる本発明による半導体装置の第1の実施例の構成
によれば、低温に於て、層7がゲート絶縁層として作用
して、通常のMI8電界効果トランジスタとして動作す
るものである。
斯(第1図にて上述せる本発明による半導体装置の第1
の実施例によれば、層7が低温に於て絶縁層として作用
するものであるが、その層7が、深い単位を形成する不
純物の添加された、半導体基板3の半導体層2と同じ冬
は格子定数が略々等しい厘−V族化合物半導体(半導体
層2が単結晶InPでなる場合、単結晶1nP又はそれ
と格子定数が等しい単結晶服−■族化合物半導体、半導
体2が単結晶GμSである場合、単結晶GaAs又はそ
れと格子定数が等しい単結晶門−■族化合物半導体)で
なるので、層7は半導体基板3の半導体層2との間で表
面準位の少ない界面を形成するものとして良好に形成さ
れているものである。又層7は、絶縁層として作用する
低温の温度範囲に於て、熱的に安定なものである。更に
層7は、Cれを例えばエピタキシャル成長法により所要
の厚さに容易に形成し得るものである。
依って第1図にて上述せる本発明による半導体装置の第
1の実施例によれば、冒頭にて前述せる従来の半導体装
置の利点はこれを有するも欠点を有しないという大なる
特徴を有するものである。
次に第2図を伴なって本発明による半導体装置め第2の
実施例を述べるに、m−v族化合物半導体でなる牛絶縁
性牛導体基板21を有し、その半絶縁性本齢番牛導体基
板21の主面上に、低温に於て絶縁性を呈する、深い準
位を形成するFe、0r10等の不純物の添加されてな
る四−v族化合物半導体でなる層22を介して電極2s
が配され、一方半絶縁性半導体基板21の層22側とは
反対側の主面上に電極24が附されてなる、MI8!!
!ダイオード構成を有する。
この場合、牛絶縁性°半導体基板21が、単結晶 In
A1でなり、又深い単位を形成する不純物の添加されて
なる膳−■族化合物半導体でなる層22が単結晶A/8
b又はそれと格子定数が略々等しいInP 、 In8
1sP系、InabAs系、GaSbAs系の単結晶型
−■族化合物半導体でなる。
以上が本発明による半導体装置の第2の実施例であるが
、斯る構成によれば、その層22は、それが深い単位を
形成する不純物の添加されてなるl−V族化合1半導体
でなるので、第1図にて上述せる本発明による半導体装
置の′IP、1の実施例に於ける層7と閾様に、低温に
於て絶縁層(層22がOrを深い準位を形成する不純物
として添加せる単結晶MSbで−なる場合 1 o 1
2Ω1以上の高比抵抗を有する)として作用して、通常
のMIa型ダイオードとして動作するものである。
斯く第2図にて上述せる本発明による半導体装置の第2
の実施例によれば、層22が低温に於て絶縁層として作
用するものであるが、その層22が、上述せる本発明の
第、1の実施例の場合と同様に、半導体基板21と同じ
又は格子定数か時々等しい■−■族化合物半導体でなる
ので、lm122は、上述せる本発明の第1の実施例の
場合と同様に、半導体基板21との間で表面準位の少な
い界面を形成せるものとして良好に形成されているもの
であり、又絶縁層として作用する低温の温に範囲に於て
熱的に安定なものであり、更に所要の厚さに容易に形成
され得るものである等の大なる特徴を有するものである
。
次に第5図を伴なって本発明による半導体装置の第3の
実施例を述べるに、1t−v族化合物半導体でなるP型
の半絶縁性半導体基板31内にその主面側よりソース領
域としてのN+型の半導体領域62及びドレイン領域と
してのN+型の半導体領域33が形成され、又半絶縁性
半導体基板31の主面の半導体領域32及び65間の領
域に、低温に於て絶縁性を呈する、深い準位を形成する
F・、cr、o等の不純物の添加されてなる膳−V族化
合物でなる層64を介して、ゲート電極35が配され、
又半導体領域32及び53にソース電極5B及び39が
附されてなる、NチャンネルMIa型電界効果トランジ
スタ構成を有する。
この場合、半絶縁性半導体基板31が単結晶In8b
でなり、又深い゛準位を形成する不純物の添加されて
なる一−v族化合物半導体でなる層34が単結晶uSb
又はこれと格子定数の略々等しい単結晶門−v族化合物
半導体でなる。
以上が本発明による半導体装置のtjpJ6の実施例で
あるが、斯る構成によれば、その層64は、それが深い
準位を形成する不純物の添加されてなる朧−■族化合物
半導体でなるので、第2図にて上述ぜる本発明による半
導体装置のwJ2の実施例に於ける鳩22と同様に、低
重に於て絶縁層として作用して、通常のNチャンネルM
la型電界効果トランジスタとして動作するものである
。
斯く第3図にて上述せる本発明による半導体装置の第3
の実施例によれば、層34が低温に・於て絶縁層として
作用するものであるが、その層34が上述せる本発明の
第2の実施例の場合と同様に、半導体基板31と同じ又
は格子定数が略々等しい■−v族化合物半尋体でなるの
で、層54は、上述せる本発明の@2の実施例の場合と
同様に、半導体基板31との間で表面準位の少ない界面
を形成せるものとして良好に形成されているものであり
、又絶縁層として作用する低温の温度範囲に於て熱的に
安定なものであり、更に所要の厚さに容易に形成され得
る等の大なる特徴を有するものである。
尚上述に於ては、本発明をMIa型電界効果トランジス
タ構成、MIa型ダイオード構成に適用した場合の実施
例を述べたが、喪は半導体基板の主面上に低温に於て絶
縁層として作用する層が形成されてなる構成の種々の半
導体装置に本発明を適用し得ること明らかであろう。
4、図面の簡単な説明
第1図、第2図及びIIg!1図は夫々本発明をこよる
半導体装置の第1、$2及び第5の実施例を示す路線的
断面図である。
1中、1は半絶縁性半導体基板本体、2&ま半導体層、
5.21及びSlは半導体基板、44才主面、5及び5
8はソース電極、6及び39Gまドレイン電極、7.2
2及び34は低温番こ於て絶縁性を呈する、深い単位を
形成する不純物の除却されてなる1i−v*化合物半導
体でなる層、8及び35はゲート電極、23及び24は
電極を夫々示す。
出願人 日本電II電話公社FIGS. 1, 2, and 3 are diagrams showing embodiments of a semiconductor device according to the present invention. Figure 1 Figure 2 Figure 3 Riichi! --131 Procedural Amendment Written Patent dated November 24, 1986, Showa Year Application No. Saimei Name Semiconductor Device 3, Relationship with the case of the person making the amendment Patent Applicant Attorney 5, Supplement 1 6, Supplement 1 7, Supplementary Description (corrected full text) 1. Title of the invention: Semiconductor device 2. Claim 1: Insulating property is provided at low temperature on the main surface of the semiconductor substrate made of the first ■-■ group compound conductor. 1. A semiconductor device characterized in that a layer made of a second ■-■ group compound semiconductor doped with an impurity forming a deep level is formed as an insulating layer at a low temperature. 2. In the semiconductor device according to claim 1, the first ■-■ group compound semiconductor is InP, and the second Nagi-V group compound semiconductor is InP or has a lattice constant similar to that of InP. A semiconductor device characterized by being made of a substantially high-density V group compound semiconductor. (5) In the semiconductor device as set forth in claim 1, the first group 11-2 compound semiconductor is made of GaAs,
The above-mentioned second arashi-1 semiconductor device is characterized in that the group compound semiconductor is made of GaAs or a group compound conductor having a lattice constant substantially equal to GaAs. 4.4 In the semiconductor device described in Section 1 of Claims,
The first I-I group compound semiconductor is Iaim, and the second I-I group compound semiconductor is A/8b or an I-V group compound semiconductor having a lattice constant substantially equal to A/8b. semiconductor devices. 5.41 In the semiconductor device described in claim 1,
The first group-III compound semiconductor is lm8b,
A semiconductor device characterized in that the second group compound semiconductor is made of AJPsb or a group compound semiconductor having a lattice constant substantially equal to that of AJPsb. 3. Detailed Description of the Invention The present invention relates to a semiconductor device that functions at low temperatures and has a structure in which an insulating layer is formed on the main surface of a semiconductor substrate at low temperatures. As such a semiconductor device, there is an MI8Il field effect transistor using an I-II group compound semiconductor substrate;
Conventionally, in a field effect transistor, the insulating layer acting as the gate insulating layer is an insulating layer formed by anodizing, thermal oxidizing, or thermal nitriding on an m-v group compound semiconductor substrate. something is proposed. However, in the case of an insulating layer formed by such a method,
Since the insulating layer is made of the oxide or nitride of the material constituting the Oboro-V group compound semiconductor substrate, it can be formed well to form an interface with few surface states with the NL-V group compound semiconductor substrate. However, it had the disadvantage of questionable thermal stability. Another drawback is that the insulating layer cannot be formed to have a relatively large thickness compared to Ffr. Furthermore, conventionally, in the M18 type field effect transistor, the insulating layer acting as the gate insulating layer is formed by a vacuum evaporation method or a sputtering method using a chemical compound other than the material constituting the 1tv group compound semiconductor substrate. , for example 8i0
.. , U, O, etc., have also been proposed. However, in the case of an insulating layer formed by such a method,
Although it is formed to have good thermal stability, its insulating layer is made of an oxide of a material different from the material constituting the m-■ group compound semiconductor substrate, so it is not compatible with the 1-■ group compound semiconductor substrate. It has the disadvantage that it is not formed to form an interface with a low surface state density between the two. Therefore, the present invention has been described above. This will become clear from the detailed description below. FIG. 1 shows a first embodiment of a semiconductor device according to the present invention, in which a semiconductor substrate 3 made of a ■-■ group compound semiconductor has a structure in which an N-type semiconductor layer 2 is formed on a semi-insulating semiconductor substrate body 1. A source electrode 5 and a drain electrode 6 are attached to the main surface 4 of the semiconductor substrate 3, and the main surface 4
A deep unit that exhibits insulating properties at low temperatures is formed between the source electrode 5 and the drain electrode 6 above. F., Or
A gate electrode 8 is disposed through a layer 7 made of an m-■ group compound semiconductor doped with impurities such as , 0, etc.
81 has a field effect transistor configuration. In this case, the semi-insulating semiconductor substrate body 1 has a resistance of 107 to 10Ω.
- The semiconductor layer 2 is made of single crystal InP or single crystal GaAs having a carrier concentration of 10 to 101 m2. Further, the layer 7 made of a Group 11 compound semiconductor to which impurities are added to form deep units is a semiconductor. When the body layer 2 is made of single-crystal InP, the single-crystal 1nP doped with impurities forming a deep unit or the single-crystal 1nP having substantially the same lattice constant as that, for example, In)hlAsP-based single-crystal -■
The semiconductor layer 2 is made of a group compound semiconductor, and the semiconductor layer 2 is made of a single crystal ()&A
In the case of 1, it is made of impurity-doped single crystal GaAs forming a deep unit, or a GaMhP-based single crystal 1-V group compound semiconductor having approximately the same lattice constant as that of single crystal GaAs. The above is the first embodiment of the semiconductor device according to the present invention. According to such a structure, even if the layer 7 is made of a ■-■ group compound semiconductor, the layer 7 is made of a ■-■ group compound semiconductor. Because they are doped with impurities that form deep levels, they exhibit high resistivity and semi-insulating properties at room temperature, but at low temperatures (liquid nitrogen temperature) By reducing the concentration of active electrons in the semiconductor, it exhibits a much higher resistivity than at room temperature, and therefore exhibits high insulation properties. Therefore, according to the structure of the first embodiment of the semiconductor device according to the present invention described above in FIG. It is something to do. (The first part of the semiconductor device according to the present invention shown in FIG. 1)
According to the embodiment, the layer 7 acts as an insulating layer at low temperatures, but the layer 7 is exposed to the same winter temperature as the semiconductor layer 2 of the semiconductor substrate 3 doped with impurities forming deep units. is a group V compound semiconductor with approximately equal lattice constants (if the semiconductor layer 2 is made of single crystal InP, the semiconductor layer 2 is made of single crystal 1nP or a single crystal compound semiconductor with a lattice constant equal to that of single crystal 1nP, and the semiconductor layer 2 is made of single crystal GμS). In some cases, the layer 7 is made of single-crystal GaAs or a single-crystal group-III compound semiconductor with the same lattice constant as that of single-crystal GaAs, so the layer 7 forms an interface with few surface states with the semiconductor layer 2 of the semiconductor substrate 3. It is well formed. Layer 7 is also thermally stable in the low temperature range where it acts as an insulating layer. Furthermore, the layer 7 can be easily formed to a desired thickness by, for example, epitaxial growth. Therefore, the first embodiment of the semiconductor device according to the present invention, which is described above with reference to FIG. It is something. Next, a second embodiment of the semiconductor device according to the present invention will be described with reference to FIG. An electrode is formed on the main surface of the conductive substrate 21 via a layer 22 made of a 4-V compound semiconductor doped with impurities such as Fe and 0R10 that exhibit insulating properties at low temperatures and form deep levels. 2s
MI8! is arranged, and an electrode 24 is attached on the main surface of the semi-insulating semiconductor substrate 21 on the opposite side to the layer 22 side. !
! It has a diode configuration. In this case, the insulating semiconductor substrate 21 is made of single crystal In
A layer 22 made of a group compound semiconductor made of A1 and doped with impurities forming deep units is a single crystal A/8.
b or InP with a lattice constant approximately equal to it, In8
It is made of a 1sP-based, InabAs-based, or GaSbAs-based single-crystal type -■ group compound semiconductor. The above is the second embodiment of the semiconductor device according to the present invention. According to this configuration, the layer 22 is a l-V group compound 1 semiconductor doped with impurities forming deep units. Therefore, in the same way as the layer 7 in the embodiment 1 of the semiconductor device according to the present invention described above in FIG. When single crystal MSb added as an impurity becomes -1 o 1
It has a high specific resistance of 2Ω1 or more) and operates as a normal MIa type diode. Thus, in FIG.
According to the embodiment, the layer 22 acts as an insulating layer at low temperatures, but the layer 22 is connected to the semiconductor substrate 21 as in the first embodiment of the present invention described above. Since it is made of a ■-■ group compound semiconductor with the same or sometimes the same lattice constant, the lm122 forms an interface with few surface states with the semiconductor substrate 21, as in the case of the first embodiment of the present invention described above. It is well formed and thermally stable in the low temperature range where it acts as an insulating layer, and it can be easily formed to the required thickness. It has certain great characteristics. Next, a third embodiment of the semiconductor device according to the present invention will be described with reference to FIG. An N+ type semiconductor region 62 as a drain region and an N+ type semiconductor region 33 as a drain region are formed in the region between the semiconductor regions 32 and 65 on the main surface of the semi-insulating semiconductor substrate 31. A gate electrode 35 is disposed through a layer 64 made of a V-group compound doped with impurities such as F, Cr, and O, which forms a deep level exhibiting .
Further, it has an N-channel MIa type field effect transistor configuration in which source electrodes 5B and 39 are attached to semiconductor regions 32 and 53. In this case, the semi-insulating semiconductor substrate 31 is made of single crystal In8b
The layer 34 made of a group I-V compound semiconductor doped with impurities to form a deep level is single crystal uSb.
Alternatively, it is made of a single-crystal group-V compound semiconductor having substantially the same lattice constant as this. The above is an embodiment of the semiconductor device tjpJ6 according to the present invention. According to such a structure, the layer 64 is made of an oboro-■ group compound semiconductor doped with impurities that form a deep level. Therefore, like the pigeon 22 in the embodiment wJ2 of the semiconductor device according to the present invention described above in FIG.
It operates as a la-type field effect transistor. Thus, the third embodiment of the semiconductor device according to the present invention described above in FIG.
According to the embodiment, the layer 34 acts as an insulating layer at low temperatures, but the layer 34 is the same as the semiconductor substrate 31, as in the second embodiment of the invention described above. Alternatively, since the layer 54 is made of a half-solid compound of the ■-v group having approximately the same lattice constants, the layer 54 has a surface level difference between it and the semiconductor substrate 31, as in the case of the embodiment @2 of the present invention described above. It is well formed as it allows for the formation of few interfaces, it is thermally stable in the low temperature range where it acts as an insulating layer, and it can be easily formed to the required thickness. It has the following great characteristics. In the above, embodiments have been described in which the present invention is applied to an MIa type field effect transistor configuration and an MIa type diode configuration. It will be obvious that the present invention can be applied to various semiconductor devices having a structure in which a layer is formed. 4. Brief explanation of the drawings Figures 1, 2 and IIg! FIG. 1 is a cross-sectional view showing a first embodiment, a second embodiment, and a fifth embodiment of a semiconductor device according to the present invention. In 1, 1 is a semi-insulating semiconductor substrate body, 2 & a semiconductor layer,
5.21 and Sl are semiconductor substrates, 44 years old main surface, 5 and 5
8 is a source electrode, 6 and 39G are a drain electrode, 7.2
2 and 34 are layers made of a 1i-v* compound semiconductor from which impurities forming deep units have been removed, exhibiting insulating properties at low temperatures, 8 and 35 are gate electrodes, and 23 and 24 are electrodes, respectively. . Applicant: Nippon Denki II Telephone Corporation
Claims (1)
主面上に、低温に於て絶縁性を呈する、深い準位を形成
する不純物の添加されてなるts2のi−v族化合物半
導体でなる層が、低温に於ける絶縁層として形成されて
なる構成を有する事を特徴とする半導体装置。 2、特許請求の範囲第1項所載の半導体装置に於て、上
記第1のI−V族化合物半導体がInPでなり、上記第
2のI−Y族化合物半導体がInP又はそれと格子定数
が略々等しい■−V族化合物半導体でなる事を特徴とす
る半導体装置。 五 特許請求の範囲第1項所載の半導体装置に於て、上
記j11のI −V族化合物半導体がGaAs でな
り、上記第2の璽−v族化合物半導体がGaAt又はそ
れと格子定数が略々等しい璽−v族化合物半導体でなる
事を特徴とする半導体装置。 4.4I許請求の範囲第1項所載の半導体装置に於て、
上記第1のI−V族化合物半導体がInA@ でなり、
上記第2のI−V族化合物半導体がIJ8b 又はそ
れと格子定数が略々等しいI−V族化合物半導体でなる
事を%徴とする半導体装置。 5、特許請求の範囲第1項所載の半導体装置に於て、上
記第1の■−マ族化合物半導体がI aab でなり、
上記第2のl−V族化合物半導体がムj8b 又はそ
れと格子定数が略々等しいI−V族化合物半導体でなる
事を特徴とする半導体装置。[Claims] A ts2 i formed by doping an impurity forming a deep level exhibiting insulating properties at low temperatures on the main surface of a semiconductor substrate made of a 1.4i1 IV group compound semiconductor. - A semiconductor device characterized in that it has a structure in which a layer made of a V group compound semiconductor is formed as an insulating layer at low temperatures. 2. In the semiconductor device according to claim 1, the first IV group compound semiconductor is made of InP, and the second I-Y group compound semiconductor is InP or has a lattice constant similar to that of InP. A semiconductor device characterized in that it is made of approximately the same ■-V group compound semiconductor. (5) In the semiconductor device set forth in claim 1, the I-V group compound semiconductor j11 is made of GaAs, and the second A-V group compound semiconductor is GaAt or has a lattice constant approximately equal to that of GaAs. 1. A semiconductor device characterized by being made of an identical P-V group compound semiconductor. 4.4I In the semiconductor device described in claim 1,
The first IV group compound semiconductor is InA@,
A semiconductor device characterized in that the second IV group compound semiconductor is made of IJ8b or an IV group compound semiconductor having a lattice constant substantially equal to IJ8b. 5. In the semiconductor device set forth in claim 1, the first ■-Ma group compound semiconductor is Iaab,
A semiconductor device characterized in that the second l-V group compound semiconductor is made of muj8b or an I-V group compound semiconductor having a lattice constant substantially equal to that of muj8b.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP56180478A JPS5882570A (en) | 1981-11-11 | 1981-11-11 | Semiconductor device |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP56180478A JPS5882570A (en) | 1981-11-11 | 1981-11-11 | Semiconductor device |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPS5882570A true JPS5882570A (en) | 1983-05-18 |
Family
ID=16083917
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP56180478A Pending JPS5882570A (en) | 1981-11-11 | 1981-11-11 | Semiconductor device |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPS5882570A (en) |
Cited By (6)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US4567503A (en) * | 1983-06-29 | 1986-01-28 | Stauffer Chemical Company | MIS Device employing elemental pnictide or polyphosphide insulating layers |
| FR2569056A1 (en) * | 1984-08-08 | 1986-02-14 | Japan Res Dev Corp | TUNNEL INJECTION TYPE STATIC INDUCTION TRANSISTOR AND INTEGRATED CIRCUIT COMPRISING SUCH A TRANSISTOR |
| JPS62262467A (en) * | 1986-05-08 | 1987-11-14 | Nec Corp | field effect transistor |
| JPS62268165A (en) * | 1986-05-15 | 1987-11-20 | Nec Corp | field effect transistor |
| US5247349A (en) * | 1982-11-16 | 1993-09-21 | Stauffer Chemical Company | Passivation and insulation of III-V devices with pnictides, particularly amorphous pnictides having a layer-like structure |
| JP2009197954A (en) * | 2008-02-25 | 2009-09-03 | Shindengen Mechatronics Co Ltd | Valve |
-
1981
- 1981-11-11 JP JP56180478A patent/JPS5882570A/en active Pending
Cited By (6)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US5247349A (en) * | 1982-11-16 | 1993-09-21 | Stauffer Chemical Company | Passivation and insulation of III-V devices with pnictides, particularly amorphous pnictides having a layer-like structure |
| US4567503A (en) * | 1983-06-29 | 1986-01-28 | Stauffer Chemical Company | MIS Device employing elemental pnictide or polyphosphide insulating layers |
| FR2569056A1 (en) * | 1984-08-08 | 1986-02-14 | Japan Res Dev Corp | TUNNEL INJECTION TYPE STATIC INDUCTION TRANSISTOR AND INTEGRATED CIRCUIT COMPRISING SUCH A TRANSISTOR |
| JPS62262467A (en) * | 1986-05-08 | 1987-11-14 | Nec Corp | field effect transistor |
| JPS62268165A (en) * | 1986-05-15 | 1987-11-20 | Nec Corp | field effect transistor |
| JP2009197954A (en) * | 2008-02-25 | 2009-09-03 | Shindengen Mechatronics Co Ltd | Valve |
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| US5506422A (en) | MOIS junction for use in a diamond electronic device | |
| US20080230867A1 (en) | Method of forming ohmic contact to a semiconductor body | |
| US4387387A (en) | PN Or PIN junction type semiconductor photoelectric conversion device | |
| KR920015626A (en) | Superconducting Field Effect Transistor with Inverted MISFET Structure and Manufacturing Method Thereof | |
| JPH06120520A (en) | Field effect transistor with non-linear transfer characteristics. | |
| JPS5882570A (en) | Semiconductor device | |
| US3706128A (en) | Surface barrier diode having a hypersensitive n region forming a hypersensitive voltage variable capacitor | |
| FR2379134A1 (en) | SEMICONDUCTOR MEMORY | |
| US4794444A (en) | Ohmic contact and method for making same | |
| US5045497A (en) | Method of making a schottky electrode | |
| US3959036A (en) | Method for the production of a germanium doped gas contact layer | |
| US4517121A (en) | Method of increasing the supraconductive critical temperature in quasi unidimensional organic supraconductors and new supraconductive compounds thus obtained | |
| JPH0666467B2 (en) | Semiconductor device | |
| JPH0359580B2 (en) | ||
| JP2817718B2 (en) | Tunnel transistor and manufacturing method thereof | |
| JPS6339110B2 (en) | ||
| KR840005930A (en) | Semiconductor device | |
| JPS62209855A (en) | Semiconductor element using silicon carbide | |
| JPS62213179A (en) | Josephson junction element | |
| JPS5911684A (en) | Forming method for buried gate of semiconductor device | |
| KR950010868B1 (en) | Ferroelectric Thin Film Devices | |
| JPH0556849B2 (en) | ||
| JPS59114873A (en) | Semiconductor device | |
| JPS62169482A (en) | Manufacture of semiconductor device | |
| JPS6142179A (en) | Semiconductor-coupled superconductive element and manufacture thereof |