JPS5883394A - Signal transmission method for semiconductor integrated circuits - Google Patents

Abstract

PURPOSE:To perform stable in-phase transfer, by providing an intermediate latch between in-phase transfer latches, and supplying it with a timing signal complementary to the timing signal of the in-phase transfer latches. CONSTITUTION:Serial latches 41-43 are in-phase transfer latches 41 and 43 controlled by the same timing signal and an intermediate latch controlled by a timing signal complementary to said timing signal, and they perform transfer operation with characteristic time lags t11, t21 and t61 behind the timing signal. Even if the timing signal varies in width according to the complementary timing signal, a state change of timing is made at the same time at the same time to perform stable operation without depending upon the pulse width of the timing signal, and the signal latched by the latch 41 is transferred in an in-phase state from the latch 43 at next timing. Further, both timing signals are generated on a semiconductor chip to reduce the influence of a timing skew, and the signal transmission system of a semiconductor integrated circuit which perfoms stable operation is obtained.

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a signal transmission system for semiconductor integrated circuits, and more particularly to a signal transmission system that can reliably perform in-phase transfer within an integrated circuit.

In data processing equipment such as digital combinations, in order to simplify the installation F and AM etc., a method of synchronizing the operation of the logic with the timing signal is M%/hb.
Timing signal shown in vh house, building 1 illustration)! Based on O, the signal repetition time (!thin nital) I
Divide C (seconds) into three equal parts, and throw the responsible timing signals 'l'l, 'I'2.'L'3 at each dividing point, mlI!p
It is often operated as WF evening -0ζζ,! L (integer) is called the phase number.

Figure 1 (→To shows the conventional logic circuit when Hanso* is the turn), Figure 1 (Xun is its timing chart) ◎ At the 1N-, latches 1, 2, . Numerals 3 and 4 are latches housed in respective integrated circuits, and each operates according to the timing 〒0.〒1.'l'2.'!'3EIljl.
, 12.15#i are circuits provided between the respective latches to perform logic operations, and inverters 11 and 13 are circuits for inverting the input to the NAND 9 gate 12.14.

The signal applied to the D input terminal of latch 1 is
The output of is applied to the D input terminal of latch 2 via gate 11.12. The signal applied to the p input terminal of latch 2 is taken into latch 2 at timing 'I'l. On the other hand, the signal applied to the D input terminal of the latch is the external signal 0.
D, and the latch is fed at timing T2. Next, the outputs of latch 2 and latch number are applied to the p input terminal of latch 6 via gates 13 and 14, and are taken into latch 3 at timing T3.

Further, the output of the latch 3 is applied to the D input terminal of the edge 1 via the OR gate 10. Below, do the same thing and time! 'O,'l'1. ! 2, latches 1 to 4 operate in sequence according to Tδ to perform a logical operation.

In this way, signal transmission between each latch requires a printed wiring board, coaxial line, gate, etc., which naturally requires time for transmission. If the timing interval of the latch is less than or equal to the timing interval of the latch, the signal sent from the one signal source latch will be in time with the timing of the receiving side latch, so that it will be taken into the receiving side latch in a normal state. In other words, in the case of the first latches, the timing interval is T074, so the transmission time between each latch is ! If it is 74 or less, it will be successfully captured by the bank.

On the other hand, if the latch transmission time exceeds the timing *m of each latch, the timing of the receiving latch operates, and the D input terminal of the receiving latch receives the signal from the transmitting value latch. Since the signal is being transmitted and remains at 1, the receiving latch will not be able to receive normal data.

On the other hand, in the case where each of the latches 1 to 111 are accommodated in one integrated circuit, the signal transmission time is almost negligible and the signal transmission time is small. There is no same layer and it should work normally.

In this case, it is only necessary to consider the maximum value of the latch transmission time during design, i.e., ! Between 0 and T1! 0~!
2 leaps, between 70 and 73? between l-'1''2, between 11 and 73, between 71 and 10, between T2 and 3, between 〒2 and TO, between 72 and
Between 71, between 73 and 10, between 13 and 71, 'iI3~'!
' Regarding signal transmission between different timings such as between two
Even if the maximum signal transmission time between each latch is less than the specified value, d
That means it's good.

On the other hand, as each timing interval becomes narrower, it is desirable to have two phases for each phase, and furthermore, it is more desirable for performance to have only one phase instead of two phases, so in-phase transfer becomes more common. Between 70 and 70? 1-1 ISl leap, between 72-72, T
3~! In the case of in-phase transfer such as 3-way transfer, the latch output on the signal source side will reach the D input terminal of the receiving side latch within the effective time (within the pulse width) of the timing signal on the receiving side. Then, the receiving latch does not take in the signal from the D input terminal at the same timing as the signal source latch, instead of taking in the signal to the receiving latch at the originally expected timing one cycle later. occurs.

FIG. 2 (&) (b) is a WiHm diagram and a time chart showing the operation of conventional in-phase transfer.

- The signal source side latch 21 and the receiving side latch 22 housed in the same integrated circuit, the ties 201 (TOCA) and 202 ('1'0@) shown in FIG. 2(b), respectively.
The gates 31, 32, and 33 are for transmitting signals from the latch 21 to the latch 221, and the description of input signals from other signal sources is omitted.
Further, No. 3 is an amplifier for supplying the timing signal 〒0 to the latches 21 and 22. 1t of this amplifier 5!4
2 pieces of IR (201) (202), one of them
') signal (201) has a signal name 'l'o(A) and is supplied to the latch 21E, and the other signal (202) II'i signal name! 0@ and is supplied to the latch 22.

As shown in FIG. 2 (2), the signals (201) and (202
), there is a power feeding difference (generally referred to as timing difference) ΔT. The timing (201) of the signal source side latch 21 is in an advanced phase, and the timing (202) of the receiving side latch 22 is in an advanced phase. In the case of a delayed phase, as mentioned above, a malfunction is likely to occur in which the receiving latch receives the signal at the same timing as the signal source latch.

(203), (204), (205) shown in Figure 2
The relationship indicates such a malfunction.

Since the transmission time of gates 31, 32, and 33 is short, the output signal (203) of the latch 21 and the output signal (203) of the gate 33 are
204), and the output signal (204) of the gate 33 reaches the D input terminal of the latch 22 within the time period in which the timing (c) of the latch 22 exists. Therefore, the latch 22 provides an output waveform like the signal (205), but the originally expected waveform is a waveform that rises at the time of the signal (205'). After all, in order to successfully perform such in-phase transfer, it is necessary to design the system to satisfy the conditions shown in the following equation.

111w1n>'! 'Wmaz+Δ〒wax
” ” ” ■Here, t)1□, ke latch 2
1 and the latch 22, T, □ is the maximum value of the timing pulse width, and ΔT, Δ is the maximum value of the timing gap.

In other words, Equation (1) above is based on the maximum value of the pulse width "vma" that guarantees normal operation, and the timing summation.
This shows that the transmission time must be greater than or equal to the algebraic sum of 〒 to the maximum value of The machine size, tal T, must be less than or equal to .In the end, the transmission time ta of chichi 21 and 22 leaps must satisfy the following equation.

〒 >s >T +ΔIII□d...
■@t W+@&! It is possible to set the timing pulse width '1' by finely adjusting the transmission time of the tie mini/da power supply system.
',,,, To guarantee the operation of the xa latch, it is not possible to lower it below a certain level (for example, Irx, ,,,p O
L-type latches require 4 to 51 L8 or more pulses and filtration).If variations in pulse width are included, this is a fairly large value.Latch? It is necessary to guarantee the transmission time between l and 22. Recent digital combinations use pipeline control methods or
methods such as shortening the engine cycle are used. Machine
-11 As the number of timing phases decreases, the number of timing phases is decreasing to two phases.As the number of timing phases decreases, the number of in-phase transfers increases significantly, and the number of latch phases decreases during design. As a result of an increase in the number of networks (routes) that must guarantee the minimum transmission time between 1. The drawback is that the number of design steps increases significantly. Furthermore, in recent years, as the degree of integration of semiconductors has increased, it has become necessary to incorporate -1 in-phase transfer logic inside the semiconductor chip. In order to guarantee the minimum transmission time, a method of using gates as delay elements is used. There is a drawback that power consumption increases as the number increases.

The purpose of the present invention is to eliminate these conventional drawbacks by easily realizing in-phase transfer on a highly integrated semiconductor chip, and by eliminating the need to set a minimum transmission time between latches that perform in-phase transfer. An object of the present invention is to provide a signal transmission method for semiconductor integrated circuits that eliminates the constraints of The 1st, 2nd and 3rd latch groups are connected in series with or without intervening groups, and the same timing is supplied to the 1st and 3rd latch groups, and the 1st and 2nd latch groups are provided with the It is characterized in that it performs in-phase transfer by supplying timing that is in a phase relationship with the timing. Hereinafter, an actual example of the present invention will be explained with reference to FIG. 3. Figure 3 shows part of the logic circuit configured on the chip.
This is an operation time chart of the logic circuit shown in (a).
[The third latch 43 is the signal source side latch that operates at timing 101 ('I'0), and the third latch 43 is the receiver side latch that operates at the same timing 101 (To) as above. 〉, second latch again! 2t; is an intermediate latch that operates at a timing 102 ('I'O) that is opposite in phase to the above timing. timing! Amplifier No. 4 is connected to the end of input terminal 57 of 0, which generates outputs 101 ('1'O) and 102 (ffi) in response to timing TO. '& O, the output 106ti of the third latch 43 is connected from the data output terminal 63 to the next latch in the chip outside the chip.

As shown in Figure 3 (→), the signal (103) given to the data input terminal 51 is "1" at time 0, and is not "1" until time t, as shown in Figure 3 @ (2). This signal (103)-
It gives up and is taken into the latch 41 in synchronization with the timing αo1) which becomes 1 at time ``10''. At 1llllt, the timing (102) is input to the intermediate tick 42.
- becomes "0", the latch 42 is in an inactive state, that is, data input is not accepted, and the intermediate latch - is in the X&- state.
The output of 42 (105) is hour*1. , and social barbarism 'Ik
At mt, .V''e time, the timing signal (101
) is "0' to 1, timing signal! (102) t8
．． ~ts, the state of the signal (103) applied to the data input terminal of the latch 41 is held, and the state of the signal (103) applied to the data input terminal of the latch 41 is held during
6. ~"set t to change the output, 1 to 10 intermediate latch 42, time t,. At time t, the timing signal (1
02) becomes 1, the signal (104) applied to the data input terminal is input. Output of intermediate latch number 2 (1
05) At the time of double transmission of the intermediate latch 42, time t11. becomes “1”.

At time mt, 1, the timing signal of the latch 43 becomes 10', so at this point the signal (105) applied to the data input terminal cannot be input, and the output of the latch 48 (106 ) does not change.

At time t5., the input signal (103) is "1" because there is no change in the state of the signal.
It changes from “0”, but tsu-! Since the timing signal 41 is "0", the state m of the latch 41 does not change. Time*1. .

At this time, the timing signals (101) and (102) each change from 0 or 1.1 to 0, so the states of latches 41 and 43 change, and the unique transmission time of each latch 41 and 43 is slightly delayed. At time t6□, the output of the latch 41 (1
04) is l to 0, output of chichi 43 (106)
may change from 0 to 1.

At time t6°, the timing signal (102) of the intermediate latch 42 changes from 1 to 0, so from time t6° to t
,. During this period, the state m of the latch 42 does not change and remains the same as the previous state 11.
is held when mt. In, RiaIII
When the sIm timing signal (102) changes from 0 to 1,
The intermediate latch 42 receives the signal (
104) changes to 0, but latch 4
As mentioned above, the output (105) of 2 is delayed by rt' during the characteristic transmission of the latch 42; *1. , it changes to 0.

In this way, the signal (10
3) appears at the output terminal 53 after l timing and performs the desired operation. Note that even if the pulse width of the timing signal (TO) applied to the input terminal 52 changes, the timing signal (101) Because of the complementary relationship between (102) and (102), the timing state changes occur simultaneously in the lightning, ensuring stable operation that does not depend on the pulse view of the timing signal. Since the timings (101) and (102) are generated on-chip, the timing skew of the input (101) and (102) leaps is extremely small and can be ignored. guaranteed operation.

3 mm (-), to simplify the explanation, the logic gates between the first latch 41 and the intermediate latch 42 and between the intermediate latch 42 and the third latch 43 are omitted; , 42 , It is of course possible to insert a logic gate between the gates 3 and 3. When a logic gate is inserted,
It is necessary to install the intermediate latch in a position such that the number of other intermediate latches that perform the same operation as the intermediate latch 42 is minimized. can be realized.

As explained above, according to the present invention, an intermediate latch is installed between one in-phase transfer latch, and a timing signal complementary to the timing signal supplied to the in-phase transfer latch is supplied to the intermediate latch. The in-phase transfer logic can be assembled on a semiconductor chip without considering the minimum transmission time of , and the in-phase transfer can be performed stably even if the pulse width of the timing signal supplied to the chip group changes.

[Brief explanation of the drawing]

Figure 1 is a logic circuit diagram showing a conventional signal transmission method using multi-phase transfer and its time and chart; Figure 2 is a logic circuit diagram and its time and chart showing a conventional signal transmission method using in-phase transfer; Figure 3 is a logic circuit diagram and its time and chart. Book 1.2, 3, 21, 22, 4
1, 42, 43! Latch, 34.44 = Amplifier, 101
, 102, 201, 202: timing signal, 10-1
5.31-33: Logic gate. Figure 1 (a) Figure 2 Mu T (205') Figure 3 (a)

Claims (1)

[Claims] ■ Temporarily storing logic signals, etc., without intervening a group of logic operation elements. $11. 2nd and 3rd
latch groups are serially connected, the same timing is supplied to the first and third latch groups, and timing complementary to the above timing is supplied to the second and third latch groups, A signal transmission method for a semiconductor integrated circuit, characterized in that in-phase transfer is performed between the first and third latch groups. ■The above 1. The second and third latch groups
2. A signal transmission system for semiconductor integrated circuits according to claim 1, wherein the signal transmission system is connected in multiple stages as a set.