JPS588625B2 - Denshisousasouchi - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention relates to an electronic scanning device for auxiliary electrodes used in solid state scanning recording devices.

FIG. 1 is a block diagram showing an example of a multi-stylus of a solid-state scanning recording device to which the present invention is applied, and the recording electrodes are grouped into GB and GO as seen in the figure.

The auxiliary electrodes GA-1, .

In FIG. 1, the positions of the auxiliary electrodes and the grouping of the recording electrodes GB and GO are different from the conventional ones, and the collection of recording electrodes GB is auxiliary electrodes GA-1 and GA-2, GA-3 and GA-4,
. . . It exists almost equally between the two auxiliary electrodes.

Therefore, in actual recording, for example, when a positive voltage is applied to the recording electrode GR-1, a negative voltage is applied to the two auxiliary electrodes GA-1 and GA-2.

In this way, recording is performed using a plurality of auxiliary electrodes.

In addition, recording with the recording electrode GO is performed using the auxiliary electrodes GA-2 and G.
Voltages are applied in combinations such as A-3, GA-4 and GA-5, etc.

By using the auxiliary electrodes in this manner, it has been possible to completely improve the conventional problem that recordings at the joints of the auxiliary electrodes were not sufficiently uniform.

Note that, in the above description, a negative voltage is applied to the recording electrode and a positive voltage is applied to the auxiliary electrode, but the polarities of both may be reversed.

However, at present, it is advantageous to apply a negative voltage to the recording electrode and a positive voltage to the auxiliary electrode due to problems such as the stability of the developing toner and the staining of the recording paper.

The case where a positive voltage is applied to the auxiliary electrode will be described below.

FIG. 2 is a circuit diagram of a conventional electronic scanning device, and FIG. 3 is a waveform diagram for explaining its operation.

In Figure 2, the number of auxiliary electrode divisions is 60, so 60
Zero-stage shift registers 11, . . . , 160 are provided.

When the reset pulse shown in FIG. 3 is applied to this shift register, only shift registers 1 and 12 become "1".
, and all others are "0".

After that, the shift pulse shown in FIG. 3 is applied to the shift registers 12 to 1.
60, the shift registers are sequentially shifted, and the respective outputs of the shift registers and the narrow stroke pulse shown in FIG.
60, and its output is the final stage transistor 31.
360, and sequentially applies a voltage of +300 V to the auxiliary electrodes GA-1 to GA-64 as shown in FIG.

Here, in the circuit configuration diagram of FIG. 2, transistors 31 to
360 is on most of the time, and is turned off only at the instants of GA-1 to GA-60 in FIG.

Therefore, power is constantly consumed in the collector resistors of the transistors 31 to 360.

In order to reduce the power consumption and size of this device, it is conceivable to increase the resistance value of the collector resistor or to use a PNP transistor so that an output is produced during the ON time of the transistor.

However, the P of 300 V or more required for solid-state scanning electrostatic recording
NP transistors are not preferred because they are expensive, so if an NPN transistor is used and the collector resistance is increased, the rise time will be longer due to the distributed capacitance, and a pulse with a narrow pulse width of 60 μS or less will not be generated.

In the case of this solid-state scanning recording method, the pulse width is 20 μS to 6
0 μS is appropriate; if it is thinner than this, the recording density will be low.
If it is too thick, recording will occur even in areas where no voltage is applied to the auxiliary electrode.

Further, the disadvantage of the circuit diagram shown in FIG. 2 is that in addition to these, 60 high-voltage transistors are used, making it very expensive.

SUMMARY OF THE INVENTION An object of the present invention is to provide an electronic scanning device for auxiliary electrodes that eliminates the above-mentioned disadvantages of high power, large size, and high cost.

An embodiment of the present invention will be described below with reference to FIGS. 4 to 8.

FIG. 4 is a circuit configuration diagram of the present invention, and FIG. 5 is a waveform diagram for explaining its operation.
The reset pulse S0 shown in the figure is applied, and this reset pulse S0 is generated only at the start of one line scan to reset all the circuits.

The strobe pulse S2 applied to the input terminal S2 is a command signal for causing the output terminal to output a signal.

In addition, a shift pulse S1 applied to the input terminal S1
is always generated after the strobe pulse S2, and is the base signal for sweeping the present electronic scanning device.

In addition, this shift pulse S1 is applied to the 60 auxiliary electrodes GA.
In order to give signals to -1 to GA-60, 60 signals are output within one line scanning time.

10 is a hexadecimal up-down counter circuit composed of a four-stage flip-flop circuit, which adds the count when a pulse is input to the up input terminal, and subtracts the count when a pulse is input to the down input terminal.

Note that this counter circuit 10 operates at the falling edge of a pulse.

Outputs 101 to 104 of the counter circuit 10 serve as inputs to a decoder 11 that synthesizes four inputs each to produce 16 outputs.

The decoder 11 outputs "1" from one of the 16 outputs 110 to 1115 based on a combination of the four outputs of the counter circuit 10.

Furthermore, since the outputs 110 to 1115 of the decoder 11 are input to the NOR circuits 120 to 1214, respectively, the truth table seen at the output portions of the NOR circuits 120 to 1214 is as shown in FIG.

In other words, the "0" outputs of the NOR circuits 120 to 1214 are output to the adjacent NOR circuits, and this is the shift pulse S.
1 is sequentially shifted.

That is, the shift pulse S1 causes the counter circuit 10 to
When applied to the input terminal, the NOR circuits 120 to 12
14, it is shifted in the direction from 120 to 1214 (downward direction in Figure 4), and when applied to the down input terminal, it is shifted in the direction from 1214 to 120 (upward direction in Figure 4). .

Further, reference numeral 13 denotes a flip-flop circuit (hereinafter referred to as FF circuit), and it is this FF circuit 13 that switches whether to input the shift pulse S4 to the up input terminal of the counter circuit 10 or to the down input terminal, and the AND circuit 141
and 142 are used for switching.

The reset pulse S0 is connected to the clear terminal of the FF circuit 13 and the counter circuit 10, and when this reset pulse S0 is input, the Q output of the FF circuit 13 becomes "1", and the counter circuit 10 becomes "1 count". shall be set to the state.

Now, when the reset pulse S0 is applied, the FF circuit 1
3 becomes the Q output "1" and the Q output "0", so the AND circuit 141 operates, and the AND circuit 142 is closed, so the shift pulse S1 passes through the AND circuit 141 and becomes the up input terminal of the counter circuit 10. is input.

Since this counter circuit 10 is set to the state of "counting 1", only the decoder 11 111 outputs "1", and only the NOR circuits 120 and 121 output "0".

When the shift pulse S1 is applied in this state, the counter circuit 10 is incremented, so the NOR circuit 120~
When looking at 1214, the place where the [0] output comes from is 121
and 122, 122 and 123, 123 and 124...
As shown in Figure 4, it is shifted downward.

Next, when the output 1115 of the decoder 11 becomes "1", the output is applied to the NOR circuit 1214 and also to the R terminal of the FF circuit 13, so that
The FF circuit 13 inverts the Q output to "0" and the Q output to "1".

As a result, the counter circuit 10 has been counting up until now, but will now count down.

At this time, only the NOR circuit 1214 outputs "0", but
Each time the shift pulse S1 enters, the NOR circuit 120~
The places where 1214 outputs “0” are 1214 and 121
3, 1213 and 1212, 1212 and 1211,...
As shown in Figure 4, it is shifted upward.

Furthermore, when the [1] output is output to the output 110 of the decoder 11, the output is applied to the NOR circuit 120 and also to the S terminal of the FF circuit 13, so the F
The F circuit 13 inverts the Q output to "1" and the Q output to "1".

Therefore, from now on, the state will be the above-mentioned up count, and the fourth
In the figure, it is shifted downward.

Thereafter, the up-down process is repeated in the same way. That is,
Counter circuit 10, decoder 11, NOR circuit 120-1
214, FF circuit 13 and AND circuits 141, 142
The operation of is a scanning circuit, but it does not proceed only in one direction, but when it is shifted and reaches the end point, it is shifted in the opposite direction.

Descriptions of these waveforms are as shown at 120 to 1214 in FIG.

Further, the NOR circuits 120 to 1214 are connected to the paces of the transistors (hereinafter referred to as Tr) 100 to 114, respectively, and only when the output is "0", the transistors 100 to 1214
114 is cut off.

At this time, if any of Tr1001 to Tr1004 is outputting a high voltage, an output is output at the intersection, but the NOR circuit 12
Where the output of 0 to 1214 is "1", Tr100 to 1
14 is turned on, even if Tr 1001 to 1004 output a high voltage, no output is output to the corresponding part.

The above solid counter circuit 10, decoder 11, NOR circuits 120 to 1214, FF circuit 13 and AND circuit 14
1,142 is a first scanning circuit, and the present invention provides another second scanning circuit.

The present invention attempts to synthesize the outputs of both scanning circuits and output various types of outputs.

Next, this second scanning circuit will be explained.

The second scanning circuit includes a counter circuit 15,
Decoder 16, OR circuits 170 to 173, AND circuit 1
81, 182, an OR circuit 19 and an AND circuit 20.

The counter circuit 15 is an octal counter circuit composed of three stages of FF circuits, and the decoder 16 synthesizes the three outputs 151 to 153 of the counter circuit 15 and outputs 160.
``1'' is placed somewhere in ~167.

These outputs 160 to 167 are OR circuits 170 to 1, respectively.
73, the truth table of the decoder 16 seen from the outputs of the OR circuits 170 to 173 is as shown in FIG.

The outputs of the OR circuits 170-173 drive high voltage transistors 1001-1004 through NAND circuits 210-213, respectively.

In addition, since the strobe pulse S2 is also input to the inputs of the NAND circuits 210 to 213, the OR circuits 170 to 17
The outputs of the NAND circuits 210 to 213 become "0" only when the strobe pulse S2 comes with the output of the NAND circuits 210 to 213 being "1".

Furthermore, only when the outputs of the NAND circuits 210 to 213 become "0", the Tr's 1001 to 1004 each output a high voltage output.

Now, if Tr1001 outputs a high voltage output, that voltage is supplied to resistors R-0 to R-14, and the Tr1001 outputs a high voltage.
If there is a cutoff between 00 and 114, only the intersection will produce an output.

Further, the clock input to the counter circuit 15 comes from an AND circuit 20.

AND circuit 20 and shift pulse S1 and OR circuit 19
The output of the counter circuit 15 serves as an input, and the shift pulse S1 is input as a clock to the counter circuit 15 only when the OR circuit 19 is "1".

As is clear from FIG. 4, this clock is turned on under the following four conditions: Condition 1: When the output 110 of the decoder 11 is "1".

Condition 2...The output 1115 of the decoder 11 is "1"
"When.

Condition 3: When the FF circuit 13 commands up count and the output 1114 of the decoder 11 is "1".

Condition 4: When the FF circuit 13 commands down count and the output 111 of the decoder 11 is "1".

As mentioned above, the clocks are controlled by Tr1001~
This is to change the state of output to 1004.

That is, first, in the strobe pulse S2 immediately after the reset pulse S0, output must be output to the auxiliary electrodes GA-0 and GA-1, so at this time, Tr1
It is necessary to control so that 001 outputs a high voltage.

Next, auxiliary electrodes GA-1 and GA-2, GA-2 and GA
-3, GA-3 and GA-4, . . . The same applies to GA-13 and GA-14.

Further, at this time, the Tr's 1002 to 1004 must be set in this manner.

If you don't do this, you'll end up with output that isn't necessary.

However, the case of auxiliary electrodes GA-14 and GA-15 is different.

At this time, output must be output to Tr 1001 and Tr 1002.

Furthermore, the following state, that is, the auxiliary electrode GA-15 and GA
-16, it is sufficient to output a high voltage only to Tr1002.

In this way, the clock pulse is used to switch the state of which of the transistors 1001 to 1004 outputs the output, and which of the transistors outputs the output.

By inputting the clock pulse as described above,
The output states of Tr 1001 to 1004 change, and FIG. 8 shows the changes in a table.

Moreover, the waveform diagrams 1001 to 1003 in FIG. 5 represent this.

Moreover, GA-0 to GA-16 in FIG. 5 are output waveforms created by combining the above.

As detailed above, the present invention provides two scanning circuits,
A large number of outputs are created by combining the two scanning circuits.

Furthermore, output can be output to two output terminals at the same time.

In addition, a plurality of voltage supply circuits (second
switching element group, voltage source, and second scanning circuit)
and a plurality of short circuits (the first switching element group and the first
(scanning circuit and leg restraint circuit), each short circuit consumes power only when the signal is needed.
The device can be made smaller and cheaper.

In addition, multiple voltage supply circuits do not operate simultaneously; instead, voltage is supplied only to the voltage supply circuit that outputs output, and the other voltage supply circuits do not consume power, so the average power consumption is It becomes less.

In addition, since the scanning direction of the first scanning circuit is configured to be switched every cycle of the scanning operation, the diode matrix can be configured simply and easily, and therefore the number of parts can be reduced, making it compact and inexpensive. It is something that can be done.

[Brief explanation of drawings]

FIG. 1 is a configuration diagram showing an example of a multi-stylus of a solid-state scanning recording device to which the present invention is applied, FIG. 2 is a circuit configuration diagram of a conventional electronic scanning device, and FIG. 3 is for explaining the operation of FIG. 2. FIG. 4 is a circuit configuration diagram of an embodiment of the present invention,
5 is a waveform diagram for explaining the operation of FIG. 4, and FIG. 6 is a truth table for explaining the operation of the force counter circuit 10, decoder 11, and NOR circuits 120 to 1214 shown in FIG.
7 is a truth table for explaining the operations of the counter circuit 15, decoder 16 and OR circuits 17o to 173 in FIG. 4, and FIG. 8 is a truth table for explaining the operations of the auxiliary electrodes GA-0 to GA-3 in FIG.
, is a table for explaining the operations of the counter circuit 15 and Tr 1001 to Tr 1003. 10...Counter circuit, 11...Decoder, 120-12, 4...NOR circuit, 13.
...Flip-flop circuit, 141, 142...
...AND circuit, 15...Counter circuit,
16...Decoder, 170-173...
・OR circuit, 181,182...AND circuit,
19...OR circuit, 20...AND circuit, 210~213...NAND circuit, 100~
114, 1001 to 1004...Transistor, GA-0 to GA-59...Auxiliary electrode.

Claims (1)

[Claims] 1. A first switching element group connected to each terminal of one terminal group of the diode matrix, and a first scanning circuit that sequentially scans two mutually adjacent switching elements of the first switching element group; a control circuit that switches the scanning direction of the first scanning circuit every cycle of the scanning operation; a second switching element group connected to each terminal of the other terminal group of the diode matrix; An electronic scanning device comprising: a voltage source connected to a switching element group; and a second scanning circuit controlling the second switching element group.