JPS5887632A - Microprogram control system - Google Patents

Abstract

(57) [Summary] This bulletin contains application data before electronic filing, so abstract data is not recorded.

Description

DETAILED DESCRIPTION OF THE INVENTION (1) Technical Field of the Invention The present invention relates to a microprogram control system, and particularly to a microprogram control system data processing system having a duplex 5N function in a working system and a standby system and a data transfer function between the working system and a standby system. This article relates to a microprogram control method for mi devices.

(Technical background) In data processing equipment that performs real-time processing, such as the central processing system of an electronic exchange, the impact on users of a functional outage due to a failure or the like is enormous, so cough data processing equipment is One set is operated as the active system, the other is kept as the backup system, and the active system data processing ff
It is well known that when a device stops functioning, a standby data processing device is put into operation to minimize downtime in real-time processing. -10,000 microprogram controller type data processing ffi
In the device 3, a group of microinstructions constituting a microprogram corresponding to each instruction is stored in a predetermined location of the control memory and carved, and when the command is executed, the scissors are used to write the microinstructions at the predetermined location. Necessary microinstructions are sequentially extracted from the control memory and drive the arithmetic unit. The microinstruction is provided with a ridge detection function and is checked for errors each time it is extracted from the control memory.

(3) Prior art and problems In conventional data processing systems of this type, when an error is detected in the microinstruction extracted from the control memory by the active data processing equipment, for example, by parity checking, etc. assumed that a failure had occurred in the bulk data processing device and switched operation to the backup data processing device.Therefore, at the time of switching, there was a considerable period of outage, which hindered real-time processing. It was coming. As a countermeasure, attempts have been made to provide not only error detection but also error correction functions to microinstructions, and to perform sufficient error correction on the microinstructions extracted from the control memory, but this is complicated and expensive. It is necessary to provide the data processing ii* with an error correction circuit, and the time required for executing the microinstructions increases, resulting in a decrease in the economic efficiency and processing capacity of the data processing apparatus.

(4) Object of the Invention The object of the present invention is to eliminate the drawbacks of the conventional microprogram control method as described above, and to do so without significantly reducing the economy and processing capacity of the data processing ffl device (correction of microinstructions). The object of this invention is to realize a microprogram control method that allows real-time processing to continue.

(5) Structure of the Invention The object of the present invention is to provide a microprogram-controlled data processing device that is dually divided into an active system and a standby system and has a data transfer function between the active system and the standby system, in which the active system data processing device has a control memory. When an error is detected in the microinstruction extracted from the microinstruction, execution of the Mukuro microinstruction is stopped,
After holding the storage address of the microinstruction in the control memory, the address is stored in the spare data processor! The armpit backup system data processing device inputs the transferred address into the control memory and transfers the extracted microinstruction to the active system data processing device, and the active system data processing device inputs the transferred address to the control memory. This is achieved by continuing microprogram control from the retained address onward after executing the microinstruction received from the data tin salt device.

(6) Examples of the invention An embodiment of the present invention will be described below with reference to the drawings.

FIG. 1 is a diagram showing a microprogram control system according to an embodiment of the present invention, and FIG. 2 is a diagram showing an example of the operation process in FIG. 181. FIG. 1 shows the active system data processing device ACT and the backup system data processor 111jl18B.
It is stored in the microprogram control section I of Y.

It is assumed that the instructions stored now correspond to a microprogram constituted by a group of microinstructions stored in addresses AO to A4 of the control memory CMI. Each microinstruction (A
O) to (λ4) have the functions shown in FIG. 2(1). The instruction stored in the instruction register IRI is converted into a corresponding microprogram AQ by the microaddress conversion circuit MACI, and input to the control memory CMI via the microprogram sequencer 5EQII. The control memory CMI extracts a microinstruction (AO) from the input address AO and stores it in the microinstruction register CMIRI via the selector 8filL11. −
Universal parity check TGI (PCHKI) inspects the extracted microinstruction (AO) and confirms that there are no ridges.
0 to allow accumulation in microinstruction register CMIRI
A normal microinstruction (AO) controls an arithmetic unit (not shown) and performs a final operation, that is, adds accumulated data (RO) and i<gz> in registers RO and R2, and stores them in register Q. Execute 6. Next, the microprogram sequencer 8EQ1 adds 1f to the address AO to obtain the address Al.
Input to control memo IJcMI 0 control memo IJcMI
extracts the next microinstruction (Al) from the manually entered address AI, and stores it in the microinstruction register CMIRI via the selector 8kiL11J). However, the parity check circuit PCHKI detects an error in the extracted microinstruction (AI), and the microinstruction (AI
) is invalidated in Fig. 2(b)), and the detection holding circuit Pa
Set TTt to error detection state. - Each address AO, AI, etc. input from the microprogram sequencer 8EQl to the control memory CMI is set to the selector 81i1L21.
The address A1 is set in the control memory address register CMARI through the output of the detection holding port @ps'rri which is in the detection state, and is held in the state set at address A1. Further i
The way this detection holding circuit P8TT comes out is that of the fixed address generation circuit V.
AGI is driven to generate a specific address, for example 100.

Cough specific address 100 is micro program sequencer 8E
When input to the control memory CMt via Q1@, the microinstruction (100) is extracted and stored in the instruction register CMIRI via the selector 8FiL11. The microinstruction (100) causes the control memory address register eMA
) The address Al stored in Ll is the shift register 8B.
When the next address 101 is input to the control memory CMl, it is stored via the operation path BSl and the selector 8EL31 and then generated by the microprogram sequencer 8EQ1. (
101) Accumulate in the controller 1iaFRc1 via the operation bus RB81id and the selector 811L31. Furthermore, when the next address 102 generated by the microprogram sequencer 8EQl is input to the control memory IJcMI, the instruction (
102) is extracted and stored in the microinstruction register CM, and the address and command CMD stored in the shift register S and Rx are stored in the standby data processing device 88Y.
0 control memo to start serial transfer in shift register 8FR2! When the microinstruction (103) extracted from address 103 of JCMI confirms the completion of serial transfer to shift register
BY is activated and the control section 8F of the shift register 8FR2
) The fixed address generating circuit VAG2 is driven via the gate G22 which is in a conductive state by the instruction CMD indicating that storage has stopped in LC2, and generates a specific address, for example 200 (l-)◎The I!
#Foot address 200 is micro program sequencer 8BQ
2, the microinstruction (200) is extracted and stored in the microinstruction register CMIR2 via the selector 8BL12. Scissors microinstruction (200) causes shift register 8FR
The address AI stored in the data section 5FRD2 of 2 is
Control memory address register C via selector 8EL22
Transfer to MAR2. Next, when the address AI is input to the control memory CM2 via the microprogram sequencer 8BQ2, the microinstruction (AI) is extracted and stored in the data section 8FRD2 of the shift register 8FR2 via the selector 8BL32. Microinstruction (A1)
is stored in the data record unit 8FRD2, the address 106 is input to the control memory CMI of the active data processing device CT.
The extracted microinstruction (106) is stored in the microinstruction register CMIRI. Mosquito micro-instruction (106)
) starts serial transfer of the instruction (AI) stored in the shift register 8FkL2 of the backup data processing device 8BY to the shift register 8FR1 of the active data processing device ACT @extracted from address 107 of the control memory CMl. Microinstruction (107) is in shift register 8F
After confirming the completion of hinge serial transfer to R1, control memory CM
Microinstruction extracted from address 10g of I (108)
transfers the microinstruction (person l) stored in the data section 8rRDI of the shift register 8FR1 to the address AI stored in the microinstruction register CMIRt via the selector 811L11 to the microprogrammer now sequencer 8FfQ1.
Transfer to 6. The current system data section @
H@ACT performs a predetermined operation, that is, adds data d2 stored in register Q (Qf) and data d2 stored in instruction register RI, stores it in memory address register MAR (not shown), and adds data d2 stored in register Q (not shown) to main memory device (not shown). Address (M.A.
Required data is extracted from R), stored in a memory buffer register MBR (not shown), and executed. On the other hand, the microprogram sequencer 8F)Ql sequentially adds l to the address A1 VIa from the control memory address register CMAR1, and adds the resulting addresses A2 and A3 to the control memory lJcM1j (sequentially, and extracts it when the address A4 is inputted). The microinstruction (A4) stored in the microinstruction register CMIRI is stored in the microinstruction register CMIRI, and a predetermined operation is performed, that is, the data (M&8) stored in the memory buffer register MBH (not shown) is stored in the microinstruction register CMIRI.
MB) is stored in a register R1 (not shown) and executed.

As is clear from the above description, according to this embodiment, when the active data processing ffl device CT detects an error in the microinstruction (A1) extracted from the control memo IJQ company's address A1, the cough microinstruction ( AI) is stopped, transferred to the backup data processing device SBY, and the normal microinstruction (A1) extracted from the control memory CM2 is returned to the active data processing device 88Y. It becomes possible to continue controlling the microprogram from address A2 onwards.

It should be noted that Figures 1 and 2 are merely examples of the present invention, and for example, the microinstructions to be executed and the addresses on the control memos IJCMI and 0M2 are not limited to those shown in the figures. Although many other modifications may be considered, the effects of the present invention remain the same in any case. Further, the configuration of the microprogram control section is not limited to that shown in the drawings, and many other modifications may be considered, but the effects of the present invention will not change in any case.

(7) Effects of the Invention According to the present invention, in the data processing device,
When an error is detected in a microinstruction - By transferring a normal microinstruction from the backup system, there is no need to switch the active system to the backup system (it is possible to continue microprogram control, and the execution of the relevant data processing device is The effect on real-time processing is minimal, and a significant decline in economic efficiency and processing capacity can be prevented.

[Brief explanation of drawings]

FIG. 1 is a diagram showing a microprogram control system according to an embodiment of the present invention, and FIG. 2 is a diagram showing an example of the operation process in FIG. 1. In the figure, ACT is an active data processing device, SBY is a backup data processing device, IRIB and a stage low address conversion circuit, VAGlg and VAG2 are fixed address generation circuits, and 8
EQ1 and 5EQ212 microprogram sequencer, 19EQcTL is sequence control circuit, CMlss
and 0M2 are control memo 1), 8EL11, 5EL21.
5FL31. SgLt2.8BL22 and 5BL32
is a selector, PCHKI and PCHK2 are parity check circuits, PSTTl [and P8TT2 are detection and holding circuits,
CMIRI and CMIR21i microinstruction registers, CMARl and CMAR2 are control memory address registers, Gll, 021% G12 and G22 are gates, R
, BSI and RB 82nd operation/calculation path, 8FR1 and 5FR2 are shift registers, 5FfLD1 and SF
1%D2 is shift register data 5.5FRCI and 5FRC2 are shift register control parts, AO to A4
, ioo to 108 and 200 indicate addresses. Agent: Patent Attorney Koji Matsuoka

Claims (1)

[Claims] In a microprogram control type data processing device which is duplexed into a working system and a standby system and has a data transfer function between the steel structure system and the standby system, the working system data processing ff
When the 1fi controller detects an error in the envy microinstruction extracted from the control memory, it stops executing the microinstruction, retains the control memory upstream storage address of the microinstruction, and then stores the address in the spare data. The backup system data processing device inputs the transferred address to the control memory and transfers the extracted microinstruction to the active system data processing device.
After transferring the microinstruction to the device and the active data processing ffi device executing the microinstruction received from the backup data processing ffl device, the microprogram is designed to continue controlling the microprogram from the address held above. control method.