JPH05189089A - Data processing system - Google Patents

Abstract

PURPOSE:To prevent destruction of necessary data or the like of a peripheral circuit device which is normally operating by applying a hardware reset to a peripheral circuit device, where a fault occurs, by execution of a program in an arithmetic circuit device. CONSTITUTION:When a bit to reset the peripheral circuit device where a fault occurs is stored in a register 1a, a reset signal control circuit 1b resets the peripheral circuit device by the reset signal from the register 1a to perform initialization.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to data processing provided with a plurality of peripheral circuit devices necessary for data processing operations, and an arithmetic circuit device for exchanging data with the peripheral circuit devices and executing an operation by executing a program. More particularly, the present invention relates to a data processing system having a function of resetting hardware to a peripheral circuit device by executing a program of the arithmetic circuit device.

[0002]

2. Description of the Related Art When a data processing system is composed of arithmetic circuit devices such as MCU and CPU capable of program operation and various peripheral circuit devices, the system is initialized at system startup or the peripheral circuit devices are operating during system operation. The reset circuit is necessary to remove the fault that occurs at. Generally, in the data processing system including the arithmetic circuit device and its peripheral circuit device, as shown in FIG.
The system is initialized by a reset signal generated from an external reset circuit (not shown) as shown in FIG. For example, there is initialization of the system by power-on reset when the power is turned on.

FIG. 15 is a block diagram showing a configuration of a conventional data processing system including an arithmetic circuit device and its peripheral circuit device. In FIG. 15, 15a is an MC
Operation circuit devices such as U and CPU, 15b, 15c, 15
d is a peripheral circuit device thereof, 15e is a signal line for transmitting a reset signal generated from an external reset circuit (not shown), and 15f is a peripheral circuit device 15b to 15d (numbered for communication with the arithmetic circuit device 15a). This is an address bus for selecting 0 to n-1).

Next, the operation of this conventional example will be described.
The operation of the case where a failure occurs in the peripheral circuit device 15b during data transfer between the arithmetic circuit device 15a and the peripheral circuit device 15b will be described. Generally, the arithmetic circuit device 1
The peripheral circuit device for 5a is the peripheral circuit device 15 of FIG.
Since there are a plurality of such devices b, 15c, and 15d, the arithmetic circuit device 15a outputs the address on the address bus 15f to select the peripheral circuit device 15b to be the data transfer target. The arithmetic circuit device 15a outputs data to the selected peripheral circuit device 15b.
After that, the arithmetic circuit device 15a waits for a certain period of time until the signal notifying that the peripheral circuit device 15b has received the data is transmitted from the peripheral circuit device 15b. If no signal is sent even after the elapse of the certain period of time, the arithmetic circuit device 15a outputs the data to the peripheral circuit device 15b again and communicates therewith. If the data transfer is not completed even if this operation is performed several times, an error message or the like is displayed in this data processing system, and therefore a reset signal must be generated from the external reset circuit to clear the fault. It was

[0005]

Since the conventional data processing system performs the reset process as described above, when a failure which cannot be recovered by the recovery operation by the arithmetic circuit device occurs in the peripheral circuit device, the entire system is reset by the external reset signal. There is a problem in that it has to be restarted and there is a possibility that necessary data and the like of the peripheral circuit device that is operating normally may be destroyed.

The present invention has been made in order to solve the above problems, and hardware can be reset to a peripheral circuit device in which a failure has occurred by executing a program by an arithmetic circuit device. It is intended to provide a data processing system.

[0007]

According to a first aspect of the present invention, there is provided a data processing system comprising: peripheral circuit devices 3b to 3d for generating a reset signal in the arithmetic circuit device by executing a program by the arithmetic circuit device 3a. A register 1a for storing a plurality of bits corresponding to each of them, a reset signal generated by an external reset circuit and a reset signal output from the register 1a are used as inputs, and in response to the generation of the reset signals, the reset signals One of them is output, and the data processing system or the peripheral circuit device 3 is provided.
The reset signal control circuit 1b for initializing b to 3d is provided in the arithmetic circuit device 3a.

In the data processing system according to the invention of claim 2, the reset signal from the reset signal control circuit 2b and the external input signal for selecting the active polarity of the reset signal are input, and the external input signal is used. A reset signal polarity selection circuit 2c that outputs a selected active polarity reset signal is provided in the arithmetic circuit device 3a.

In the data processing system according to the third aspect of the present invention, the register 7a and the reset signal control circuit 7b are configured so as to simultaneously output the reset signals to the plurality of peripheral circuit devices 3b to 3d.

In the data processing system according to a fourth aspect of the present invention, further, a reset pulse signal generation for outputting a reset signal by writing an instruction for outputting a reset signal to the register 9a by executing a program by the arithmetic circuit device 3a. The means 9b is provided in the arithmetic circuit device 3a.

In the data processing system according to the fifth aspect of the present invention, the program is executed by the arithmetic circuit device 3a to detect the reset signal generated by the reset pulse signal generating means 12b, and the register 12a is reset and reset. The reset stop means 12c for stopping the signal output operation is provided in the arithmetic circuit device 3a.

[0012]

In the invention of claim 1, the register 1a has a plurality of bits corresponding to each of the peripheral circuit devices 3b to 3d for generating a reset signal in the arithmetic circuit device by the execution of the program by the arithmetic circuit device 3a. Store.
The reset signal control circuit 4b receives the reset signal generated by the external reset circuit and the reset signal output from the register 1a, and outputs one of the two reset signals in response to the generation of both reset signals. The system or peripheral circuit devices 3b to 3d are initialized.

In the second aspect of the invention, the reset signal polarity selection circuit 2c receives the reset signal from the reset signal control circuit 2b and an external input signal for selecting the active polarity of the reset signal as an input, and an external input signal. The reset signal of the active polarity selected by is output.

In the invention of claim 3, the register 7a and the reset signal control circuit 7b are composed of a plurality of peripheral circuit devices 3b.
The reset signal is simultaneously output to 3d.

In the invention of claim 4, the reset pulse signal generating means 9b outputs the reset signal by writing a command for outputting the reset signal to the register 9a by executing the program by the arithmetic circuit device 3a.

In the invention of claim 5, the reset stopping means 12c detects the reset signal generated by the reset pulse signal generating means 12b by executing the program by the arithmetic circuit device 3a, resets the register 12a, and resets the reset signal. Stop the output operation of.

[0017]

【Example】

Example 1. FIG. 3 is a block diagram showing the configuration of a data processing system according to an embodiment of the present invention. In FIG. 3, reference numeral 3a denotes an arithmetic circuit device such as MCU or CPU, and 3b to
3d is a peripheral circuit device. The peripheral circuit device 3b is numbered 0, the peripheral circuit device 3c is numbered 1, and the peripheral circuit device 3d is numbered n-1. Reference numeral 3e is an input signal line for transmitting an external reset signal from an external reset circuit (not shown) to the arithmetic circuit device 3a, and 3f is a reset signal output from the arithmetic circuit device 3a.
A reset bus 3g for transmitting to d is an address bus for selecting a peripheral circuit device with which the arithmetic circuit device 3a communicates.

FIG. 1 is a block diagram showing a configuration of a reset signal output means which is a feature of an arithmetic circuit device according to an embodiment of the present invention. In FIG. 1, reference numeral 1a is a register for storing a plurality of bits corresponding to each of peripheral circuit devices for generating a reset signal in the arithmetic circuit device by executing a program by the arithmetic circuit device. 1b
Is a reset signal generated by an external reset circuit (not shown) and a reset signal output from the register 1a, and outputs one of the reset signals in response to the generation of both reset signals. It is a reset signal control circuit for initializing.
Reference numeral 1c is a signal line from bit 0 to bit n-1 of the register 1a for transmitting the output signal of the register 1a to the reset signal control circuit 1b, and 1d is an input signal line for inputting an external reset signal 1e. Is an output signal line for outputting a reset signal, and 1f is an input signal line for a reset signal to the register 1a.

FIG. 4 is a circuit diagram of the reset signal output means in the arithmetic circuit device of FIG. This arithmetic circuit device is
A reset signal output means including a register 4a and a reset signal control circuit 4b is built-in, and a program is executed to reset hardware for a peripheral circuit device in which an unrecoverable failure has occurred in a retry operation. To enable that. The register 4a stores n bits for generating a reset signal to the n peripheral circuit devices by executing the program by this arithmetic circuit device. The reset signal control circuit 4b includes the register 4
It is composed of n AND gates 41 to which the reset signal of the signal line 4d of a and the external reset signal from the input signal line 4e are input and which outputs one of them in response to the generation of the both reset signals. 4c is an n for writing data in the register 4a by executing a program by the arithmetic circuit unit.
A bit data bus, 4d is a signal line for transmitting the output signal of the register 4a to one input of the AND gate 41, and 4e is an external reset signal for transmitting the external reset signal to the other input of the AND gate 41 and the reset terminal of the register 4a. Signal lines 4f for transmitting the reset signals from the n AND gates 41 to the n peripheral circuit devices, respectively.

FIG. 5 shows the reset of FIG. 4 from the time of power-on to the occurrence of an unrecoverable fault in the peripheral circuit device in the data processing system of FIG. 3 composed of the arithmetic circuit device and n peripheral circuit devices. It is a time chart figure which shows the operation state of a signal output means. In FIG. 5, the R signal is an external reset signal of the signal line 4e in FIG. 4, b ₀ , b ₁ , b
_{The n-1} signal is the data signal of the data bus 4c, R ₀ , R ₁ , R
_{The n-1} signal is the NAD gate 4 of the reset signal control circuit 4b.
It is a reset signal output from 1.

Next, the operation of this embodiment will be described with reference to FIGS. The operation after the power is turned on will be described below. When the power of the data processing system is turned on, the R signal of the signal line 4e becomes active (time a), and each bit of the register 4a is set to a high level (hereinafter referred to as H level). As a result, an H level reset signal is input to one input terminal of the AND gate 41 of the reset signal control circuit 4b, and a low level (hereinafter referred to as L level) reset signal is input to the other input terminal. Therefore, the output signal of the AND gate 41 (R ₀ signal,
R ₁ signal, R _n-1 signal), n peripheral circuit devices 3
b, 3c and 3d are initialized and the data processing system starts to operate normally.

Now, the arithmetic circuit unit 3a is replaced by the address bus 3g.
The address is output above, and the number 0 is targeted for data transfer.
A case will be described in which the peripheral circuit device 3b is selected, and an unrecoverable failure occurs in this peripheral circuit device 3b. The arithmetic circuit device 3a outputs data to the peripheral circuit device 3b. After that, the arithmetic circuit device 3a waits for a certain period of time until the signal notifying that the peripheral circuit device 3b has received the data is transmitted from the peripheral circuit device 3b. When the signal is not transmitted even after the elapse of the fixed period of time, the arithmetic circuit device 3a outputs the data to the peripheral circuit device 3b again and communicates therewith. If the data transfer is not completed even if this operation is repeated several times, the self-diagnosis function of the arithmetic circuit device 3a determines that fact, and the arithmetic circuit device 3a executes the program and registers via the data bus 4c. Four
An L level signal is written to bit 0 (b ₀ ) of a, an H level signal is subsequently written, and a reset signal (R ₀ signal) is output (time b). Only the peripheral circuit device 3b in which the failure has occurred is initialized by the R ₀ signal and the failure is released. Further, since the peripheral circuit devices 3c and 3d in which no failure has occurred are not reset, data and the like are not destroyed.

Example 2. FIG. 2 is a block diagram showing a configuration of a reset signal output means which is a feature of the arithmetic circuit device according to the second embodiment of the invention. In addition to the register 2a and the reset signal control circuit 2b, this arithmetic circuit device receives a reset signal from the reset signal control circuit 2b and an active polarity selection signal (external input signal) for selecting the active polarity of the reset signal. It further includes a reset signal polarity selection circuit 2c which receives an input and outputs a reset signal having an active polarity selected by the active polarity selection signal. 2d is bit 0 of register 2a
Output signal line of bit n−1, 2e is an input signal line for an external reset signal, 2f is an input signal line for a reset signal to the reset signal polarity selection circuit 2c, 2g is an input signal line for the active polarity selection signal, 2h Is a reset signal output signal line.

FIG. 6 is a circuit diagram showing an example of the reset signal polarity selection circuit shown in FIG. In FIG. 6, 6a is a signal line for transmitting the reset signal (R ₀ signal) which is the output of the reset signal control circuit 4b (see FIG. 4), and 6b is the active polarity of the reset signal (R ₀ signal). Active polarity selection signal (external input signal) SEL for
For transmitting the active polarity selection signal SE
An inverter that controls the reset signal output from the AND gates 6e and 6f according to the level of L, and 6d is a reset signal R ₀ that is the output of the reset signal control circuit 4b.
An inverter that inverts the reset signal to generate a reset signal having a positive active polarity, and 6e is the reset signal control circuit 4b.
Is an AND gate that outputs a reset signal with a negative active polarity, 6f is an AND gate that outputs a reset signal with a positive active polarity, and 6g is an AND gate 6
O that takes the logical sum of the reset signals output from e and 6f
It is an R gate.

In the data processing system shown in FIG. 3, there are two types of polarities of the reset signal to the peripheral circuit devices 3b to 3d, that is, the L level and the H level. The reset signal polarity selection circuit shown in FIG. You can choose. That is, in the arithmetic circuit device having the reset signal output means (register 2a, reset signal control circuit 2b, and reset signal polarity selection circuit 2c) as shown in FIG. 2, the level of the active polarity selection signal SEL shown in FIG. 6 is set in advance. By setting to H level or L level, it becomes possible to output a reset signal according to the active polarity of the reset signal to the peripheral circuit devices 3b to 3d.

Example 3. In the data processing system of FIG. 3 including the arithmetic circuit device having the reset signal output means shown in FIG. 4 and the peripheral circuit device, the peripheral circuit device is operating when the power consumption is smaller at the time of reset than at the time of operation. When the peripheral circuit devices 3b and 3c are not used, the register 4a in the reset signal output means of FIG.
The L level is written to the bit 0 (b ₀ ) and the bit 1 (b ₁ ) and the reset signal to the peripheral circuit devices 3b and 3c corresponding to each bit is output and the power consumption of the entire system is saved. can do.

Example 4. FIG. 7 is a circuit diagram of a reset signal output means for outputting a reset signal by software in an embodiment according to the invention of claim 3. In FIG.
Reference numeral 7a is a register having a function of outputting a reset signal to all peripheral circuit devices, and 7b is a reset signal control circuit for controlling the reset signal output by the output signal of the register 7a or the like. The reset signal control circuit 7b is composed of n AND gates 71.

FIG. 8 is a timing chart showing the operation of the reset signal output means of FIG. The reset signal output means of FIG. 7 can reset all peripheral circuit devices at the same time by setting the b _a signal in the b _a bit of the register 7 _a by software.

Example 5. FIG. 10 shows an embodiment of the reset signal output means having the reset pulse signal generation means shown in FIG. 9 (an embodiment according to the invention of claim 4). In FIG. 10, 10b, 10c and 10d correspond to the reset pulse signal generating means. As shown in the time chart (FIG. 11) of the reset signal output means, the arithmetic circuit device sends data to the reset pulse signal generating instruction register 10a (b at time t = a in the time chart (FIG. 11)).
By writing ₀ (D ₀ ) signal, it becomes possible to generate reset pulse signals R ₀ ″ and R ₀ in the peripheral circuit device in which the failure has occurred. In designing a data processing system such as a microcomputer, The weight of hardware and software becomes a problem.This reset signal output means can reduce hardware.

Example 6. FIG. 13 shows an embodiment of the reset signal output means according to the invention of claim 5, which has means for detecting the reset pulse signal shown in FIG. 12 and resetting the reset pulse generating instruction register. In FIG.
13c detects the reset pulse signal and resets the reset pulse generating instruction register 13a, that is,
It corresponds to reset stop means for stopping the output operation of the reset signal. As shown in the time chart (FIG. 14) of the reset signal output means, the arithmetic circuit device writes the data in the reset pulse generating instruction register 13a (time t = a b in the time chart (FIG. 14)).
₀ , D ₀ signal), and a reset pulse signal R ₀ is generated in the peripheral circuit device in which the failure has occurred. Reset stop means 13c
Detects the rising edge of this reset pulse signal (time t = b), generates a reset pulse signal, and resets the reset pulse signal generation instruction register 13a. However, in this embodiment, the register 13a is set by the reset signals R and R '''. This reset signal output means can reduce the weight of software.

[0031]

As described above, according to the invention of claim 1,
A register for storing a plurality of bits corresponding to each of the peripheral circuit devices for generating a reset signal in the arithmetic circuit device by executing the program by the arithmetic circuit device, and a reset signal and a register generated by an external reset circuit. Provided in the arithmetic circuit device is a reset signal control circuit that receives the output reset signal as an input, outputs one of the two reset signals in response to the generation of both reset signals, and initializes the data processing system or the peripheral circuit device. Since it is configured as described above, it is possible to reset the hardware for the peripheral circuit device in which the failure has occurred, and it is possible to obtain the effect that the necessary data of the peripheral circuit device that is operating normally does not have to be destroyed. .. Also, if the power consumption of the peripheral circuit device is less at reset than at operation,
By setting the reset signal to the output state to the peripheral circuit device which is not used during the operation of the system, it is possible to reduce the power consumption of the entire system.

According to the second aspect of the present invention, the reset signal from the reset signal control circuit and the external input signal for selecting the active polarity of the reset signal are input, and the active polarity selected by the external input signal is input. Since the reset signal polarity selection circuit for outputting the reset signal is provided in the arithmetic circuit device, a reset signal corresponding to the active polarity of the reset signal to the peripheral circuit device can be output, and the above effect can be easily achieved.

According to the third aspect of the present invention, the register and the reset signal control circuit are configured to output the reset signal to the plurality of peripheral circuit devices at the same time. Therefore, it is desired to reset the peripheral circuit devices at the same time. In this case, it is effective, and the above effects can be achieved.

According to the fourth aspect of the invention, the arithmetic circuit device further includes reset pulse signal generating means for outputting a reset signal by writing a command for outputting the reset signal to the register by executing the program by the arithmetic circuit device. Since it is provided, the hardware reset signal can be output by software, and the same effect as described above can be obtained.

According to the invention of claim 5, reset pulse signal generating means for outputting a reset signal by writing a command for outputting a reset signal to the register by executing the program by the arithmetic circuit device is further provided, and further, the arithmetic operation By executing the program by the circuit device, the reset signal generated by the reset pulse signal generating means is detected,
Since the arithmetic circuit unit is provided with the reset stopping means for resetting the register and stopping the output operation of the reset signal, it can be effectively used in the case of the processing for stopping the reset operation, and the same effect as the above can be obtained. Be done.

[Brief description of drawings]

FIG. 1 is a block diagram showing a configuration of a reset signal output means which is a feature of an arithmetic circuit device according to an embodiment of the present invention.

FIG. 2 is a block diagram showing a configuration of a reset signal output means which is a feature of an arithmetic circuit device according to an embodiment of the invention of claim 2;

FIG. 3 is a block diagram showing an overall configuration of a data processing device according to an embodiment of the present invention.

FIG. 4 is a circuit diagram of a reset signal output unit that is a feature of the arithmetic circuit device of FIG.

5 is a time chart showing the operation of the circuit of FIG.

FIG. 6 is a circuit diagram showing an example of a reset signal polarity selection circuit in FIG.

FIG. 7 is a block diagram showing a configuration of a reset signal output means which is a feature of the arithmetic circuit device according to the invention of claim 3;

FIG. 8 is a time chart showing the operation of the circuit of FIG.

FIG. 9 is a block diagram showing a configuration of a reset signal output means which is a feature of an arithmetic circuit device according to an embodiment of the invention of claim 4;

FIG. 10 is a circuit diagram including a circuit of reset pulse signal generating means in FIG.

11 is a time chart showing the operation of the circuit of FIG.

FIG. 12 is a block diagram showing a configuration of a reset signal output means which is a feature of an arithmetic circuit device according to an embodiment of the invention of claim 5;

13 is a circuit diagram of the reset signal output means of FIG.

FIG. 14 is a time chart showing the operation of the circuit of FIG.

FIG. 15 is a block diagram showing a configuration of a conventional data processing system.

[Explanation of symbols]

1a, 2a, 4a, 7a, 9a, 10a, 12a, 13
a register 1b, 2b, 4b, 7b, 9c, 10e, 12d, 13
d reset signal control circuit 2c reset signal polarity selection circuit 9b, 12b, 13b reset pulse signal generation means 12c, 13c reset stop means

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[Procedure amendment]

[Submission date] July 31, 1992

[Procedure Amendment 1]

[Document name to be amended] Statement

[Name of item to be amended] Claims

[Correction method] Change

[Correction content]

[Claims]

[Procedure Amendment 2]

[Document name to be amended] Statement

[Correction target item name] 0009

[Correction method] Change

[Correction content]

In the data processing system according to the third aspect of the present invention, further, by executing the program of the arithmetic circuit device, it is possible to register a bit that enables a reset signal to be simultaneously output to the plurality of peripheral circuit devices 3b to 3d. Prepared for 7a
It is a gift .

[Procedure 3]

[Document name to be amended] Statement

[Correction target item name] 0011

[Correction method] Change

[Correction content]

In the data processing system according to the fifth aspect of the present invention, the program is executed by the arithmetic circuit device 3a to detect the reset signal generated by the reset pulse signal generating means 12b, and the register 12a is reset and reset. The reset stop means 12c for completing a series of operations for generating a signal is provided in the arithmetic circuit device 3a.

[Procedure amendment 4]

[Document name to be amended] Statement

[Correction target item name] 0014

[Correction method] Change

[Correction content]

In the third aspect of the invention, the register 7a and the reset signal control circuit 7b are provided by the arithmetic circuit unit 3a.
When the program is executed, the bit ba of register 7a
By writing the data into the plurality of peripheral circuit devices 3b to 3b.
A reset signal can be simultaneously output to d .

[Procedure Amendment 5]

[Document name to be amended] Statement

[Correction target item name] 0016

[Correction method] Change

[Correction content]

In the invention of claim 5, the reset stopping means 12c detects the reset signal generated by the reset pulse signal generating means 12b by executing the program by the arithmetic circuit device 3a, resets the register 12a, and resets the reset signal. To complete a series of operations that generate

[Procedure correction 6]

[Document name to be amended] Statement

[Name of item to be corrected] 0027

[Correction method] Change

[Correction content]

Example 4. FIG. 7 shows an embodiment according to the invention of claim 3, in which all peripheral circuits are executed by executing the program of the arithmetic circuit.
(B) that can output a reset signal to
FIG. 7A is a circuit diagram of a reset signal output means included in the register 7a . In FIG. 7, reference numeral 7a denotes an arithmetic circuit device.
A register having a bit (ba) for outputting a reset signal to all peripheral circuit devices at the same time by executing a program , 7
The reset signal control circuit controls a reset signal output by the output signal of the b register 7a or the like. The reset signal control circuit 7b is composed of n AND gates 71.

[Procedure Amendment 7]

[Document name to be amended] Statement

[Name of item to be corrected] 0030

[Correction method] Change

[Correction content]

Example 6. FIG. 13 shows an embodiment of the reset signal output means according to the invention of claim 5, which has means for detecting the reset pulse signal shown in FIG. 12 and resetting the reset pulse generating instruction register. In FIG.
13c detects the reset pulse signal and resets the reset pulse generating instruction register 13a, that is,
It corresponds to a reset stop means for completing a series of operations for outputting a reset signal. As shown in the time chart (FIG. 14) of the reset signal output means, the arithmetic circuit device writes the data in the reset pulse generating instruction register 13a (time t = a b in the time chart (FIG. 14)). ₀ , D ₀ signal), and a reset pulse signal R ₀ is generated in the peripheral circuit device in which the failure has occurred. The reset stop means 13c detects the rising edge of the reset pulse signal (time t = b), generates a reset pulse signal, and resets the reset pulse signal generation instruction register 13a. However, in this embodiment, the register 13a is set by the reset signals R and R '''. This reset signal output means can reduce the weight of software.

[Procedure Amendment 8]

[Document name to be amended] Statement

[Correction target item name] 0035

[Correction method] Change

[Correction content]

[0035] According to the invention of claim 5, and a reset pulse signal generating means for outputting a reset signal by writing an instruction for outputting a reset signal to the register by executing programs by the arithmetic circuit unit provided in further, Lycee
Detects Tsu preparative pulse signal generating reset signal generated from the means to reset the register, of generating a reset signal
Since the reset stop means for completing the series of operations is provided in the arithmetic circuit device, the reset signal is generated.
A series of operations that need to be completed programmatically
The same effect with Kunar also obtained.

Claims (5)

[Claims] 1. A data processing system comprising: a plurality of peripheral circuit devices necessary for data processing operation; and an arithmetic circuit device for exchanging data with the peripheral circuit device and executing a program to execute an operation. A register for storing a plurality of bits corresponding to each of the peripheral circuit devices for generating a reset signal in the arithmetic circuit device by executing a program by the circuit device, a reset signal generated by an external reset circuit, and the register A reset signal control circuit for inputting a reset signal output from the data processing device, outputting one of the reset signals according to the generation of the reset signals, and initializing the data processing system or the peripheral circuit device. A data processing system provided in an arithmetic circuit device. 2. A data processing system comprising: a plurality of peripheral circuit devices necessary for data processing operation; and an arithmetic circuit device for exchanging data with the peripheral circuit device and performing an operation by executing a program. A register for storing a plurality of bits corresponding to each of the peripheral circuit devices for generating a reset signal in the arithmetic circuit device by executing a program by the circuit device, a reset signal generated by an external reset circuit, and the register And a reset signal control circuit for inputting the reset signal output from the above and outputting one of the reset signals in response to the generation of the reset signals and for initializing the data processing system or the peripheral circuit device. , The reset signal from the reset signal control circuit and the active polarity of the reset signal And a reset signal polarity selection circuit for inputting an external input signal for selecting, and outputting a reset signal of the active polarity selected by the external input signal, in the arithmetic circuit device. .. 3. A data processing system comprising: a plurality of peripheral circuit devices necessary for data processing operation; and an arithmetic circuit device for exchanging data with the peripheral circuit device and executing a program to execute an arithmetic operation. A register for storing a plurality of bits corresponding to each of the peripheral circuit devices for generating a reset signal in the arithmetic circuit device by executing a program by the circuit device, a reset signal generated by an external reset circuit, and the register And a reset signal control circuit for inputting the reset signal output from the above and outputting one of the reset signals in response to the generation of the reset signals and for initializing the data processing system or the peripheral circuit device. , The register and the reset signal control are executed by executing the program by the arithmetic circuit device. A data processing system, wherein the control circuit is configured to simultaneously output a reset signal to the plurality of peripheral circuit devices. 4. A data processing system comprising: a plurality of peripheral circuit devices necessary for data processing operations; and an arithmetic circuit device for exchanging data with the peripheral circuit devices and executing a program to execute an operation. A register for storing a plurality of bits corresponding to each of the peripheral circuit devices for generating a reset signal in the arithmetic circuit device by executing a program by the circuit device, a reset signal generated by an external reset circuit, and the register And a reset signal control circuit for inputting the reset signal output from the above and outputting one of the reset signals in response to the generation of the reset signals and for initializing the data processing system or the peripheral circuit device. Furthermore, the execution of the program by the arithmetic circuit device causes a reset signal to the register. A data processing system, characterized in that reset pulse signal generating means for outputting a reset signal by writing a command for outputting is provided in the arithmetic circuit device. 5. A data processing system comprising: a plurality of peripheral circuit devices necessary for data processing operation; and an arithmetic circuit device for exchanging data with the peripheral circuit device and executing a program to execute an arithmetic operation. A register for storing a plurality of bits corresponding to each of the peripheral circuit devices for generating a reset signal in the arithmetic circuit device by executing a program by the circuit device, a reset signal generated by an external reset circuit, and the register A reset signal control circuit for inputting a reset signal output from the above and outputting one of the reset signals in response to the generation of the reset signals to initialize the data processing system or the peripheral circuit device; An instruction to output a reset signal to the above register by executing a program by the arithmetic circuit unit By providing a reset pulse signal generating means for outputting a reset signal by writing, further, by executing the program by the arithmetic circuit device,
A data processing system, wherein the arithmetic circuit device is provided with reset stop means for detecting a reset signal generated by the reset pulse signal generating means, resetting the register, and stopping the output operation of the reset signal.