JPS5890877A - Video copy timing signal generating circuit - Google Patents

Abstract

PURPOSE:To avoid shift of the position of timing in sampling a picture signal, by generating a video copy timing based on a horizontal synchronizing signal at the 2nd and succeeding, after a vertial synchronizing signal. CONSTITUTION:A negative synchronizing signal S1 including equivalent pulse inputted from a terminal T1 is integrated at a circuit comprising a resistor R1 and a capacitor C1 and outputted to a counter of a microcomputer and a clear terminal CLR of a flip-flop 12 via a transistor (TR)TR1 and an inverter 11. Further, the synchronizing signal S1 is amplified at a TR2, integrated at a resistor R5 and a capacitor C2 and inputted to a switching signal for a TR3. The output of the TR3 is sequentially inputted to flip-flop circuits 12, 13, 14 and a video copy timing signal based on the 2nd and succeeding horizontal synchronizing signals after the vertical synchronizing signal of the composite sunchronizing signal S1 indlucing equivalent pulses is outputted from an NAND circuit 15.

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a video copying apparatus that samples a video signal corresponding to a still image displayed on a cathode ray tube and prints the sampled data. In particular, the present invention relates to a video copy timing signal generation circuit that outputs a video copy timing signal to a video signal sampling circuit of this video copy apparatus.

In this type of video signal sampling circuit, as shown in FIG. 1, a sampling position in the vertical direction is specified based on a vertical synchronization signal, and a sampling position in the horizontal direction is specified based on a horizontal synchronization signal. As a result, the video SPG is sampled at an arbitrary pixel position, and the sampled data is sequentially stored in a data buffer with a memory capacity corresponding to the number of pixels on seven vertical axes or a plurality of vertical axes. FIG. 2 is a circuit diagram of this video signal sampling circuit. / is a counter that outputs a signal HP representing the pixel position on the horizontal scanning line to be sampled, and its contents are updated, for example, by incremental signals H, INC applied each time / completes scanning of the vertical axis. This counter takes in the output signal HP of / at the generation timing of the video copy timing signal based on the horizontal synchronization signal, and then counts the pixel signal DOT (pulse corresponding to the / pixel) and samples its carry output during horizontal scanning. This is a preset counter that outputs a timing signal TM corresponding to a pixel position on a line in each horizontal scanning period. 3, the video signal V is generated by the timing signal TM output from this preset caran tacho.
This is a shift register that takes in D and outputs it to the data buffer as sampling data SD.

By the way, in the case of a television receiver, unlike in the case of a cathode ray tube display device such as a personal computer, since it is an interlaced system, the equivalent pulse in the synchronization signal is /H (H :
(horizontal scanning period). For this reason,
When sampling image signals corresponding to still images displayed on the CRT of a television receiver,
A video copy timing signal applied to a preset counter of the video signal sampling circuit is generated based on the equivalent pulse before generated based on the horizontal synchronization signal. Therefore, for example, if you are sampling the screen sequentially from the left edge to the right (then the left half of the screen will be sampled normally, but the right half of the screen will be sampled by the equivalent pulse that exists between the first horizontal sync signal after the vertical sync signal). If the sampling position is shifted by the number of samples, and this is printed, the right half will be shifted downward as shown in FIG.

The present invention solves the above-mentioned drawbacks, namely, a video copy timing signal generation circuit that prevents the phenomenon that the sampling position shifts from the center of the screen due to equivalent pulses when sampling the image signal of a television receiver. Our goal is to provide the following.

In order to achieve such an object, a video copy timing signal generation circuit of the present invention includes a synchronization signal integration circuit, a circuit that switches the output of this integration circuit at a predetermined threshold level, and a plurality of flip-flops. The video copy timing signal is composed of a loop and a NAND circuit, and generates a video copy timing signal based on the first and subsequent horizontal synchronization signals after the vertical synchronization signal, and outputs it to the video signal sampling circuit.

The present invention will be described below with reference to the drawings.

FIG. S is a circuit diagram showing a video copy timing signal generation circuit according to an embodiment of the present invention. Terminal T is a synchronization signal S separated by a synchronization signal separation circuit.

is input to the transistor TR via the resistor R1.
A transistor TR is connected to the base of 1 through a resistor.

and to the power supply element B, respectively. A capacitor C2 and a resistor - are grounded between the resistor and the base of the transistor TR. The circuit consisting of the resistor and capacitor C2 is an integrating circuit for the synchronizing signal S. Power supply element B1, resistor R2, resistor R5, transistor TR
, is a circuit that integrates the synchronizing signal S, and then amplifies it. // is an inverter that integrates the synchronizing signal S1 and inverts the amplified signal, and outputs the signal S2 from the clear terminal CLR of flip-flop /2 and the terminal T2 to a microcomputer (not shown) which is the main control unit of the video copying device. Output to counter. Resistor R4 is a transistor TR.

Limit the base current applied to the Further, the synchronization signal S1 is amplified by the transistor TR, and then is amplified by the transistor TR,
The signal is integrated by an integrating circuit connected between the collector of the transistor TR and the base of the transistor TR, that is, a grounded resistor R3 and a capacitor C2. For resistors, the impedance between the capacitor fC and the base of the transistor TR8 is increased. The transistor TR performs a switching operation by the signal S after it has passed through the resistor, and outputs the signal S4 to the clock pulse input terminal Ck of the first flip-flop/2 and the data input terminal of the first flip-flop/3. to be applied. The resistor R7 is a resistor for operating the transistor TR8. 10B2 is transistor TR2
At the same time as the transistor TR3 is operated, the level at which the transistor TR, together with the resistor R6 and the resistor R7, performs the switching operation, that is, the threshold
This is the power supply that sets the level. /2. /3. /ll are a first flip-flop, a second flip-flop, and a third flip-flop, all of which operate at negative logic. The data input terminal of the first flip-flop/2 and the preset terminal PR, the second flip-flop/3
The preset terminal PR1 and the clear terminal CLR of the third flip-flop /1 are both connected to the power source B2 and are always at a high level. 1st
The clock pulse input terminal Ck of the flip-flop saw
, the signal S switched by the transistor TR8 is
4 is input, and the signal S, which is obtained by integrating and amplifying the synchronizing signal S, is input to the clear terminal CLH, and the signal S is output from the output terminal Q to the clear terminal CLR of the first flip-flop /3. be done. First flip-flop/
A signal S4 switched by the transistor TR3 is input to the data input terminal No. 3, and a clock pulse of, for example, 20 MHz is input from an oscillation circuit (not shown) to the clock pulse input terminal Ck via the input terminal T3. This second flip-flop /3 has its inverting output terminal Q
The output signal S is outputted to the data input terminal of the third flip-flop /l and to the NAND game 15. Third
The output signal S from the inverting output terminal Q of the first flip-flop 3 is connected to the data input terminal of the flip-flop /l.
, is input to the clock pulse input terminal Ck, and a clock pulse of <20 MH2, which is the same as that of the second flip-flop, is input from the input terminal T, and its inverted output terminal Q
A signal S is output from the NAND game) 15. The Nant gate 15 converts the signal S into a second signal based on the output signal S6 from the inverting output terminal Q of the second flip-flop /3 and the output signal S7 from the inverting output terminal Q of the third flip-flop /4'. It is output to the brisset caran tacho of the video signal sampling circuit shown in the figure.

Next, the operation of the circuit shown in FIG. S will be explained based on the waveform diagram shown in FIG. A negative synchronizing signal S, which is input from the terminal T1 and includes an equivalent pulse, is connected to the resistor R1 and the capacitor C1.
The signal S, which is integrated by the circuit consisting of the transistor TR1, is amplified by the transistor TR1, and inverted by the inverter //, is sent to the terminal T.
2 to the microcomputer counter and the clear terminal CLH of flip-flop/2. Similarly, the synchronizing signal S1 is amplified by a transistor TR, and then amplified by a resistor and a capacitor C! The signal S is integrated by a circuit consisting of
, becomes. After passing through the resistor -, the signal S3 is switched by the transistor TR. That is, the pulse rises when the signal S becomes less than the threshold voltage "fh" and falls when the signal S becomes more than the threshold voltage "fh".

First flip-flop/2. The output signal S from the output terminal Q of is initially in the initial state of 1/@, and the output signal S from the output terminal Q of
At the fall of the LH input signal S, @/@ is inverted to 10", and then regardless of the clock pulse input terminal, "/
The output signal S6 from the inverting output terminal Q of the flip-flop/3 is initially in the initial state of "0", and becomes l at the fall of the input signal S at the data input terminal.
The signal is inverted from IO'' to /1, and thereafter falls and rises repeatedly in response to the rises and falls of the input signal S4.

However, the timing of the rise and fall of the output signal S6 is shifted by the timing of the 20MH2 clock pulse. The output signal S7 from the inverting output terminal 4 of the third flip-flop /lI has an opposite relationship to the input signal S6 from the data input terminal, being shifted by the timing of the 20 MHz clock pulse.

When the output signal S6 of the third flip-flop /3 and the output signal S of the third flip-flop /lI, which are input signals, are both 101, the Nant gate /S performs a video copy of the negative pulse output signal S. It is output as a timing signal to the brisset caran tacho of the video signal sampling circuit shown in FIG. As a result, it is possible to generate a video copy timing signal based on the second and subsequent horizontal synchronization signals after the vertical synchronization signal of the decoded synchronization signal S including the equivalent pulse.

As explained above, the present invention generates a video copy timing signal based on the horizontal synchronization signal after the vertical synchronization signal, so that the synchronization signal includes an equivalent pulse due to the interlace method. This has the effect that the sampling position does not shift when sampling the image signal of the television receiver.

[Brief explanation of drawings]

Figure 1 is an explanatory diagram of the video signal sampling operation, Figure 2 is a circuit diagram of the video signal sampling circuit, Figure 3 is a waveform diagram of the synchronization signal of a cathode ray tube display device such as a personal computer, and Figure 4. 1 is a diagram of a conventional video copy timing signal generation circuit sampling and printing an image signal of a television receiver, and FIG. S is a circuit diagram of an embodiment of a video copy timing signal generation circuit according to the present invention. Figure 6 is the waveform diagram. S, ...Composite synchronization signal. /2...First flip-flop. /3...The first flip-flop. /G...Third flip-flop. /S...Nand circuit. S8: Video copy timing signal. Figure 1 Figure 3 Flash 1114

Claims (1)

[Claims] A counter that outputs a signal representing a pixel position on a horizontal scanning line to be sampled; the output signal of the counter is taken in at the timing of generation of a horizontal synchronization signal; after that, the pixel signal is counted; A preset counter outputs a timing signal corresponding to a pixel position on a horizontal scanning line to be sampled, and a composite video signal is sampled using the evening/timing signal outputted from the preset counter, and the unit of screen vertical period is sampled as sampling data. a video signal sampling circuit for the composite video signal displayed on the screen, which includes a shift register that outputs the signal to the data buffer; and a video copy timing signal that outputs the output signal of the counter to the preset counter at the timing of generation of the horizontal synchronization signal. a video copy timing signal generation circuit that prints the contents of the data buffer, a printing mechanism that prints the contents of the data buffer, and a main control section that controls the video signal recording circuit, the video copy timing signal generation circuit, and the printing mechanism. A first integrating circuit that outputs a vertical periodic signal representing a vertical scanning period by integrating a composite synchronization signal, and a second integrating circuit that outputs a horizontal periodic signal representing a horizontal scanning period by integrating the composite periodic signal. a switching circuit that outputs a continuous λ value signal that is inverted once per horizontal scanning period in response to the horizontal periodic signal; The reception of the λ value signal is made possible only during the vertical scanning period by the application of the signal, and this reception delays the input λ value signal by the clock period of the clock pulse and a circuit that creates an inverted λ value signal having an opposite phase to the λ value signal by inverting the signal, and outputs the inverted λ value signal and the accepted λ value signal; and both signals output from this circuit. a gate circuit for applying a pulse signal obtained by performing a logical product to the preset counter as the video copy timing signal.