JPS5892230A - 半導体装置 - Google Patents

半導体装置

Info

Publication number
JPS5892230A
JPS5892230A JP56191171A JP19117181A JPS5892230A JP S5892230 A JPS5892230 A JP S5892230A JP 56191171 A JP56191171 A JP 56191171A JP 19117181 A JP19117181 A JP 19117181A JP S5892230 A JPS5892230 A JP S5892230A
Authority
JP
Japan
Prior art keywords
semiconductor substrates
substrates
gold wires
pads
main surfaces
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
JP56191171A
Other languages
English (en)
Other versions
JPS6347259B2 (ja
Inventor
Hidenobu Ishikura
石倉　秀信
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Mitsubishi Electric Corp
Original Assignee
Mitsubishi Electric Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Mitsubishi Electric Corp filed Critical Mitsubishi Electric Corp
Priority to JP56191171A priority Critical patent/JPS5892230A/ja
Publication of JPS5892230A publication Critical patent/JPS5892230A/ja
Publication of JPS6347259B2 publication Critical patent/JPS6347259B2/ja
Granted legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W90/00—Package configurations
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W70/00—Package substrates; Interposers; Redistribution layers [RDL]
    • H10W70/60—Insulating or insulated package substrates; Interposers; Redistribution layers
    • H10W70/67—Insulating or insulated package substrates; Interposers; Redistribution layers characterised by their insulating layers or insulating parts
    • H10W70/68—Shapes or dispositions thereof
    • H10W70/682—Shapes or dispositions thereof comprising holes having chips therein
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W72/00—Interconnections or connectors in packages
    • H10W72/071—Connecting or disconnecting
    • H10W72/072—Connecting or disconnecting of bump connectors
    • H10W72/07231—Techniques
    • H10W72/07236—Soldering or alloying
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W72/00—Interconnections or connectors in packages
    • H10W72/071—Connecting or disconnecting
    • H10W72/075—Connecting or disconnecting of bond wires
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W72/00—Interconnections or connectors in packages
    • H10W72/071—Connecting or disconnecting
    • H10W72/075—Connecting or disconnecting of bond wires
    • H10W72/07551—Connecting or disconnecting of bond wires characterised by changes in properties of the bond wires during the connecting
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W72/00—Interconnections or connectors in packages
    • H10W72/071—Connecting or disconnecting
    • H10W72/075—Connecting or disconnecting of bond wires
    • H10W72/07551—Connecting or disconnecting of bond wires characterised by changes in properties of the bond wires during the connecting
    • H10W72/07554—Connecting or disconnecting of bond wires characterised by changes in properties of the bond wires during the connecting changes in dispositions
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W72/00—Interconnections or connectors in packages
    • H10W72/50—Bond wires
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W72/00—Interconnections or connectors in packages
    • H10W72/50—Bond wires
    • H10W72/531—Shapes of wire connectors
    • H10W72/5363—Shapes of wire connectors the connected ends being wedge-shaped
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W72/00—Interconnections or connectors in packages
    • H10W72/50—Bond wires
    • H10W72/541—Dispositions of bond wires
    • H10W72/547—Dispositions of multiple bond wires
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W72/00—Interconnections or connectors in packages
    • H10W72/50—Bond wires
    • H10W72/551—Materials of bond wires
    • H10W72/552—Materials of bond wires comprising metals or metalloids, e.g. silver
    • H10W72/5522—Materials of bond wires comprising metals or metalloids, e.g. silver comprising gold [Au]
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W72/00—Interconnections or connectors in packages
    • H10W72/50—Bond wires
    • H10W72/551—Materials of bond wires
    • H10W72/552—Materials of bond wires comprising metals or metalloids, e.g. silver
    • H10W72/5524—Materials of bond wires comprising metals or metalloids, e.g. silver comprising aluminium [Al]
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W72/00—Interconnections or connectors in packages
    • H10W72/50—Bond wires
    • H10W72/59—Bond pads specially adapted therefor
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W72/00—Interconnections or connectors in packages
    • H10W72/90—Bond pads, in general
    • H10W72/951—Materials of bond pads
    • H10W72/952—Materials of bond pads comprising metals or metalloids, e.g. PbSn, Ag or Cu
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W90/00—Package configurations
    • H10W90/701—Package configurations characterised by the relative positions of pads or connectors relative to package parts
    • H10W90/721—Package configurations characterised by the relative positions of pads or connectors relative to package parts of bump connectors
    • H10W90/722—Package configurations characterised by the relative positions of pads or connectors relative to package parts of bump connectors between stacked chips
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W90/00—Package configurations
    • H10W90/701—Package configurations characterised by the relative positions of pads or connectors relative to package parts
    • H10W90/721—Package configurations characterised by the relative positions of pads or connectors relative to package parts of bump connectors
    • H10W90/724—Package configurations characterised by the relative positions of pads or connectors relative to package parts of bump connectors between a chip and a stacked insulating package substrate, interposer or RDL
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W90/00—Package configurations
    • H10W90/701—Package configurations characterised by the relative positions of pads or connectors relative to package parts
    • H10W90/751—Package configurations characterised by the relative positions of pads or connectors relative to package parts of bond wires
    • H10W90/752—Package configurations characterised by the relative positions of pads or connectors relative to package parts of bond wires between stacked chips
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W90/00—Package configurations
    • H10W90/701—Package configurations characterised by the relative positions of pads or connectors relative to package parts
    • H10W90/751—Package configurations characterised by the relative positions of pads or connectors relative to package parts of bond wires
    • H10W90/754—Package configurations characterised by the relative positions of pads or connectors relative to package parts of bond wires between a chip and a stacked insulating package substrate, interposer or RDL
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W90/00—Package configurations
    • H10W90/701—Package configurations characterised by the relative positions of pads or connectors relative to package parts
    • H10W90/751—Package configurations characterised by the relative positions of pads or connectors relative to package parts of bond wires
    • H10W90/756—Package configurations characterised by the relative positions of pads or connectors relative to package parts of bond wires between a chip and a stacked lead frame, conducting package substrate or heat sink

Landscapes

  • Wire Bonding (AREA)

Abstract

(57)【要約】本公報は電子出願前の出願データであるた
め要約のデータは記録されません。

Description

【発明の詳細な説明】 この発明は機能素子を８次元的に積み重ねて、単位面積
当りの集積度を高密度化することができる半導体装置に
関するものである。
第１図は従来の半導体装置を示す断面図である４同図に
おいて、（１）はセラミック基板、（２）は該セラミッ
ク基板（１）上に形成されたメモリあるいは論理回路等
を形成したチップ、（３）は内部リード、（４）はチッ
プ（２）に形成したパッド（６）と内部リード（３）と
を接続する金線もしくはＡＩ線等の接続リード、（５）
は前記内部リード（３）に接続する外部リード、（７）
は封止蓋である。
このように、従来の半導体装置では１チツプを１セラミ
ツク容器あるいは１プラスチツクパツケージ内に収納し
、金線（４）−内部リード（３）−外部リード（５）の
経路で外部との電気的接続を与えていた。
従来の半導体装置は以上のように構成されているので、
実装密度を上げる方法として、平面上に、配列するもの
であるため、その高密度化に限度がある欠点があった。
この発明は上記のような従来のものの欠点を除去するた
めになされたもので、主表面の集積回路上に形成された
突起電極を持つ大きさの異なる各種半導体基板を、突起
電極間接続もしくは半導体基板の裏面間接綿を交互に三
次元的に積み重ねることにより、高密度化された半導体
装置を提供することを目的としている。
以下、この発明の一実施例を第２図において説明する。
同図において、（１）はセラミック基板、（３）は内部
リード、（４）は金線又はＡＩ線等の金属リード、（６
）は半導体基板（９−１〜９−ｎ）の主表面上の周辺部
に位置して形成されたパッド、（８）は半導体基板（９
−１）〜（９−ｎ）の主表面上に形成された突起電極、
（９−１）〜（９−ｎ）は大きさが異なる例えばメモリ
回路を形成した半導体基板であり、同図に示されている
如く、大きい半導体基板より順次、セラミック基板（１
）上に三次元的に積み重ねられている。
以上、説明したように、バンプ（８）間−パッド（６）
−金線（４）、又はバンブ（８）間−金線（４）−パッ
ド（６）等の組み合せによる電気経路により、半導体基
板（９−１）〜（９−ｎ）上の集積回路は外部と内部リ
ード（３）−金線（４）を通して電気的接触をすること
ができる。
なお、上記実施例ではセラミック基板（１）と半導体基
板（９−１）の裏面と接続しているが、セラミック基板
（１）上にバンブを形成し、当バンブが半導体基板（例
えば９−２）主表面上のバンプと直接接続してもよい。
また、第８図のように多層セラミック基板０Ｑ上に、小
さい半導体基板（１１−ｔ）〜（１１−ｎ　）を下にし
て順次、三次元的に積み重ねてもよい。
以上のように、この発明によれば各半導体基板を三次元
的に積み重ねて配置するよう構成したので、（Ａ）配線
長が短かくなるので、浮遊容量が低下し、高速化が可能
になる。（Ｂ）各層の半導体基板がチップ段階でテスト
できるため、良品チップであることを確認できるので、
Ｎ層積層しても高い良品率を維持することができる。（
Ｃ）チップ間がフリップチップボンディングだから配線
接続の信頼性が高い、（Ｄ）半導体基板を任意の数だけ
積層することができるため、単位面積当りの集積度を高
くすることができ、システム自体の容積を小さくするこ
とができるなどの効果がある。
【図面の簡単な説明】
第１図は従来の半導体装置を示す断面図、第２図は本発
明の一実施例による半導体装置を示す断面図、第８図は
この発明の他の実施例を示す断面図である。 （１）・・・セラミック基板、（２）・・・チップ、（
３）・・・内部リード、（４）・・・金線、（５）・・
・外部リード、（６）・・・パッド。 （７）・・・封止蓋、（８）・・・突起電極、（９−１
）〜（９−ｎ）。 （１１−１）〜（ｔｔ−ｎ）・・・半導体基板、（１０
・・・多層セラミック基板 代理人　　　葛　野　信　− 第１図 手続補正書（自発） 特許庁長官殿 １、事件の表示　　　　特願昭６６−１９１１７１号２
、発明の名称　　　　半導体装置 ３、補正をする者 明細書の発明の詳細な説明の鞠 ６、補正の内容 明細書をつぎのとおり訂正する。

Claims (1)

    【特許請求の範囲】
  1. 主表面の集積回路上に形成された突起電極を持つ大きさ
    の異なる各種半導体基板を、突起電極間接続もしくは半
    導体基板の裏面間接綿を交互に組合せて積み重ねたこと
    を特徴とする半導体装置。
JP56191171A 1981-11-27 1981-11-27 半導体装置 Granted JPS5892230A (ja)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP56191171A JPS5892230A (ja) 1981-11-27 1981-11-27 半導体装置

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP56191171A JPS5892230A (ja) 1981-11-27 1981-11-27 半導体装置

Publications (2)

Publication Number Publication Date
JPS5892230A true JPS5892230A (ja) 1983-06-01
JPS6347259B2 JPS6347259B2 (ja) 1988-09-21

Family

ID=16270076

Family Applications (1)

Application Number Title Priority Date Filing Date
JP56191171A Granted JPS5892230A (ja) 1981-11-27 1981-11-27 半導体装置

Country Status (1)

Country Link
JP (1) JPS5892230A (ja)

Cited By (24)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS6262451U (ja) * 1985-10-04 1987-04-17
US5222014A (en) * 1992-03-02 1993-06-22 Motorola, Inc. Three-dimensional multi-chip pad array carrier
US5381039A (en) * 1993-02-01 1995-01-10 Motorola, Inc. Hermetic semiconductor device having jumper leads
US5485292A (en) * 1993-06-24 1996-01-16 North American Philips Corporation High voltage differential sensor having a capacitive attenuator
US5614766A (en) * 1991-09-30 1997-03-25 Rohm Co., Ltd. Semiconductor device with stacked alternate-facing chips
US5715144A (en) * 1994-12-30 1998-02-03 International Business Machines Corporation Multi-layer, multi-chip pyramid and circuit board structure
US5773896A (en) * 1996-02-19 1998-06-30 Matsushita Electric Industrial Co., Ltd. Semiconductor device having offsetchips
US5907903A (en) * 1996-05-24 1999-06-01 International Business Machines Corporation Multi-layer-multi-chip pyramid and circuit board structure and method of forming same
US6014586A (en) * 1995-11-20 2000-01-11 Pacesetter, Inc. Vertically integrated semiconductor package for an implantable medical device
US6172417B1 (en) * 1993-06-25 2001-01-09 Lucent Technologies Inc. Integrated semiconductor devices
US6365500B1 (en) * 1994-05-06 2002-04-02 Industrial Technology Research Institute Composite bump bonding
US6452279B2 (en) * 2000-07-14 2002-09-17 Mitsubishi Denki Kabushiki Kaisha Semiconductor device
US6590282B1 (en) * 2002-04-12 2003-07-08 Industrial Technology Research Institute Stacked semiconductor package formed on a substrate and method for fabrication
US6593647B2 (en) * 2001-06-15 2003-07-15 Oki Electric Industry Co., Ltd. Semiconductor device
US6646342B2 (en) 2001-03-14 2003-11-11 Matsushita Electric Industrial Co., Ltd. Semiconductor chip and multi-chip module
WO2004038798A3 (en) * 2002-10-22 2004-07-29 Unitive Int Ltd Stacked electronic structures including offset substrates
US6833626B2 (en) 2001-07-09 2004-12-21 Matsushita Electric Industrial. Co., Ltd. Multichip module structure
US6914259B2 (en) 2001-10-03 2005-07-05 Matsushita Electric Industrial Co., Ltd. Multi-chip module, semiconductor chip, and interchip connection test method for multi-chip module
US6975039B2 (en) 1998-08-20 2005-12-13 Oki Electric Industry Co., Ltd. Method of forming a ball grid array package
US7071546B2 (en) * 2002-01-16 2006-07-04 Alfred E. Mann Foundation For Scientific Research Space-saving packaging of electronic circuits
US7211884B1 (en) 2002-01-28 2007-05-01 Pacesetter, Inc. Implantable medical device construction using a flexible substrate
US8089142B2 (en) * 2002-02-13 2012-01-03 Micron Technology, Inc. Methods and apparatus for a stacked-die interposer
US8674494B2 (en) 2011-08-31 2014-03-18 Samsung Electronics Co., Ltd. Semiconductor package having supporting plate and method of forming the same
US8748229B2 (en) 2008-06-11 2014-06-10 Fujitsu Semiconductor Limited Manufacturing method including deformation of supporting board to accommodate semiconductor device

Citations (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS5081475A (ja) * 1973-11-19 1975-07-02
JPS51102566A (en) * 1975-03-07 1976-09-10 Suwa Seikosha Kk Shusekikairo
JPS5337383A (en) * 1976-09-20 1978-04-06 Hitachi Ltd Semiconductor integrated circuit
JPS56103455A (en) * 1980-01-22 1981-08-18 Fujitsu Ltd Semiconductor ic device
JPS56137665A (en) * 1980-03-31 1981-10-27 Chiyou Lsi Gijutsu Kenkyu Kumiai Semiconductor device
JPS56148857A (en) * 1980-04-18 1981-11-18 Mitsubishi Electric Corp Semiconductor device

Patent Citations (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS5081475A (ja) * 1973-11-19 1975-07-02
JPS51102566A (en) * 1975-03-07 1976-09-10 Suwa Seikosha Kk Shusekikairo
JPS5337383A (en) * 1976-09-20 1978-04-06 Hitachi Ltd Semiconductor integrated circuit
JPS56103455A (en) * 1980-01-22 1981-08-18 Fujitsu Ltd Semiconductor ic device
JPS56137665A (en) * 1980-03-31 1981-10-27 Chiyou Lsi Gijutsu Kenkyu Kumiai Semiconductor device
JPS56148857A (en) * 1980-04-18 1981-11-18 Mitsubishi Electric Corp Semiconductor device

Cited By (27)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS6262451U (ja) * 1985-10-04 1987-04-17
US5614766A (en) * 1991-09-30 1997-03-25 Rohm Co., Ltd. Semiconductor device with stacked alternate-facing chips
US5222014A (en) * 1992-03-02 1993-06-22 Motorola, Inc. Three-dimensional multi-chip pad array carrier
US5381039A (en) * 1993-02-01 1995-01-10 Motorola, Inc. Hermetic semiconductor device having jumper leads
US5485292A (en) * 1993-06-24 1996-01-16 North American Philips Corporation High voltage differential sensor having a capacitive attenuator
US6172417B1 (en) * 1993-06-25 2001-01-09 Lucent Technologies Inc. Integrated semiconductor devices
US6365500B1 (en) * 1994-05-06 2002-04-02 Industrial Technology Research Institute Composite bump bonding
US5715144A (en) * 1994-12-30 1998-02-03 International Business Machines Corporation Multi-layer, multi-chip pyramid and circuit board structure
US6014586A (en) * 1995-11-20 2000-01-11 Pacesetter, Inc. Vertically integrated semiconductor package for an implantable medical device
US5773896A (en) * 1996-02-19 1998-06-30 Matsushita Electric Industrial Co., Ltd. Semiconductor device having offsetchips
US5907903A (en) * 1996-05-24 1999-06-01 International Business Machines Corporation Multi-layer-multi-chip pyramid and circuit board structure and method of forming same
US6975039B2 (en) 1998-08-20 2005-12-13 Oki Electric Industry Co., Ltd. Method of forming a ball grid array package
US6452279B2 (en) * 2000-07-14 2002-09-17 Mitsubishi Denki Kabushiki Kaisha Semiconductor device
US6646342B2 (en) 2001-03-14 2003-11-11 Matsushita Electric Industrial Co., Ltd. Semiconductor chip and multi-chip module
US6593647B2 (en) * 2001-06-15 2003-07-15 Oki Electric Industry Co., Ltd. Semiconductor device
US6833626B2 (en) 2001-07-09 2004-12-21 Matsushita Electric Industrial. Co., Ltd. Multichip module structure
US6914259B2 (en) 2001-10-03 2005-07-05 Matsushita Electric Industrial Co., Ltd. Multi-chip module, semiconductor chip, and interchip connection test method for multi-chip module
US7071546B2 (en) * 2002-01-16 2006-07-04 Alfred E. Mann Foundation For Scientific Research Space-saving packaging of electronic circuits
US7211884B1 (en) 2002-01-28 2007-05-01 Pacesetter, Inc. Implantable medical device construction using a flexible substrate
US8089142B2 (en) * 2002-02-13 2012-01-03 Micron Technology, Inc. Methods and apparatus for a stacked-die interposer
US8476117B2 (en) 2002-02-13 2013-07-02 Micron Technology, Inc. Methods and apparatus for a stacked-die interposer
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