JPS5893231A - Preparation of semiconductor device - Google Patents

Abstract

PURPOSE:To realize high integration density by making thicker a conductive film thickness than the mask positioning accuracy and then irradiating an active gas or ion vertical to the main surface of substrate and by forming a conductive film. CONSTITUTION:A P-N junction 12 is formed on an Si substrate 10 with an SiO2 film 11 used as the mask. The substrate is heated up to 150-300 deg.C as a whole and the Si-added Al 13 is deposited by the sputtering in the thickness of about 1.5mum (two times or more of mask positioning accuracy). At this time, the thickness of the side wall 15 of a masking hole 14 becomes about 1/2 of the film 13. Thereafter, a resist 16 is coated, masking is carried out with the mask positioning accuracy of 0.3-0.5mum, the CCl4 is supplied and thereby an Al film 13 is etched by the reactive ion. The resist is removed and a wiring layer 17 is completed. According to this constitution, there is no need of providing an extra wiring layer around the electrod window, high integration density can be realized and substrate surface is not exposed because thickness of side wall of hole is thicker than the masking accuracy even when the masking is deviated.

Description

DETAILED DESCRIPTION OF THE INVENTION (1) 1. Technical Field to which the Invention Pertains The present invention relates to a method of manufacturing a semiconductor device that is suitable and advantageous for forming dense electrode wiring.

(2), Prior art and its problems Conventionally, when forming electrode holes in a conductive film pattern such as an electrode or wiring on a substrate, as shown in FIGS. The pattern 1 was larger than the size of the electrode hole 2 by more than the mask alignment accuracy and extended on the insulating film 3. This extended region 4 was 0.5 to 1 μm, which was inconvenient for high integration of devices. On the other hand, if the electrode hole 2 and the wiring layer pattern 1 are made to have the same size, if the mask alignment is misaligned, the substrate surface 6 will be exposed as shown in FIG. 1(C). When the conductive film is silicon-doped aluminum, the next step is a silicon residue removal step, which causes an accident in which the junction 5 is destroyed, which is extremely inconvenient in terms of yield and reliability.

Furthermore, if only a portion of the electrode hole is covered by the wiring layer, the contact resistance will increase and the device characteristics will be adversely affected, which is inconvenient. That is, the contact resistivity is, for example, 2X10'Ω.
crd, the electrode hole is 1 μmD, and the hole not in contact with the wiring layer is 1 μm x 0.5 μm, then the contact resistance is 2.
00Ω will also increase.

(3) 1. Purpose of the Invention The present invention has been made in view of the above circumstances, and it is an object of the present invention to provide a method for manufacturing a highly integrated and highly reliable semiconductor device.

(4) 1 Summary of the Invention That is, the present invention is characterized in that the thickness of the conductive film is made larger than the mask alignment accuracy, and then the conductive film is processed by irradiating active gas or ions approximately perpendicularly to the main surface of the substrate. It is something to do.

(5) Embodiment 1 of the Invention Next, an embodiment of the invention will be described with reference to FIGS. 2(a) and 2(b). As shown in FIG. 2A, a junction 12 is formed on a silicon substrate 10 using a silicon oxide film 11 as a mask. Next, heat the entire board to about 150-300°0 and
A silicon-doped aluminum film 13 having a thickness of about 100 m is deposited by sputtering. At this time, the silicon-doped aluminum film is deposited on the side wall 15 of the hole 14 to a thickness of about 1/2 of the thickness of the deposited film. Next, a resist (Resist) 16 is applied, a mask is aligned with a mask alignment accuracy of 03 to 0.5 μm by photolithography, and the wiring layer pattern is exposed and developed. Subsequently, CC2 is introduced, and the silicon-doped aluminum base 13 is etched by reactive ion etching, and the resist is removed to complete the wiring layer 17 and form an element (FIG. 2(b)).

Since the mask alignment accuracy is smaller than the hole side wall film thickness, Figure 1 (
As shown in c), the substrate surface of the electrode hole is not exposed. This manufacturing method has been made possible by improvements in mask alignment accuracy, vapor deposition technology, and directional etching compared to conventional methods.

(6) Effects of the first invention As described above, according to the present invention, when providing a wiring layer over the electrode hole, there is no need to arrange an extra wiring layer around the electrode hole, and as shown in FIG. As shown in FIG. 3(a), a large degree of integration can be achieved. In addition, as shown in Figure 3 (b),
Even if the mask alignment deviates, the thickness of the conductive film, ie, the thickness of the hole side wall, is greater than the mask alignment accuracy, so the substrate surface will not be exposed, which is advantageous in terms of reliability. Furthermore, the p-n junction is ~
When the thickness is 1 μm or less, silicon-containing aluminum alloy is used, so etching is required to remove residual silicon after processing the wiring layer, but since the substrate surface is not exposed, the bonding and other element areas are not destroyed. 4. Highly reliable elements can be obtained by not exposing the elements. Furthermore, the contact resistance is not affected by mask alignment and can be obtained as a designed value.

(Modification of the first invention) Although silicon was used as the substrate in this embodiment, a compound semiconductor may also be used, and in addition to an aluminum film containing silicon, copper-doped aluminum, polycrystalline silicon, molybdenum silicide, etc. may be used as the conductive film. In addition to the reactive ion etching method, ion etching may be used as the wiring layer processing method.Furthermore, it can be applied to holes for electrodes between multilayer wiring layers in addition to holes for elements on the substrate. .

[Brief explanation of the drawing]

FIG. 1(A) is a plan view of the wiring area of a conventional semiconductor device.
1(B) and (C) are cross-sectional views of the wiring area of a conventional semiconductor device, FIGS. 2(A) and (B) are cross-sectional views of main parts of an embodiment of the invention, and FIG. (a) and (b) are a plan view and a cross-sectional view, respectively, of a wiring region of a semiconductor device according to an embodiment of the present invention. 10...Silicon substrate, 11...Silicon oxide film, 1
2... pn junction. 13...Silicon-doped aluminum film, 14...Resist. Representative patent attorney Keisuke Norichika and one other person have been invited
Figure 1 Figure 2

Claims (1)

[Claims] A process of arranging an insulating film on a semiconductor substrate on which a semiconductor cluster is formed, a process of opening a predetermined area of the insulating film to form an electrode hole, and a process of aligning a mask on the insulating film including the electrode hole. , a step of disposing a conductive film having a thickness at least twice that of the conductive film, a step of applying a resist on the conductive film, and processing the resist into a predetermined wiring layer pattern; 1. A method for manufacturing a semiconductor device, comprising the steps of vertically irradiating active gas or ions to etch the conductive film until the insulating film is exposed, and then removing the resist.