JPS5893343A - Forming method for isolation region of semiconductor integrated circuit - Google Patents

Abstract

PURPOSE:To obtain the isolation region with narrow width by forming a silicon film to the surface of a substrate with a convex section, selectively removing the silicon film coated to the side surface of the convex section and shaping a concave section to the side surface of the convex section through a removed section. CONSTITUTION:The silicon oxide film 2 is formed to the surface of the silicon substrate 1. A polycrystal silicon film 4 is shaped to the whole surface. Boron is implanted in the film 4, and a high-concentration region 5 and a low-concentation region 6 are molded. The region 6 is removed through etching. The concave section 8 is formed through etching through the removed section 7. The region 5 and the film 2 are removed. A silicon oxide film 9 is buried into the substrate 1, and the isolation region is shaped.

Description

DETAILED DESCRIPTION OF THE INVENTION Technical Field of the Invention The present invention relates to a method for forming isolation regions in semiconductor integrated circuits using etching rate differences depending on impurity concentrations.

TECHNICAL BACKGROUND OF THE INVENTION Conventionally, various methods have been developed for forming isolation regions in semiconductor integrated circuits, and one of them is the so-called "Kogusina method" which is often used.

This method involves forming a silicon nitride film on a semiconductor substrate where an element is to be formed, through an oxide film, and then oxidizing it for a long time (about 10 hours) to a thickness of 1 to 1.5 μm. In this method, an oxide film is grown, and a field oxide film is formed with the lower half buried on the semiconductor substrate to form an isolation region.

Problems with the Background Art of the Invention However, from the table, it can be seen that in this Cosolana method, oxygen molecules invade under the silicon nitride film during field oxidation, and the silicon oxide film from the bottom edge of the silicon nitride film to 1#I becomes so-called pars beag. (birds b@ak), which is shaped like a bird's beak, and the design dimensions cannot be obtained.
In such a bird's hole area, a field oxide film of a predetermined thickness is not formed and the rounding element forming area, which is an unnecessary area, needs to be widened, but on the other hand, the field area including the bird's hole area is wide. This was a major cause of hindering miniaturization. 9 Silicon nitride film NoJ? Turning is done by resist, so the spacing between resists,
That is, the width of the field region is determined by the minimum interval that can be formed by resist, and it is difficult to form element isolation regions with a submicron width using conventional methods. This invention has been developed in view of the above, and provides a method for forming an isolation region of a semiconductor integrated circuit, which enables the formation of an isolation region with a width of 1 submicron and achieves high-density miniaturization.

Summary of the Invention Namely, the method of the present invention includes a step of depositing a film of almost uniform thickness on both surfaces of a substrate having a convex portion, and a step of selectively removing the film deposited on the side surfaces of the convex portion. a step of selectively removing the substrate near the side surface of the convex portion through the removal portion to form a concave portion;
It is characterized by comprising a step of embedding an insulating layer in this recess.

The present invention will be described in detail below.In the present invention, in addition to semiconductor substrates such as silicon substrates, metal substrates such as molybdenum and aluminum can be used.In the present invention, the portions provided with convex portions are For example, a silicone film is used as the film provided in the region where the element is to be formed and on which the convex portion is formed on the surface of the substrate.

Further, in the present invention, as a method for selectively etching the film on the side surface of the convex portion, the film is formed of a silicon film, and ions of, for example, chilene are implanted into the film to remove the part of the film parallel to the substrate. A high concentration region with a holon concentration of 5×10 am or more, and a portion m on the convex side perpendicular to the substrate as a low concentration region with a holon concentration of 10 cm or less, ? This method selectively etches the film in the low-density region, that is, the side surface of the convex portion, by utilizing the difference in etching speed depending on the concentration of ion.Furthermore, in the present invention, the substrate near the side surface of the convex portion is selectively etched. The insulating layer buried in the recess formed by the process, that is, the insulating layer that becomes the isolation region, may be, for example, a silicon oxide film or a silicon nitride film. It may also be a method of forming.

Examples of the invention Examples of the present invention will be described below.

1 to 6 show an embodiment of the present invention. First, as shown in FIG. 1, a silicon oxide film 2 is formed on the surface of a silicon substrate 10 by thermal oxidation or a CVN method. A resist (not shown) is provided in the bag to a thickness of 5,000 mm. After nine resists are placed, this is turned, and the silicon oxide film 2 is selectively etched by, for example, anisotropic etching, using the turned resist as a mask. etching it into
A convex portion 3 made of a silicon oxide film 2 is formed on the surface of a silicon substrate 10 which is a region where an element is to be formed.

Next, as shown in FIG. 2, when a polycrystalline silicon film 4 is deposited on the entire surface to a thickness of about 2001 by CVD, polycrystalline silicon $4 is also deposited on the sides of the convex portion 3 with a uniform thickness. .

Next, when ions are implanted into the surface of the polycrystalline silicon film 40, a large amount of fron is implanted into the part of the polycrystalline silicon film 4 parallel to the silicon substrate 1, forming a high concentration region 5, and the silicon substrate The side surface portion of the convex portion 3 perpendicular to 1 becomes a low concentration region 6 where a small amount of zolon is implanted. In this case, the ion concentration in the high concentration region 5 is 5×10em or more,
The implantation conditions are set so that the Ron concentration in the low concentration region 6 is 1018@m-3 or less.

After this, if necessary, heat treatment may be performed to activate the ion-implanted zolon. In this case, heat treatment conditions include, for example, heat treatment at 1000° C. for 10 minutes in a nitrogenous gas atmosphere.

Then, a known silicon etching drop solution, such as KOH
When the polycrystalline silicon layer 4 deposited with a solution containing .

This effect occurs when the boron concentration is 5, as shown by gut 7 in Figure 7.
At X10 cm or more, the etching rate (etching rate) of the polycrystalline silicon film 4 is slow and fast, and the difference in etching speed is utilized. After removing the polycrystalline silicon 4 and exposing a part of the silicon substrate 1, the exposed silicon substrate 1 is further etched with a solution containing KOH through the removed portion 1 to form convex portions as shown in FIG. Recesses 8, 8 are formed near the SO side surface.

Next, the high concentration region 5 of the polycrystalline silicon film 4 containing a large amount of silicon is removed by etching, and then the silicon oxide film 2 on which the convex portion 3 is formed is removed by etching.
As shown in the figure, the entire surface of the silicon substrate 1 is exposed. After this, a silicon oxide film 9 is deposited on the entire surface of the silicon substrate 1, and as shown in FIG. Bury it and use this part as a separation area.

Thereafter, a transistor is formed in a region where an element is to be formed surrounded by an isolation region according to a conventional method.

Therefore, in the conventional Cosolana method, a resist is used for the continuous turning of the silicon nitride film.

The width of the current distribution region is 1 μm or more, but in the present invention, a low concentration of iron is determined depending on the thickness of the polycrystalline silicon film 4, and the thickness is controlled. It becomes possible to form an isolation region with a width of several tens of thousands.

Note that in the above explanation, the convex portion 3 provided on the surface of the silicon substrate 1 is
Although the case is shown in which the film is formed on the silicon oxide film 2, a silicon nitride film or the like may also be used.

As described in detail, the method for forming an isolation region in a semiconductor integrated circuit according to the present invention utilizes the difference in etching speed depending on the impurity concentration to form a narrow recess in a substrate without using a resist. If an insulating film is buried here to form an isolation region, it will be more difficult to achieve high-density miniaturization by making it possible to form a submicron width.

[Brief explanation of drawings]

1 to 6 are cross-sectional views showing one embodiment of the method for forming an isolation region according to the present invention according to the steps, and FIG. 7 is a diagram illustrating the relationship between the concentration and etching rate of the silicon film. It is 7. 1... Silicon substrate, 2... Silicon oxide film, S.
...Convex portion, 4...Polycrystalline silicon film, 5...High concentration region, 6...Low concentration region, 7...Removed portion, 8...
Concave portion, 9... silicon oxide film. Applicant's agent Patent attorney Suzue Takehiko 111 3 RiIl/12v! J Figure 3 Figure 5 Figure 61!1 7th WIJ 11 boats (crn')

Claims (1)

[Scope of Claims] (1) A step of depositing a film of approximately uniform thickness on the surface of a substrate having convex portions, and a step of selectively removing the film deposited on the side surfaces of the convex portions. , a step of selectively removing the substrate near the side surface of the convex portion through a removal portion to form a recess, and a step of embedding an insulating layer in the recess.
111. A method for forming an isolation region in a semiconductor integrated circuit. (2) A method for forming an isolation region in a semiconductor integrated circuit according to claim 1, characterized in that a semiconductor substrate or a metal substrate is used as the substrate. A method for forming an isolation region in a semiconductor integrated circuit according to claim 1, characterized in that: (4) As a method for selectively etching the film on the side surface of the convex portion, the film is formed of a silicon film, and by implanting ion ions into this film, the part of the film parallel to the substrate is raised. 2. A method for forming an isolation region in a semiconductor integrated circuit according to claim 1, wherein a side surface of the convex portion perpendicular to the substrate is used as a low concentration region, and the low concentration region is selectively etched. (5) The concentration in the high talk area is 5X10@m
5. A method for forming an isolation region in a semiconductor integrated circuit according to claim 4, wherein the ion concentration of one low concentration region is set to 10@m or less.