JPS5893397A - Manufacturing method of wiring board - Google Patents
Manufacturing method of wiring boardInfo
- Publication number
- JPS5893397A JPS5893397A JP19222481A JP19222481A JPS5893397A JP S5893397 A JPS5893397 A JP S5893397A JP 19222481 A JP19222481 A JP 19222481A JP 19222481 A JP19222481 A JP 19222481A JP S5893397 A JPS5893397 A JP S5893397A
- Authority
- JP
- Japan
- Prior art keywords
- wiring board
- thin film
- insulator
- wiring
- manufacturing
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
Landscapes
- Production Of Multi-Layered Print Wiring Board (AREA)
Abstract
(57)【要約】本公報は電子出願前の出願データであるた
め要約のデータは記録されません。(57) [Summary] This bulletin contains application data before electronic filing, so abstract data is not recorded.
Description
【発明の詳細な説明】
発明の技術分野
この発明は、銅の薄膜からなる配線ノ4ターンを有する
配線基板の製造方法に関する◎発明の技術的背景とその
問題点
従来の薄膜配線基板においては、絶縁性基体上にCr、
Pd、 Auの薄膜を順次蒸着し、その上にフォトレ
ジストを塗布し無光、現像し、それをマスクとして上記
薄膜を選択的にエツチング除去して、配線パターンを形
成していた0しかし、金(Au )を配線t!パターン
材料に用いることはコスト面で好ましく々い。DETAILED DESCRIPTION OF THE INVENTION Technical Field of the Invention The present invention relates to a method for manufacturing a wiring board having four turns of wiring made of a copper thin film. ◎Technical background of the invention and its problems In a conventional thin film wiring board, Cr on an insulating substrate,
Thin films of Pd and Au were sequentially deposited, a photoresist was applied thereon, developed without light, and the thin film was selectively etched away using the photoresist as a mask to form a wiring pattern. Wire (Au)! It is preferable to use it as a pattern material in terms of cost.
一方、このような薄膜配線パターンにょシ多層配線基板
を形成する場合、層間絶縁体としてポリイミド等の有機
質膜が従来用いられている。On the other hand, when forming a multilayer wiring board using such a thin film wiring pattern, an organic film such as polyimide is conventionally used as an interlayer insulator.
しかしながら、このような有機質膜は一般に熱伝導性が
悪いため、この多層配線基板上に大電力のLSI等のチ
ップ部品を実装する場合、信頼性の点で問題がある。ま
た、配線パターンに大電流を流す場合、メッキによシ肉
付けを行なうが、メッキ工程は一般に煩雑であシ、さら
にメッキ膜の内部応力によってパターンが破損するおそ
れがある。However, since such organic films generally have poor thermal conductivity, there is a problem in reliability when mounting chip components such as high-power LSIs on this multilayer wiring board. Furthermore, when a large current is passed through a wiring pattern, thickening is performed by plating, but the plating process is generally complicated and there is a risk that the pattern may be damaged due to internal stress in the plating film.
発明の目的
この発明の目的は、低コストであって、放熱性の問題も
なく、さらに大電流にも耐え得る配線基板の製造方法を
提供するととである。OBJECTS OF THE INVENTION An object of the present invention is to provide a method for manufacturing a wiring board that is low cost, has no heat dissipation problems, and can withstand large currents.
発明の概要
この発明は、下地絶縁体上に銅薄膜を形成し、この上に
7オトレジストを塗布して露光、現像し、この無光、現
僚後の7オトレジストをマスクとして銅薄膜を選択的に
エツチング除去した後、フォトレジストを除去し、しか
る後中性雰囲気中にて銅薄膜が下地絶縁体と反応する温
度以上で焼成を行なうことによシ、銅薄膜からなる配線
AIパターン有する配線基板を得ることを特徴としてい
る。Summary of the Invention This invention involves forming a copper thin film on a base insulator, coating it with a 7-photoresist, exposing and developing it, and selectively coating the copper thin film using the 7-photoresist as a mask. After removing the photoresist by etching, the photoresist is removed and then baked in a neutral atmosphere at a temperature higher than that at which the copper thin film reacts with the underlying insulator, thereby producing a wiring board having a wiring AI pattern made of the copper thin film. It is characterized by obtaining.
発明の効果
この発明によれば、薄膜配線ノリーンを銅薄膜で形成す
るため、製造コストを下げることができるとともに1フ
オトエツチングでノリーニングを行なうので、微細な配
線ノ母ターンが得られる◎また、焼成が可能なため、多
層配線基板を形成する場合、層間絶縁体として焼成を必
要とするが熱伝導性の良好な厚膜絶縁体を使用すること
ができる。さら忙、配線パターンとして::1:
やはシ焼成を必要とするがメッキに比べて工程が簡単で
、電気伝導性が良好な大電流に耐え得る厚膜導体を併用
することが可能である。従って、大電力LSI等を実装
するのに適し九多層配線基板を得ることができる。Effects of the Invention According to the present invention, since the thin film wiring layer is formed of a copper thin film, the manufacturing cost can be reduced, and since the layering is performed in one photo etching, a fine wiring pattern can be obtained. Therefore, when forming a multilayer wiring board, a thick film insulator with good thermal conductivity can be used as an interlayer insulator, although it requires firing. As a wiring pattern: 1: Although it requires baking, the process is simpler than plating, and it is possible to use thick film conductors with good electrical conductivity that can withstand large currents. . Therefore, a multilayer wiring board suitable for mounting high-power LSIs and the like can be obtained.
発明の実施例
第1図はこの発明の一実施例の基本工程図である。まず
、下地絶縁体である例えばアルミナ(At20s)ある
いはシリコン酸化物(sto2)を主成分とする基体1
上の全面に1第1図(a)K示す如く銅薄膜2を例えば
蒸着またはスパッタ、メッキ等圧よシ1〜20μ程度被
着形成する。次に、m1図(b)Ic示す如く銅薄lI
2の上にフォトレジスト3を塗布し、所定ノ母ターンに
露光、現像を竹なって、不要部分3を除去する。次に、
この不要部分3が除去されたフォトレジスト3をマスク
として、銅薄JII2を選択的にエツチング除去する。Embodiment of the Invention FIG. 1 is a basic process diagram of an embodiment of the invention. First, a base 1 whose main component is a base insulator such as alumina (At20s) or silicon oxide (sto2)
As shown in FIG. 1(a)K, a thin copper film 2 of about 1 to 20 .mu.m is deposited on the entire upper surface by, for example, vapor deposition, sputtering, plating or the like. Next, as shown in m1 diagram (b) Ic, the copper thin lI
A photoresist 3 is applied on the photoresist 2, exposed to light in a predetermined pattern, and developed to remove unnecessary portions 3. next,
Using the photoresist 3 from which unnecessary portions 3 have been removed as a mask, the thin copper JII 2 is selectively etched away.
そして次に、フォトレジスト3を例えば酸素プラズマに
よシ、または銅薄mzが酸化しない程度の温度下の焼成
によシ、またはレジストストリッパによシ除去する・
しかる後、中性雰囲気、例えば窒素またはアルゴン中に
て、銅薄膜2が下地絶縁体である基体1と反応する温度
以上で焼成を行なう。ここで、基体1がAz2o5を主
成分とする材料の場合は、900℃〜1200℃の範囲
で館1図(e)K示す如く銅アルミネート4が形成され
、銅薄膜2と基体1との強固な結合が発生する。また、
基体1が8102を主成分とする材料の場合は、750
℃〜950℃の範囲で同様に強固な結合が生じる。Then, the photoresist 3 is removed, for example, by oxygen plasma, or by baking at a temperature that does not oxidize the copper thin film, or by using a resist stripper. After that, the photoresist 3 is removed in a neutral atmosphere, for example, nitrogen. Alternatively, baking is performed in argon at a temperature higher than the temperature at which the copper thin film 2 reacts with the substrate 1, which is an underlying insulator. Here, when the substrate 1 is a material whose main component is Az2O5, a copper aluminate 4 is formed in the temperature range of 900°C to 1200°C as shown in Fig. 1(e)K, and the bond between the copper thin film 2 and the substrate 1 is A strong bond occurs. Also,
If the substrate 1 is made of a material whose main component is 8102, 750
Similar strong bonding occurs in the temperature range from .degree. C. to 950.degree.
こうして、基体J上に第1図(c)K示す如く銅薄膜2
から々る配線ノ譬ターン5が形成される◎第2図はこの
発明を多層配線基板の製造に適用した場合の工程図を示
すものである。即ち、第1図の工程によって得られた銅
薄膜からなる第1層配線ツクターン5の少なくとも一部
を檄うように1熱分解型またはペースト中のガラスの酸
素分によシ分解する有機物を、主成分とする絶縁体ペー
スト、つまり中性雰囲気中で焼成可能な厚膜用絶縁体ペ
ーストを印刷し、焼成することによって、第2図←)K
示す如く層間絶縁体としての厚膜絶縁体6を形成する。In this way, a thin copper film 2 is formed on the substrate J as shown in FIG. 1(c)K.
A parable of a dry wiring pattern Turn 5 is formed. ◎ Fig. 2 shows a process diagram when the present invention is applied to the manufacture of a multilayer wiring board. That is, in order to remove at least a part of the first layer wiring layer 5 made of the copper thin film obtained by the process shown in FIG. By printing and firing the insulating paste as the main component, that is, the insulating paste for thick films that can be fired in a neutral atmosphere,
As shown, a thick film insulator 6 as an interlayer insulator is formed.
そして次に、例えば銅ペースト、ニッケルペースト等の
厚換用導体(−ストを印刷し、中性雰囲気中で焼成する
ことによって、第2図(b)に示す如く厚膜絶縁体6に
形成された開口部7を通して第1層配線パターン5と適
宜電気的に接続された厚膜導体からなる第1層配線パタ
ーン8を形成する。Next, a thick film insulator 6 is formed as shown in FIG. 2(b) by printing a conductor (-) for thickening, such as copper paste or nickel paste, and firing it in a neutral atmosphere. A first layer wiring pattern 8 made of a thick film conductor is electrically connected to the first layer wiring pattern 5 through the opening 7 .
以下同様に、必要に応じて厚膜絶縁体からなる階間絶縁
体と、厚膜導体からなる、または層間絶縁体を下地導体
として第1層配線パターンと同様の工程で形成される配
線パターンとを交互に積層することによって、多層配線
基板が作製される。Similarly, if necessary, an interstory insulator made of a thick film insulator, and a wiring pattern made of a thick film conductor or formed in the same process as the first layer wiring pattern using the interlayer insulator as a base conductor. A multilayer wiring board is produced by alternately laminating the above.
このようにして、この実施例によれば厚膜絶縁体からな
る層間絶縁体を介して銅薄膜または厚膜導体からなる配
線ノ9ターンを積層した多層配線基板が得られる@
この場合、銅薄膜からなる配線パターンは金の薄膜から
なる配線ノ4?ターンに比べ非常に安価である0しかも
、この配線ノ母ターンはエツチングによりノ母ターニン
グされるため、例え−ば線幅40μ程度の微細なノ母タ
ーンに形成することが可能である。In this way, according to this example, a multilayer wiring board is obtained in which nine turns of wiring made of a thin copper film or a thick film conductor are laminated via an interlayer insulator made of a thick film insulator. The wiring pattern consisting of is the wiring No. 4 consisting of a thin film of gold? It is much cheaper than the wiring pattern.Moreover, since the main turn of the wiring is patterned by etching, it is possible to form a fine main turn with a line width of about 40 microns, for example.
また、層間絶縁体に熱伝導性の良い厚膜絶縁体を用いる
ことができるため、基板上に大電力LSIチッf%を実
装する場合、好都合である。Further, since a thick film insulator with good thermal conductivity can be used as the interlayer insulator, it is convenient when mounting a high power LSI chip f% on a substrate.
さう<銅ペースト、二、ケルペースト等の中性雰囲気中
で焼成する厚膜用導体ペーストを用いて配線パターンを
形成できるため、銅薄膜からなる微細な配線ノ4ターン
と厚膜導体からなる配線ノ臂ターンとの組合せによる多
鳩基板が得られるので、後者の配線AIパターン大電流
の流れる部分に使用することによって、大電力LSIチ
ップ叫の実装に十分対応することが可能となるO特に銅
ペーストからなる厚膜導体は、電気伝導性に優れるのみ
でなく、半田付は性が良好で、半田リーチに対しても強
いという特長があるO“、tgsom*thati !
l:。Since wiring patterns can be formed using thick film conductor pastes such as copper paste and kel paste, which are fired in a neutral atmosphere, it is possible to form wiring patterns consisting of four turns of fine wiring made of thin copper film and thick film conductors. Since a multi-circuit board can be obtained by combining the wiring arm turn, by using the latter wiring AI pattern in the part where large current flows, it becomes possible to sufficiently support the mounting of high power LSI chips. Thick film conductors made of copper paste not only have excellent electrical conductivity, but also have good soldering properties and are resistant to solder reach.
l:.
第1図はこの発明の一実施例の工程図、第2図はこの発
明を多層配線基板の製造に適用した実施例の工程図であ
る。FIG. 1 is a process diagram of an embodiment of the present invention, and FIG. 2 is a process diagram of an embodiment in which the invention is applied to the manufacture of a multilayer wiring board.
1・・・基体(下地絶縁体)、2・・・銅薄膜、3・・
・フォトレジスト、4・・・銅アルミネート、5・・・
銅薄膜からなる配線/IPターン、6・・・厚膜絶縁体
からなる層間絶縁体(下地絶縁体)、7・・・開口部8
・・・厚膜導体または銅薄膜からなる配線1?ター0
出願人代理人 弁理士 鈴 江 武 彦:、、a;、
1図
フ1... Base (underlying insulator), 2... Copper thin film, 3...
・Photoresist, 4...Copper aluminate, 5...
Wiring/IP turn made of copper thin film, 6... Interlayer insulator (base insulator) made of thick film insulator, 7... Opening 8
...Wiring 1 made of thick film conductor or copper thin film? ter0 Applicant's agent Patent attorney Takehiko Suzue: a;
Figure 1
Claims (5)
レジストを塗布して露光、現俸し、この露光、現像後の
7オトレジストを!スクトシて前記銅薄膜を選択的にエ
ツチング除去した後、フォトレジストを除去し、しかる
後中性雰囲気中にて前記銅薄膜が前記下地絶縁体と反応
する温度以上で焼成を行なうことにょシ、銅薄膜が遣方
法。(1) Form a copper thin film on the base insulator, apply 7-photoresist on it, expose and develop it, and after this exposure and development, 7-photoresist! After selectively etching and removing the copper thin film, the photoresist is removed, and then baking is performed in a neutral atmosphere at a temperature higher than the temperature at which the copper thin film reacts with the underlying insulator. Thin film is the method.
囲第1項記載の配線基板の製造方法。(2) The method for manufacturing a wiring board according to claim 1, wherein the base insulator is a base of the wiring board.
体であって、厚膜絶縁体ペーストを印刷し中性雰囲気中
にて焼成することKよって形成されるものである特許請
求の範囲第1項記載の配線基板の製造方法。(3) The base insulator is an interlayer insulator in a multilayer wiring board, and is formed by printing a thick film insulator paste and baking it in a neutral atmosphere.Claim 1 A method for manufacturing a wiring board as described in Section 1.
ける配線i4ターンである特許請求の範囲第1項記載の
配線基板の製造方法。(4) The method for manufacturing a wiring board according to claim 1, which is a wiring i4 turn in a Noreen multilayer wiring board made of a copper thin film.
−ストを印刷し中性雰囲気中にて焼成することKよって
形成される厚膜導体からなる配線/?ターンとともに多
層配線基板におけ゛る配線)臂ターンを構成するもので
ある特許請求の範囲第1項記載の配線基板の製造方法。(5) Wiring/arm turn thick film conductor made of copper thin film (
- Wiring made of thick film conductor formed by printing and firing in a neutral atmosphere/? 2. The method of manufacturing a wiring board according to claim 1, wherein the wiring board together with the turn constitutes a turn in a multilayer wiring board.
Priority Applications (5)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP19222481A JPS5893397A (en) | 1981-11-30 | 1981-11-30 | Manufacturing method of wiring board |
| DE8282108225T DE3280233D1 (en) | 1981-09-11 | 1982-09-07 | METHOD FOR PRODUCING A SUBSTRATE FOR MULTI-LAYER SWITCHING. |
| EP82108225A EP0074605B1 (en) | 1981-09-11 | 1982-09-07 | Method for manufacturing multilayer circuit substrate |
| US06/415,798 US4525383A (en) | 1981-09-11 | 1982-09-08 | Method for manufacturing multilayer circuit substrate |
| US06/695,466 US4569902A (en) | 1981-09-11 | 1985-01-28 | Method for manufacturing multilayer circuit substrate |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP19222481A JPS5893397A (en) | 1981-11-30 | 1981-11-30 | Manufacturing method of wiring board |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPS5893397A true JPS5893397A (en) | 1983-06-03 |
Family
ID=16287723
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP19222481A Pending JPS5893397A (en) | 1981-09-11 | 1981-11-30 | Manufacturing method of wiring board |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPS5893397A (en) |
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US5139856A (en) * | 1988-12-20 | 1992-08-18 | Ngk Insulators, Ltd. | Plated ceramic or glass substrate having undercoat |
-
1981
- 1981-11-30 JP JP19222481A patent/JPS5893397A/en active Pending
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US5139856A (en) * | 1988-12-20 | 1992-08-18 | Ngk Insulators, Ltd. | Plated ceramic or glass substrate having undercoat |
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