JPS5894237A - Frequency divider - Google Patents

Abstract

PURPOSE:To attain the high frequency working, high reliability and a high degree of integration at one time, by forming only the high-speed working part of the front stage with a semiconductor IC of the III-V group compound and forming a frequency dividing circuit of the rear stage with Si-IC. CONSTITUTION:A GaAs-IC chip 11 which takes charge of a high-speed dividing operation of the front stage is connected to a prescribed area on the surface of an Si-IC chip 12 which takes charge of a low-speed operation of a level converting circuit and the rear stage upside down and in a flip chip state. That is, the thick-plated posts formed on an input signal pad 51 and an output signal pad 61 of the chip 11 are loaded directly to an input clock signal pad and input signal pad 52 of the level converting circuit formed on the chip 12, respectively. With such a constitution, the working with a high input clock frequency, a low cost and high reliability can be attained at one time.

Description

[Detailed description of the invention] This invention connects multiple stages of 1/2 frequency divider circuits in cascade,
This invention relates to a frequency divider that is an integrated circuit.

Figure 1(a) is a plan view showing the external appearance of a conventional frequency divider constructed from a single integrated circuit (IC), and Figure 1(b) is a line IB-IB in Figure 1(a). FIG. In this conventional example, silicon (Si) IC or gallium arsenide (Ga
Aθ) A single IC chip (+l) such as an IC is mounted on the pan cage (2), and the ground pad (3) formed on the chip ill is connected to the ground bottom surface (+l) of the package (2).
4) with bonding wires, input clock signal pad (6), output signal pad (6) and power supply pad,
The pressure pads (7) are connected to the input bonding area (8), output bonding area (9), and power supply voltage application bonding area (IO) of the package (2), respectively, by bonding wires.

With a frequency divider constructed from a single IC in this way, it is extremely difficult to achieve both operation in a high frequency band of 2GH2 or higher, low cost, and high nIIJI performance. Ta. In other words, frequency dividers using 81 IC chips are more than an order of magnitude cheaper in material cost than GaAs ICs because 81 naturally exists inexhaustibly. Although it has the advantage of being dramatically improved over frequency dividers using compound semiconductors, it has a mobility that is nearly an order of magnitude lower than that of GaAa, and it is difficult to realize it entirely on a semi-insulating substrate. For reasons of this, it has not been possible to obtain very high operable division frequencies of 2()H2 or higher. On the other hand, G
Although a frequency divider using an aAs IC chip is capable of stable frequency division operation for high input frequencies of 2 GHz or higher due to the above-mentioned reasons, the yield is significantly lower than that of SI due to lower reliability and integration. , and because the material price is higher than that of 81, it has the disadvantage that it is difficult to reduce the cost at a practical level. It is an object of the present invention to provide a frequency divider that simultaneously realizes frequency operation, high multipliers, high integration, that is, low cost.

That is, in the present invention, in a configuration in which four frequency dividers are connected in cascade in multiple stages, the front stage part that receives the input signal is E31.
■-V group compound semiconductor IC capable of faster operation than 1C
It consists of a splitter chip consisting of 81 input frequencies.
After reducing the frequency band to a frequency band that can be divided at 1C, the above ■
-The output signal terminal of the divider chip consisting of a group V compound semiconductor IC is connected to the subsequent stage 5ill:! via a level conversion circuit. The above object is achieved by connecting the frequency divider to the input signal terminal of the frequency divider.

FIG. 2(a) is a plan view showing the appearance of a frequency divider according to an embodiment of the present invention, and FIG. 2(b) is a sectional view taken along line H-11BN in FIG. 2(a). In Fig. 2(a), there is a built-in first-stage GaAs frequency divider chip with m stages of cascade-connected frequency dividers (b), and a second-stage frequency divider with built-in level conversion circuits and n-stages of 1A frequency dividers connected vertically. A Si IC chip (121'ii) is mounted on the above package (2), and the input clock signal pad (51) of the previous stage GaAs IC chip (II) is connected to the input bonding area (8) of the package (2) with a bonding wire. Output signal pad (61).

Connect the ground pad c11) and power supply voltage pad ()1) to the level change circuit input (M pad (52), & ground hat 34 and power supply voltage pad (72) on the rear d81 XC step Cl21, respectively). 81 IC chips (12
1) Connect the output signal pad (62) and the tjI source voltage voltage pad (73) with bonding wires to the output bonding area (9) of the package (2) and the bond ink area for applying the 'M source voltage, respectively. Overall, the result is 1 r of gains divided by 1/2 of losses.

In this way, only the m stages of the frequency divider can be replaced by a GaAg divider that can be manufactured at high speed, and the n stages Ai6
Since it is composed of an 81 frequency divider with good axiality and high yield, it is possible to operate up to a higher frequency band than the conventional 811C-only frequency divider, and at the same time, the number of stages of the 81 frequency divider is usually reduced. Since n is sufficiently large compared to the GaAa frequency division gain division number m, that is, Ω>>m, the GaAa frequency division gain as a whole is
It also has the advantage of being significantly cheaper than a frequency divider made up of only Aa ICs.

FIG. 3(a) is a plan view showing the appearance of a frequency divider according to another embodiment of the present invention, and FIG. 3(b) is a plan view showing the appearance of a frequency divider according to another embodiment of the present invention.
A cross-sectional view taken along the [lB-[lB line] is shown. In this embodiment, as shown in the figure, G
aAs IC chip (II) It is connected upside down to a predetermined portion on the surface of the 5iIO chip 021, which is responsible for the t-level conversion circuit and the low-speed frequency division operation at the subsequent stage, in the form of a 7-lip chip. That is, as shown in FIG. 3(b), the GaAs IC chip (11+ input signal pads (51+)
) and the thick plating pillars (511) and (611) formed on the output signal pad (61) respectively.
Input clock signal pad formed on chip 021 (
6) and the level conversion circuit input signal pad (52) without using bonding wires.

The branching unit configured in this manner not only provides the same effects as the embodiment shown in Fig. 2, but also eliminates the need for any wires connecting the GaAs IC chip and the 81-chip chip, making assembly easier. Since the bonding process becomes simpler and the delay time due to the bonding wire is shortened, even higher speed operation becomes possible.
Since an integrated circuit can be formed on the surface of the 5tIC chip where the C chip is mounted, it also has the advantage of increasing the degree of integration.

In addition, in the above embodiment, a combination circuit of 8110 and GaAa IC was described, but indium phosphide (InP)
Other m that can operate faster than Eli IO such as IC
It goes without saying that the same effect can be achieved by combining the -v1pjc compound semiconductor integrated circuit and the Si process.

As explained above, the frequency divider according to the present invention is
Only the first stage high-speed operation part is a tO-V group compound semiconductor IC.
After reducing the frequency to below the maximum operating frequency division frequency of the frequency divider circuit using 5i IC, the subsequent frequency divider circuit is implemented using Si IC.
) It is possible to achieve both operation at a high input clock frequency a of 12 or more, low cost, and high reliability.

[Brief explanation of the drawing]

FIG. 1(a) is a plan view showing the external appearance of a frequency divider with a conventional configuration, and FIG. 1(b) is an IB-IB diagram of FIG. 1(a).
2(a) is a plan view showing the external appearance of a frequency divider according to an embodiment of the present invention, and FIG. 2(1)) is a cross-sectional view of the IB-11BM in FIG. 2(a). Sectional view at 3rd
Figures (a) and 'i are a plan view showing the external appearance of a frequency divider according to another embodiment of the present invention, and Figure 3 (b) is a sectional view taken along line 111B-IIIB in Figure 3 (a). In a certain diagram, io) is a GaAs IC nap (first divider chip), 02) is a 5i ICi chip (second divider chip), (51) l (61) is a connecting node, (51
1), (611) are conductor pillars, (61, (52) Ic
The corresponding pad is 0. Note that the same reference numerals in the figures are the same.
c indicates a considerable portion 0 Agent Shin Kuzuno - (1 other person) 1st L4 Book 2 Figure 3

Claims (1)

[Claims] (1) 1/2, which divides the frequency of the input signal into 1/2
In an integrated circuit in which multiple stages of frequency dividers are connected in series, the first stage is a first frequency divider chip made of a -Ma group compound semiconductor, and the second stage is a second divider chip made of silicon. The front stage portion on the first divider chip and the rear stage portion on the second divider chip are connected to each other through a signal level conversion circuit formed on the second divider chip. A frequency divider characterized by being connected in cascade. i21 A conductive column formed by thick plating on the connection pad of the first branch chip to the second branch chip is connected to the second branch chip.
2. The frequency divider according to claim 1, wherein the frequency divider is directly bonded in an upside-down manner to a pad formed on the divider chip corresponding to the connection band.