JPS5896762A - Semiconductor element - Google Patents

Semiconductor element

Info

Publication number
JPS5896762A
JPS5896762A JP56195410A JP19541081A JPS5896762A JP S5896762 A JPS5896762 A JP S5896762A JP 56195410 A JP56195410 A JP 56195410A JP 19541081 A JP19541081 A JP 19541081A JP S5896762 A JPS5896762 A JP S5896762A
Authority
JP
Japan
Prior art keywords
type
conductor layer
layer
trench conductor
bipolar transistor
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP56195410A
Other languages
Japanese (ja)
Inventor
Masahide Yamauchi
山内 眞英
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Mitsubishi Electric Corp
Original Assignee
Mitsubishi Electric Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Mitsubishi Electric Corp filed Critical Mitsubishi Electric Corp
Priority to JP56195410A priority Critical patent/JPS5896762A/en
Publication of JPS5896762A publication Critical patent/JPS5896762A/en
Pending legal-status Critical Current

Links

Classifications

    • HELECTRICITY
    • H10SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10DINORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D84/00Integrated devices formed in or on semiconductor substrates that comprise only semiconducting layers, e.g. on Si wafers or on GaAs-on-Si wafers
    • H10D84/40Integrated devices formed in or on semiconductor substrates that comprise only semiconducting layers, e.g. on Si wafers or on GaAs-on-Si wafers characterised by the integration of at least one component covered by groups H10D12/00 or H10D30/00 with at least one component covered by groups H10D10/00 or H10D18/00, e.g. integration of IGFETs with BJTs
    • H10D84/401Combinations of FETs or IGBTs with BJTs
    • H10D84/403Combinations of FETs or IGBTs with BJTs and with one or more of diodes, resistors or capacitors
    • H10D84/406Combinations of FETs or IGBTs with vertical BJTs and with one or more of diodes, resistors or capacitors

Landscapes

  • Bipolar Transistors (AREA)
  • Metal-Oxide And Bipolar Metal-Oxide Semiconductor Integrated Circuits (AREA)

Abstract

(57)【要約】本公報は電子出願前の出願データであるた
め要約のデータは記録されません。
(57) [Summary] This bulletin contains application data before electronic filing, so abstract data is not recorded.

Description

【発明の詳細な説明】 この発明は半導体素子、特に利得制御および破壊強度の
向上を図ったバイポーラ形トランジスタに関するもので
ある。
DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a semiconductor device, and particularly to a bipolar transistor with improved gain control and breakdown strength.

高周波高出力用として利用されるこの種のバイポーラト
ランジスタの従来例を第1図に示しである。すなわち、
この第1図において、(1)はn形シリコン基板、(2
)はこの基板上に気相成長された第1のn層、(3)は
この第1のn層上に拡散、あるいはイオン注入などによ
って選択的に形成された第1のP層、(4)はこの第1
のP層上に同様に拡散。
A conventional example of this type of bipolar transistor used for high frequency and high output is shown in FIG. That is,
In this FIG. 1, (1) is an n-type silicon substrate, (2
) is the first n-layer grown in vapor phase on this substrate, (3) is the first p-layer selectively formed on this first n-layer by diffusion or ion implantation, and (4 ) is this first
Similarly diffused onto the P layer.

あるいはイオン注入などによって選択的に形成された第
2のn層、(5)はこれらの表面に形成された酸化膜、
(6)および(7)は前記層(4)および(3)に接続
された金あるいはアルミニウムなどからなるエミッタお
よびベース電極であシ、この構造によシいわゆるNPN
形バイポーラトランジスタを構成している。
or a second n layer selectively formed by ion implantation, etc.; (5) is an oxide film formed on these surfaces;
(6) and (7) are emitter and base electrodes made of gold or aluminum connected to the layers (4) and (3).
It constitutes a type bipolar transistor.

そしてこのような高周波高出力用のバイポーラトランジ
スタにおいては、一般に高利得、高出力を得るために、
前記第1のP層(3)および第2のn層(4)の形成深
さは非常に浅く、これによって遍電圧励振、過大力励振
、負荷の異常などによ)極めて破壊し易い構造となって
おシ、この対策として従来は外部回路として自動出力制
御回路、いわゆるAPC回路などを伺加することによシ
、する出カレペルに達したときはトランジスタの入力レ
ベルを下げるなどの破壊に対する特別の考慮を払ってい
るのであるが、とのAPC回路についてもドライブ段の
電源電圧を降下しているために、発振などのトラブルが
往々にして発生するなどの不都合があった。
In such bipolar transistors for high frequency and high output, in order to obtain high gain and high output,
The formation depth of the first P layer (3) and the second N layer (4) is very shallow, which results in a structure that is extremely susceptible to destruction (due to uniform voltage excitation, excessive force excitation, abnormal load, etc.). As a countermeasure to this problem, conventionally, it has been necessary to add an automatic output control circuit, a so-called APC circuit, as an external circuit. However, since the power supply voltage of the drive stage is lowered in the APC circuit, troubles such as oscillation often occur.

この発明は従来のこのような欠点に鑑み、バイポーラト
ランジスタのエミッタ側に電界効果トランジスタを接続
して、その破壊強度を向上させるようにしたものである
In view of these conventional drawbacks, the present invention connects a field effect transistor to the emitter side of a bipolar transistor to improve its breakdown strength.

以下、この発明の一実施例につき、第2図および第3図
を参照して詳細に説明する。
Hereinafter, one embodiment of the present invention will be described in detail with reference to FIGS. 2 and 3.

第2図はこの実施例を適用したNPN形バイポーラトラ
ンジスタの構成を示している。この第2図中、前記第1
図と同一符号は同一または相当部分を表わしておシ、こ
の実施例では前記従来例において、第1のn層(2)上
に第1のP層(3)と同時に第2のP IF!t (8
)を形成させ、この第2のP層(8)にエミッタ電極(
6)を接続させると共に、酸化膜(5)を介して金属か
らなるゲート電極(9)を設けたものである。
FIG. 2 shows the structure of an NPN type bipolar transistor to which this embodiment is applied. In this Figure 2, the first
The same reference numerals as those in the figures represent the same or corresponding parts. In this embodiment, in the conventional example, the second PIF! t (8
) is formed, and an emitter electrode (
6), and a gate electrode (9) made of metal is provided via an oxide film (5).

この実施例構成での等価回路を第3図に示しておシ、結
局、この実施例では、バイポーラトランジスタのエミッ
タ側に電界効果トランジスタを接続した構造となる。
An equivalent circuit of this embodiment is shown in FIG. 3. In the end, this embodiment has a structure in which a field effect transistor is connected to the emitter side of a bipolar transistor.

従ってこの発明によるときは、バイポーラトランジスタ
のエミッタ側に電界効果トランジスタを接続させ、その
ゲート電極に外部から任意の電圧を印加できる構成にな
っているために、過大力励振、過電圧印加時には、印加
電圧を上げエミッタ電流を減少させて、バイポーラトラ
ンジスタを破壊から守ることができ、またゲート電極へ
の印加電圧を変化させて、バイポーラトランジスタの利
得を任意に制御し得るなどの特長を有するものである。
Therefore, according to the present invention, a field effect transistor is connected to the emitter side of a bipolar transistor, and since the field effect transistor is configured to be able to apply any voltage from the outside to its gate electrode, when excessive force excitation or overvoltage is applied, the applied voltage It has the advantage that it can protect the bipolar transistor from destruction by increasing the current and decreasing the emitter current, and that it can arbitrarily control the gain of the bipolar transistor by changing the voltage applied to the gate electrode.

【図面の簡単な説明】[Brief explanation of drawings]

第1図は従来のバイポーラトランジスタの概要構成を示
す断面図、第2図はこの発明の一実施例を適用したバイ
ポーラトランジスタの概要構成を示す断面図、第3図は
第2図構成の等価回路図である。 (1)・・・・n形シリコン基板、C2)・・・・第1
のn層、(3)・・・・第1のP層、(4)・・・・第
2のn層、(5)・・・・酸化膜、(6)・・・・エミ
ッタ電極、(7)・・・・ペース電極、(8)・・・・
第2のP層、(9)・・・・ゲート電極。 代理人 葛野信−(外1名) 第1図 第2図 第3図
FIG. 1 is a sectional view showing the general structure of a conventional bipolar transistor, FIG. 2 is a sectional view showing the general structure of a bipolar transistor to which an embodiment of the present invention is applied, and FIG. 3 is an equivalent circuit of the structure shown in FIG. It is a diagram. (1)...n-type silicon substrate, C2)...first
(3)...first P layer, (4)...second n layer, (5)...oxide film, (6)...emitter electrode, (7)...Pace electrode, (8)...
Second P layer, (9)...gate electrode. Agent Makoto Kuzuno (1 other person) Figure 1 Figure 2 Figure 3

Claims (1)

【特許請求の範囲】[Claims] シリコン基板上に第1のnまたはP形溝電層を形成する
と共に、この第1のnまたはP形溝電層に相互に独立し
た第1および第2のPまたはn形溝電層を選択形成させ
、またこの第1のPまたはn形溝電層に第20ntたは
P形溝電層を形成させ、さらに前記第1のPまたはn形
溝電層にベース電極、第2のnまたはP形溝電層と第2
のPまたはn形溝電層とを接続するエミッタ電極、およ
び第2のPまたはn形溝電層の一部に酸化膜を介してゲ
ート電極を、それぞれに設けて構成したことを特徴とす
る半導体素子。
forming a first n-type or p-type dielectric layer on a silicon substrate, and selecting mutually independent first and second p- or n-type dielectric layers for the first n- or p-type dielectric layer; and forming a 20th nt or P-type trench conductor layer on the first P or n-type trench conductor layer, and further forming a base electrode on the first P or n-type trench conductor layer and a second n- or P-type trench conductor layer and second
An emitter electrode connecting the second P- or n-type trench conductor layer, and a gate electrode provided on a part of the second P- or n-type trench conductor layer through an oxide film, respectively. semiconductor element.
JP56195410A 1981-12-03 1981-12-03 Semiconductor element Pending JPS5896762A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP56195410A JPS5896762A (en) 1981-12-03 1981-12-03 Semiconductor element

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP56195410A JPS5896762A (en) 1981-12-03 1981-12-03 Semiconductor element

Publications (1)

Publication Number Publication Date
JPS5896762A true JPS5896762A (en) 1983-06-08

Family

ID=16340631

Family Applications (1)

Application Number Title Priority Date Filing Date
JP56195410A Pending JPS5896762A (en) 1981-12-03 1981-12-03 Semiconductor element

Country Status (1)

Country Link
JP (1) JPS5896762A (en)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH022665A (en) * 1987-12-22 1990-01-08 Sgs Thomson Microelettronica Spa Integrated semiconductor device and its manufacturing method

Citations (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS5276884A (en) * 1975-12-22 1977-06-28 Mitsubishi Electric Corp Semiconductor integrated circuit
JPS5333071A (en) * 1976-09-09 1978-03-28 Nec Corp Complementary type insulated gate semiconductor circuit

Patent Citations (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS5276884A (en) * 1975-12-22 1977-06-28 Mitsubishi Electric Corp Semiconductor integrated circuit
JPS5333071A (en) * 1976-09-09 1978-03-28 Nec Corp Complementary type insulated gate semiconductor circuit

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH022665A (en) * 1987-12-22 1990-01-08 Sgs Thomson Microelettronica Spa Integrated semiconductor device and its manufacturing method

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