JPS5899265A - Fault detecting circuit for thyristor device - Google Patents

Abstract

PURPOSE:To reduce non-working stop time of device significantly at fault occurring state, by a method wherein gate pulse detecting circuit for detecting pulses supplied to SCR, interface circuit for taking output of the detecting circuit to data bus and a timing circuit are installed to constitute CPU. CONSTITUTION:Each pulse of output pulse train generated from an armature gate circuit 14 is detected, a pulse detecting circuit 20 comprising a monostable multivibrator for triggering by pulse rising signal is added, and summation of gate pulse width and OFF time between pulses of the pulse train is converted into one pulse and outputted. Interface circuit 21 is provided to connect signal from the detecting circuit 20 to data bus. In this constitution, when fault occurs the information is immediately taken from a memory circuit and discriminated synthetically together with other voltage, current and operation data fault signal stored in the same sampling time, thereby fault can be detected rapidly and accurately.

Description

DETAILED DESCRIPTION OF THE INVENTION When operating a thyristor device, the present invention memorizes the operating voltage of each part of the circuit constituting the device, or the output status of electrical signals and special two-gate pulses, and retrieves it in the event of a device failure. The present invention relates to a failure detection circuit for a thyristor device which is used as means for extracting data and detecting a circuit failure.

Conventionally, as this type of thyristor control circuit, there is an analog type thyristor device that controls the speed of a motor using a thyristor, as shown in FIG.

However, in the case of this method, among the circuit elements that make up the thyristor device, the thyristor element, gate circuit,
If the amplifier section etc. breaks down, the control often has poor reproducibility, so connect a data recorder, etc. to the output of each amplifier, feedback signal, pulse signal output line, etc. and continue operation. When a failure occurs, a failure detection means is often taken, such as reproducing the recorded data connected to each line and comparing and comparing the recorded data before the occurrence of the failure with the reproduced data. However, with the recent development of data processing technology using microcomputers, as shown in Figure 2 (DDC)
Direct digital control) systems are on the verge of being put into practical use. In other words, the feature of this DDC system is the ease of data recording, and the signal data and buoyancy data of each part of the circuit are always stored in the internal memory circuit. This is a powerful advantage of gDDc operations, such as stopping the system, extracting memory data, and detecting failures.

That is, Fig. 2 shows an example of a thyristor device using a microcomputer or micro CPU that is currently in practical use. Convert to DC power by gate control, and load DC electric power 11
The second speed control is performed. 2' is the DC electric motor f
The field current is controlled by the field thyristor 6 in the field winding i2. Further, 4 is a DC voltage detection circuit applied to the DC motor 2, 5 and 6 are respectively an armature and a CT for detecting field current, 5' and 61 are armatures,
and a field current detection device, and 7 is a pulse generator (hereinafter referred to as PG) that detects the rotation speed of the electric motor m1.

Next (= 11 is the DDC circuit section, central processor unit (hereinafter referred to as CPU) 12, memory section (R
OM or RAM) 13, armature and field gate circuits 14 and 15 that generate a pulse train during the conduction period of the thyristor device 1, and outputs of the armature and field current detection devices 5' and 6'. An A/D converter 16 that converts the signal tλ/D, and a speed detector 17 that receives the output signal of the PG 7 that detects the rotation speed of the DC motor 1. DDC circuit section 11
The DDC is comprised of a signal interface circuit 18 for controlling the DDC by external commands, a data bus 19 for organically signal-coupling the respective operating functions within the DDC, and the like.

In a conventional thyristor device having such a configuration, when storing data during the operation of each part of the device, that is, DC power supply voltage, armature current, rotation speed, field current, operating status of the thyristor device, etc. The most difficult data is the presence/absence of gate pulses. The reason is that, as shown in Figure 4, in the case of DDC, the CPU section 12
1-chip microcontroller or 1-chip C for economic reasons.
If P [Jt- is adopted, ζ: is inevitably slow, so the diagnostic data necessary for failure analysis cannot be captured within a unit time, and C:, the output voltage and output voltage of the thyristor. The waveforms are shown in (a) and (b) in Figure 5.
As shown in the figure, since the waveform is a ripple waveform peculiar to a thyristor, it is necessary to take in and average as much sampling data as possible in order to faithfully store these waveform data. These two requirements give the chimpling time τ8 shown in FIG.
: Conventionally, the 1-pulse width τPl of the gate pulse train is τ2. compared to the chimpling time τ. Since there is a relationship I: <τ8, there is a drawback that information confirmation of the presence or absence of a gate pulse becomes inaccurate and the failure detection accuracy of the thyristor device decreases.

Therefore, the present invention has been made to eliminate the above-mentioned drawbacks, and by adding a simple auxiliary circuit to improve the sampling accuracy of gate pulse output, it is possible to accurately detect the presence or absence of gate pulse data. It is an object of the present invention to provide a failure detection circuit for a thyristor device that can store data.

An embodiment of the present invention will be described below with reference to the drawings.

In FIG. 6, the same parts as in FIGS. 81 to 5 are indicated by the same reference numeral t. In FIG. A pulse detection circuit consisting of a monostable multi-pie break that triggers a pulse at
Gate pulse width τ, and OFF between each pulse of the pulse train
The sum of the times τ□ is converted into one pulse and output. 2
Reference numeral 1 denotes an interface circuit that connects all signals from the pulse detection circuit 20 to the data bus.

In the present invention having such a configuration, FIG. 7 shows the main waveforms of FIG. 6. FIG. This is the output signal of the circuit 20. As shown in the figure, each pulse of each gate pulse train in the <(at diagram) is detected, and each pulse width τ is converted into the relationship τ, hτP1 + τ□. Therefore, while the gate pulse train is continuous, the output of the detection circuit 20 is The waveforms are superimposed and a pulse signal having a pulse width equal to the conduction period of the thyristor element is output.Thus, the sampling period τ8 is set to approximately -7.5 degrees in electrical angle, and the pulse signal U in FIG. 7(b)... When input to the Yt-data bus D, fist, D, through the interface circuit 21Y:, the data detected at each chimpling time is I! are faithfully converted into 111 and 161 signals.In this way, the information of the gate pulse train is converted into wide pulses and sequentially stored in the memory circuit as shown in Figure s7 (C). If this occurs (
= is another voltage immediately taken out from the information t memory circuit in FIG. 7(C) and stored at the same sampling time,
current.

Rapid and accurate failure detection can be performed by making a comprehensive judgment in conjunction with the continuous, sentence, each calculation data, and failure signal. Although the gate pulse circuit of the field thyristor is not particularly mentioned in the embodiment described herein, it is needless to say that the same concept can be applied to the gate pulse failure detection means.

Therefore, according to the present invention, failure detection in a thyristor device employing a microcomputer or the like is performed by detecting the data of each main part inside the device, as well as by detecting the presence/absence of a gate pulse and its phase information. Since data can be stored through a pulse detection circuit that uses a pull monostable multivibrator circuit, troubleshooting in the event of a failure of the thyristor device becomes easier, and the time when the device is inoperative can be significantly reduced. Moreover, the practical effects are extremely large, such as the device being able to be constructed at low cost.

[Brief explanation of drawings]

Figure 1 is a block circuit diagram of a conventional analog thyristor device; Figure 2 is a block circuit diagram of a thyristor device currently in practical use;
The figure shows the relationship between the output voltage waveform and current waveform of the thyristor and the chimpling period. Figure 6 is a block circuit diagram of a thyristor device according to an embodiment of the present invention. Figure @7 shows the gate pulse output waveform and its waveform after shaping. FIG. 3 is a diagram showing the relationship between the output waveform and stored data information and the sampling period. 1... Thyristor device, 12... CPU, 13...
・Memory, 14.15...Gate circuit, 16...A
/D converter, 20... pulse detection circuit, 21...
・Interface circuit. Note that the same reference numerals in the figures indicate the same or equivalent parts. Agent Makoto Kuzuno (and 1 other person) Houki 7th 3rd Inkyo 5th Ward 0 Diagram■

Claims (1)

[Claims] Detects the voltage, current, pulse width, etc. of the main parts of the circuit, converts it to A/D as necessary, and direct digital control circuit section C; imports the data, and detects failure of the device I:
In the thyristor device of the applied control method, a gate pulse detection circuit detects the presence or absence of each pulse of the gate pulse train applied to the thyristor and converts it into a wide pulse; and an output signal of the gate pulse non-detection circuit is taken into a data bus. an interface circuit, a CPU provided with a timing circuit that transfers an input signal taken in by the interface circuit to a memory circuit in a predetermined numbering period, and data taken into the memory circuit when a failure occurs in the previous I thyristor circuit. A failure detection circuit for a thyristor device, characterized in that a signal is extracted and used for determining failure detection.