JPS5910030A - Analog-digital converter - Google Patents
Analog-digital converterInfo
- Publication number
- JPS5910030A JPS5910030A JP11923682A JP11923682A JPS5910030A JP S5910030 A JPS5910030 A JP S5910030A JP 11923682 A JP11923682 A JP 11923682A JP 11923682 A JP11923682 A JP 11923682A JP S5910030 A JPS5910030 A JP S5910030A
- Authority
- JP
- Japan
- Prior art keywords
- voltage
- output
- conversion
- input
- digital
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
Classifications
-
- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03M—CODING; DECODING; CODE CONVERSION IN GENERAL
- H03M1/00—Analogue/digital conversion; Digital/analogue conversion
- H03M1/12—Analogue/digital converters
- H03M1/14—Conversion in steps with each step involving the same or a different conversion means and delivering more than one bit
- H03M1/145—Conversion in steps with each step involving the same or a different conversion means and delivering more than one bit the steps being performed sequentially in series-connected stages
- H03M1/146—Conversion in steps with each step involving the same or a different conversion means and delivering more than one bit the steps being performed sequentially in series-connected stages all stages being simultaneous converters
-
- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03M—CODING; DECODING; CODE CONVERSION IN GENERAL
- H03M1/00—Analogue/digital conversion; Digital/analogue conversion
- H03M1/12—Analogue/digital converters
- H03M1/34—Analogue value compared with reference values
- H03M1/36—Analogue value compared with reference values simultaneously only, i.e. parallel type
- H03M1/361—Analogue value compared with reference values simultaneously only, i.e. parallel type having a separate comparator and reference value for each quantisation level, i.e. full flash converter type
- H03M1/362—Analogue value compared with reference values simultaneously only, i.e. parallel type having a separate comparator and reference value for each quantisation level, i.e. full flash converter type the reference values being generated by a resistive voltage divider
- H03M1/365—Analogue value compared with reference values simultaneously only, i.e. parallel type having a separate comparator and reference value for each quantisation level, i.e. full flash converter type the reference values being generated by a resistive voltage divider the voltage divider being a single resistor string
Landscapes
- Engineering & Computer Science (AREA)
- Theoretical Computer Science (AREA)
- Analogue/Digital Conversion (AREA)
Abstract
(57)【要約】本公報は電子出願前の出願データであるた
め要約のデータは記録されません。(57) [Summary] This bulletin contains application data before electronic filing, so abstract data is not recorded.
Description
【発明の詳細な説明】
本発明はアナログ風圧をデジタル変換する八−り変換装
酋に関し、その目的は低分解h)のA−D変換器で一分
解能の変換を安定に実施することかできる変投方法を提
供するものである。[Detailed Description of the Invention] The present invention relates to an eight-way conversion device for converting analog wind pressure into digital data, and its purpose is to stably perform one-resolution conversion using a low-resolution A-D converter. This provides a method for changing pitches.
最近、m子オーブンレンジ、ルームエアーコンテイショ
ナ鶴の家庭粗化111ノ品ではA−D変換器内蔵倶のマ
イクロコンピュータが広く使用されている。ここで内蔵
されている6i1記A−D変換器は、高分解能のものは
高価になるなどの理由により低分計能〔通′帛、8ヒツ
ト〕のものが使用される。Recently, microcomputers with a built-in A-D converter have been widely used in microwave ovens and room air conditioners made by Tsuru. The built-in A/D converter 6i1 is of low resolution (typically 8 hits) because high resolution ones are expensive.
しかし、少しでも精度の高い制御が実行できるように、
廉価でしかも安定しf、=^分解rIrの変換器がW(
まれでいる。However, in order to be able to perform control with as much precision as possible,
An inexpensive and stable converter with f, =^ decomposition rIr is W(
It's rare.
本発明は、入力未知電圧と基準yU圧を比較してr’1
u記入力未知璽圧が向れのレベル区分に属するかを判定
し判定されたレベル区分の最低電圧を前記入力未知ψ、
圧から差引いた補正電圧を出力する演糎増幅回1薩と、
デジタル変換基準m圧入力端子にHilt)ピ基準魁圧
のうちの最低レベル区分の上限市、圧が印加され変換入
力端子に1jir記補正電圧が印加される比率変換型ア
ナログ・デジタル変換器と、前記最低市、王に相当する
N、ビット〔但し、N2は整数〕のデジタル信号を出力
するコータとを設け、前記比率変換型アナログ・デジタ
ル変換器のN1ビット〔(uし%N、?ま整数〕の変換
出力を下位側ビット出力としDI記ココー出力のN2ビ
ットを上位側ビット出力として(N十N、)ビットを変
換出力としたことを特徴とし、入力未知電圧のレベル区
分の判別と補正電圧を作ることによつて廉価な低分解能
のA−D変換器で高分解能のデジタル変換を実行するこ
とができ、まtこ、A−D変換器のデジタル変換基準電
圧入力端子には前記レベル区分の判別の際の最低レベル
区分の上限電圧を印加したため、レベルDH[:A−D
’fmllのフルスケールとが一致し、安定な動作がW
1待できるものである。The present invention compares the input unknown voltage and the reference yU pressure to determine r'1.
It is determined whether the unknown input pressure u input belongs to the corresponding level division, and the lowest voltage of the determined level division is set as the input unknown ψ,
an amplification circuit that outputs a correction voltage subtracted from the voltage;
A ratio conversion type analog-to-digital converter in which the upper limit of the lowest level division of the Hilt reference pressure is applied to the digital conversion reference m pressure input terminal, and a correction voltage of 1 jir is applied to the conversion input terminal; A coater is provided to output a digital signal of N bits [where N2 is an integer] corresponding to the lowest market and king, and a coater is provided to output a digital signal of N bits [(u and %N, ?) of the ratio conversion type analog-to-digital converter. Integer] conversion output is the lower bit output, N2 bits of the DI Coco output are the upper bit output, and (N + N,) bits are the conversion output. By creating a correction voltage, it is possible to perform high-resolution digital conversion with an inexpensive low-resolution A-D converter. Since the upper limit voltage of the lowest level classification was applied when determining the level classification, the level DH[:A-D
'fmll's full scale matches, stable operation is W
It's something you can wait for.
以下、本発明の一実施例を第1図と第2図に基づいて説
明する、
第1図は8ビツトの比率変換型A−D変換器(1)に外
部回路を付加して10ビツトの変換出力を得る場合の構
成を示す。(2)は入力未知電圧Eilが印加抗舶はR
8二R2=R3に設定されている。(4)〜(7)は反
転入力(=)に各基準電圧0ポルト% elボルト、向
ボルト、e3ホルトが印加され非反転入力(+−)に前
記入力未知電圧Einが印加されy、=演算増幅器で、
この演聯増幅脂(4)〜(7)の出力にはそれぞれEi
n、(Eirl−e+)、(Ein h)、(Ein
−es )の電圧が発生する6(8)〜αυは前記演
舞、増幅器(4)〜(7)の出力電圧ら、1ζ1、E2
、E3のレベル判定を行うコンパレータで、ここでAi
r記A−D変換器(1)のフルスケールF、S時のA−
DI換器(1)の入力電圧をEMAX(ここでEMAX
= e+ )とすると、各コンパレータ(3)〜0υ
はそれぞfI Eo < EMAX s Om El
<EMAX 、 0≦E! < E MAX %0≦
E3<EMAXを検出して出力が論理レベル“H”に股
転するよう構成されている。@〜aGは一端がそれぞれ
前記演算増幅器(4)〜(7)の出力に接続され他端相
互が接続されtこアナログ・スイッチで、このアナログ
・スイッチ0シ〜Uυはそれぞれそのレベル区分のコン
パレータ(8)〜αpの出力が両地しベルパI4”に反
転しfこ時にメイク状態となって前記A−1)変換器(
1)の入力に印加される。aoは前記コンパレータ【8
〕〜aυのうちの出力が論理レベル“H9′に反転して
いるコンパレータが属するレベル区分の酸0AIIIJ
、圧に相当する2ビツトのデジタル信号を出力するコー
タで、コンパレータ(82〜0υがそれぞれ論理レベル
“l(”に反転しTこ場合にはコーダθd出力には、基
準−;1王0 * el se! he+に相当する2
ビツトのデジタル信号として下記表の信号を出力する。Hereinafter, one embodiment of the present invention will be explained based on FIGS. 1 and 2. FIG. 1 shows a 10-bit ratio conversion type A-D converter (1) with an external circuit added. The configuration for obtaining conversion output is shown. (2) is the input unknown voltage Eil and the applied drag is R
82R2=R3. In (4) to (7), each reference voltage 0 port % el volt, direction volt, e3 volt is applied to the inverting input (=), and the input unknown voltage Ein is applied to the non-inverting input (+-), y, = With an operational amplifier,
The outputs of these amplifying fats (4) to (7) each have Ei
n, (Eirl-e+), (Ein h), (Ein
-es ) voltages 6(8) to αυ are the output voltages of the amplifiers (4) to (7), 1ζ1, E2
, a comparator that determines the level of E3, where Ai
A- at full scale F and S of A-D converter (1)
Set the input voltage of the DI converter (1) to EMAX (here, EMAX
= e+ ), each comparator (3) ~ 0υ
are respectively fI Eo < EMAX s Om El
<EMAX, 0≦E! < E MAX %0≦
The output is configured to switch to logic level "H" upon detecting E3<EMAX. @~aG is an analog switch whose one end is connected to the output of the operational amplifiers (4) to (7), and the other ends are connected to each other, and these analog switches 0~Uυ are each a comparator for that level division. (8) The outputs of ~αp are both grounded and reversed to Belpa I4'', and at this time it becomes a make state, and the converter (A-1) (
1) is applied to the input. ao is the comparator [8
]~acid 0AIIIJ of the level division to which the comparator whose output among aυ is inverted to logic level “H9’” belongs
, is a coater that outputs a 2-bit digital signal corresponding to the pressure, and the comparators (82 to 0υ are each inverted to logic level "l("). el se! 2 equivalent to he+
The signals shown in the table below are output as bit digital signals.
く表〉
領J +;l並−面列変換器で、A−I)変換器(1)
出力の8ヒツトを下位側ビット、コータQf1出力の2
ビツトを上位側ヒツトとして受は入れて、ビy ) t
t+列で変掴出力(至)を順次出力す2+ 、 fJ:
ji・、前記A−1)変拐器のデジタルに換基準紙吐入
力、には、最低レベル区分の上限値としての基準電圧e
1が印加されている。Table〉 Area J +; l Parallel - plane array converter, A-I) converter (1)
8 bits of the output are the lower bits, 2 of the coater Qf1 output
Accept the bit as the upper side person, and
Sequentially output variable grip output (to) in t+ column 2+, fJ:
ji, the above A-1) digital conversion reference paper ejection force of the capacitor, includes the reference voltage e as the upper limit value of the lowest level classification.
1 is applied.
第2図は入力米知電[Einに対する油算増幅器(4)
〜(7)の出力直圧E、〜E3を表わす。例えは人力未
知華、圧1.: i nが自≦Ein < e2の場合
、コンパレータ(引出力が反転してアナログ・スイッチ
03がメイク状麩となり、(Ein el)がA−D
f換器(1)の入力に印加されて8ビツトのデジタル信
号〔例えば“0ot)00000”〕に変換される。こ
の時、コータ01)出力は前記表から“01”となり、
並−直列変換器θカ\、
には上位ビットかう順に“0100000000”の1
0ビツトの変換出力(ト)がビット並列て入力される。Figure 2 shows the oil amplifier (4) for the input electric current [Ein].
~(7) represents the output direct pressure E, ~E3. For example, human power unknown flower, pressure 1. : If in is self≦Ein<e2, the comparator (output output is inverted and analog switch 03 becomes a makeup state, and (Ein el) becomes A-D
The signal is applied to the input of the f converter (1) and converted into an 8-bit digital signal (for example, "0ot) 00000". At this time, the coater 01) output becomes "01" from the table above,
Parallel-to-serial converter θ, 1 of “0100000000” in the order of upper bits
A 0-bit conversion output (T) is input in parallel bits.
なお、上dピ実施例では、各基準電圧o、eしe21句
と前記入力未知wI!を圧Einとを4つのIi算増幅
器(4)〜(7)を用いて同時に比較して入力未知−1
圧が伺れのレベル区分に属するかを判定したが、とJL
Cよ基準電圧を順次切換えて時分割でレベル区分の判定
を実7#4してもIfL1様の効果が得られる。In the above embodiment, each reference voltage o, e and e21 clause and the input unknown wI! is simultaneously compared with the pressure Ein using four Ii calculation amplifiers (4) to (7) to obtain the input unknown -1.
JL determined whether the pressure belongs to the level category of
The effect similar to IfL1 can be obtained even if the reference voltages are sequentially switched and the level divisions are determined in a time-sharing manner.
Jノ、l説明のように本発明のA −I)変換方法によ
ると、低分角’F (rトのA −I)変換器とわオが
の外部(ロ)路をイス1加才ろjごitで品価なハ分解
能のA−D変換と同等の変換出力が得られ、卑ν品コス
トの低廉化にjh与できる。まfこ、最低レベル区分に
おけろA−D”+2換器のテシタル変換がフルスケール
になっ1こ時には、47/’ 賞’と判定レベル区分が
1つ上のレベル区分に切換ねる動作の安定し7tコもの
であり、正確なテジタル変換が期待できるものである。According to the A-I) conversion method of the present invention as explained in J and I, the external (B) path of the low arc minute 'F (r) converter and the It is possible to obtain a conversion output equivalent to A-D conversion with a low resolution and low price, and contribute to lowering the cost of low-quality products. In the lowest level division, when the digital conversion of the A-D"+2 converter reaches full scale, 47/'Award' and the judgment level division switches to the next higher level division. It is stable and has a capacity of 7 tons, so accurate digital conversion can be expected.
H41図は本発明のA−Ds換方法の具体的な一実施例
の構成図、第2図は第1図の入出力特性図である。
(1)・・・比菫変換型A −Ll変換器、(3)・・
・定市圧喧蝕、(4)〜(7)・・・11ν1Φ#l藷
、(+’l)〜0υ・・・コンパレータ、叩〜OQ・・
・アナロ゛グ・スイッチ、θG・・・コーグ、Ein゛
°“入力未知附圧
代地人 森木義弘FIG. H41 is a block diagram of a specific embodiment of the A-Ds conversion method of the present invention, and FIG. 2 is an input/output characteristic diagram of FIG. 1. (1)... Violet conversion type A-Ll converter, (3)...
・Standard pressure noise, (4)~(7)...11ν1Φ#l藷, (+'l)~0υ...Comparator, hit~OQ...
・Analog switch, θG...Korg, Ein゛°"Input unknown pressure agent Yoshihiro Moriki
Claims (1)
電圧が伺れのレベル区分に属するかを判定し判定された
レベル区分の最低電圧を前記入力未知電圧から差引い1
こ補正電圧を出力する演騨増幅回路と、デジタル変換基
準電圧入力端子に前記基準電圧のうちの最低レベル区分
の上限V圧が印加され変換入力端子に前記補正電圧が印
加される比率変換型アナログ・デジタル変換器と、前記
最低電圧に相当するN、ビット〔但し、N2は整数〕の
デジタルf言号を出力するコーグとを設け、O1I記比
率変換型アナログ・デジタル変換器のN1ヒーノト((
F L−N+は整数〕の変換出力を下位側ビット出力と
しOil記コーダ出力のN、ビットを上位側ビット出力
として(N+Nz)ビ・ソトを変換出力としf: A
−D髪換装瞳。[Claims] 1. Comparing the human power unknown voltage with a reference voltage to determine whether the human power unknown voltage belongs to a given level classification, and subtracting the lowest voltage of the determined level classification from the input unknown voltage by 1.
a ratio conversion type analog circuit in which the upper limit V voltage of the lowest level division of the reference voltages is applied to the digital conversion reference voltage input terminal and the correction voltage is applied to the conversion input terminal;・Provide a digital converter and a cog that outputs a digital f-word of N bits [however, N2 is an integer] corresponding to the minimum voltage, and convert the N1 heanote (((
F L-N+ is an integer] with the conversion output as the lower bit output, and the N bit of the oil coder output as the upper bit output, and (N+Nz) BiSoto as the conversion output f: A
-D hair replacement eyes.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP11923682A JPS5910030A (en) | 1982-07-08 | 1982-07-08 | Analog-digital converter |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP11923682A JPS5910030A (en) | 1982-07-08 | 1982-07-08 | Analog-digital converter |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPS5910030A true JPS5910030A (en) | 1984-01-19 |
Family
ID=14756328
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP11923682A Pending JPS5910030A (en) | 1982-07-08 | 1982-07-08 | Analog-digital converter |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPS5910030A (en) |
Citations (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS5235968A (en) * | 1975-09-16 | 1977-03-18 | Sony Corp | Analog digital convertor |
| JPS5623026A (en) * | 1979-08-03 | 1981-03-04 | Nec Corp | Analog-digital conversion unit |
| JPS5693426A (en) * | 1979-12-27 | 1981-07-29 | Toshiba Corp | Analogue-digital converter |
-
1982
- 1982-07-08 JP JP11923682A patent/JPS5910030A/en active Pending
Patent Citations (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS5235968A (en) * | 1975-09-16 | 1977-03-18 | Sony Corp | Analog digital convertor |
| JPS5623026A (en) * | 1979-08-03 | 1981-03-04 | Nec Corp | Analog-digital conversion unit |
| JPS5693426A (en) * | 1979-12-27 | 1981-07-29 | Toshiba Corp | Analogue-digital converter |
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