JPS5910090B2 - Output driver circuit - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention relates to an improvement in an output driver circuit that realizes three-state outputs: high level, low level, and high impedance.

Next, an example of a conventional output driver circuit will be explained with reference to FIG.

Here, each transistor will be explained as a P-channel MOS type, but the explanation is the same for an N-channel MOS type, except that the potentials are reversed.

Further, state A is a state in which a signal can be transmitted, and state B is a state in which the output impedance is high.

That is, in the figure, a load transistor Q and a drive transistor Q1.

The inverter circuit, which is composed of both enhancement-type elements, is driven by a depletion-type load transistor Q.
The load transistor Q3 is a depletion type element operated by the input signal IN of the drive transistor Q2 which is an enhancement type element connected in series with the drive transistor Q2 which is an enhancement type element connected in series with the drive transistor Q2. ，
A first drive circuit consisting of a load transistor Q6, which is also a depletion type element, and a second drive circuit consisting of a drive transistor Q7tQ8, which is also an enhancement type element, and the voltage VDD is increased as shown in the figure.
, vss is applied and the drive transistor Q, ,
Q. A first signal E is applied to.

In such an output driver circuit, state B, that is, the transistors forming the inverter circuit') Q9
- In order to realize the case where both Qto are in the off state, the first signal E is set to a low level and the transistor Q9 is turned off.
The potential applied to the gate of tQto needs to be at a high level.

At this time, transistors Q3, Q. , the transistor Q. of the second drive circuit. , Q. A steady current flows through the route of the transistor Q. When the input signal IN is 0, the transistor Q. , Q2 also flows through the routes, so the current consumption is at its maximum.

In state A, depending on the value of IN, a steady current flows through the routes of transistors Q3 and Q4 of the first drive circuit and transistors Q6 and Q7 of the second drive circuit, or a steady current flows through the routes of transistors Q1 and Q2 and the routes of transistors Q6 and Q7 of the second drive circuit. Since it depends on which of the routes of the transistors Q6 and Q7 the current flows, more current consumption flows in state B than in state A, and in this circuit example, it is approximately twice as much.

In other words, the current consumption is maximum when the output impedance is high, and when multiple such circuits are used and the number of output terminals increases, problems such as heat generation and an increase in the capacity of the power supply occur. .

The present invention has been made in view of the above drawbacks, and aims to eliminate the above drawbacks by reducing current consumption in a state where the output impedance is high, and further improve circuit characteristics.

Next, one embodiment of the output driver circuit of the present invention will be described with reference to FIG.

Here, each transistor will be explained as a P-channel MOS type, but the explanation is the same for an N-channel MOS type, only that the potentials are reversed.

Further, the state in which signals can be transmitted is state A, and the state in which the output impedance is high is state B, and transistors are indicated by the same reference numerals.

That is, in the figure, the inverter circuit in which the load transistor Q9 and the drive transistor Q1o are both made up of enhancement type elements is driven by the input signal IN of the drive transistor Q2 made of an enhancement type element connected in series with the depletion type load transistor Q1. The load transistor Q3 is a depletion type element that operates; the drive transistor Q3 is an enhancement type element; , Q, and a second drive circuit consisting of a load transistor Q6, which is also a depletion type element, and drive transistors Q7 and Q8, which are enhancement type elements, as shown in the figure. ss is applied and the drive transistors Q, , Q. A common first signal E is applied to the gates of the load transistors Q3 and Q6, and the first signal E is applied to the gates of the load transistors Q3 and Q6.
A second signal E, which is an inversion of the signal E, is applied.

In such an output driver circuit, in state A, the mutual conductance fim of the load transistors Q3 and Q6 should be large in order to speed up signal transmission, and in state B, the gate potential of the inverter transistors Q9 e Qto should be maintained. Focusing on the point that only the load transistors Q3, Q. This is characterized in that current consumption is reduced by changing the gate potential of the first signal E by a second signal E obtained by inverting the first signal E.

In this embodiment, the current consumption in state A is almost the same as that of the conventional example, but in state B it is reduced to about 1/6.

Transistor Q3 in state A in this circuit. Since the gate potential of Q6 is lower than that of conventional circuits and gm is large, the size of the transistor can be reduced to allow the same amount of current to flow, which is advantageous in terms of design.

In addition, since the capacitive load on the signal lines for the first signal E and the second signal E is reduced, the transmission time of the signals E and E, that is, the transition time between state A and state B is shortened. arise.

Note that ■ss and ■DD indicate the power supply voltage, and P-
In the case of a channel MOS type element, ■ss>■DD.

FIG. 4 shows an example in which the circuit of the present invention is applied to a bidirectional multiple input/output type driver, and in this circuit diagram, the circuit of FIG. 2 is indicated by the symbols of FIG. 3.

This driver takes the following four states by changing the control signals E1 and E2.

However, "0" is a level, and "1" is a high level.

? When using the previous circuit, E1='''0'', E 2
−=? +011, both directions are in state B and the current consumption increases, but when using the circuit of the present invention, E=
゛Q 11, E22゛1'' or E12tl l
ll,E2241 0? The maximum value is +, and the value decreases to about 173 compared to the conventional example.

- As is clear from the above, in the output driver circuit of the present invention, the current consumption is reduced to a fraction of that of the conventional example which can provide the same output current.

In state A, the voltage applied to the gate of the load transistor is low and the mutual conductance is large, so the size of the transistor can be reduced.

Further, the capacitive load of the signals E and E is reduced, and the transition time between state A and state B is shortened, so that it is extremely effective in practical use.

[Brief explanation of the drawing]

FIG. 1 is a wiring diagram of an example of a conventional output driver circuit, FIG. 2 is a wiring diagram of an embodiment of an output driver circuit according to the present invention, and FIG. 3 is a symbolic diagram showing the circuit of FIG. 2. 4
The figure is a wiring diagram when the circuit of the present invention is applied to a bidirectional multiple input/output type driver. Q. , Q2, Q3...Depression type MOS
Transistors, Q2-Q. ．． (Excluding Q3 and Q.<)...
...Enhancement type MOS} transistor.

Claims (1)

[Claims] 1. An inverter circuit in which a first load transistor and a first drive transistor are connected in series through a first circuit point and both are configured with enhancement type elements, and a second depletion type load transistor and a first drive transistor are connected in parallel with each other. a first drive circuit in which second and third enhancement-type drive transistors are connected in series via a second circuit point; a third depletion-type load transistor and an enhancement-type third load transistor connected in parallel with each other; and a second drive circuit in which the fourth and fifth drive transistors are connected in series through a third circuit point, and the third circuit point is an input terminal of the first load transistor and the third drive transistor. and in the output driver circuit, the second circuit point is connected to the input terminal of the first drive transistor, and the input terminal of the fifth drive transistor and the first circuit point are the input terminal and the output terminal, respectively. , a common first signal is applied to the input terminals of the second and fourth drive transistors, and a second signal obtained by inverting the first signal is commonly applied to the input terminals of the second and third load transistors. An output driver circuit characterized in that the output driver circuit is configured to apply a voltage to the output driver.