JPS59103408A - Muting device - Google Patents

Abstract

PURPOSE:To avoid time delay by turning on a transistor (TR) switch circuit by the potential difference between a power supply voltage and an output of an integration circuit and turning on a muting TR with the output at the on/off of the power supply voltage. CONSTITUTION:The integration circuit comprising a resistor 4, a diode 5, and a capacitor 6 is provided between a power supply input terminal 1 and ground and a base is onnected to a connecting point between the resistor 4 and the diode 5 via a resistor 7. The device is formed by the TR8 whose emitter is connected to the power input terminal and the TR9 whose emitter is connected between the diode 5 and the capacitor 6 of the integration circuit, whose collector is connected to the collector of the TR8. Then, the muting is applied without time delay and the time constant at the power supply on/off is decided by one integration circuit.

Description

[Detailed Description of the Invention] Industrial Application Fields 2. The present invention relates to a muting device that can prevent shock noise generated when power is turned on and off. Problem Generally, electronic devices usually generate shock noise due to the instantaneous application of a large power supply voltage when the power switch is turned on or off.

Therefore, when the power is turned on and off, muting is applied to the signal path using a time signal determined by a time constant circuit. however.

Conventional muting circuits for electronic devices use a one-time constant circuit and a relay, and are configured to turn on the relay after an arbitrary time constant has elapsed after the power is turned on, resulting in slow operation time. was there.

OBJECTS OF THE INVENTION An object of the present invention is to provide a muting device that can mute a signal path without time delay when power is turned on or off.

3-.-J Structure of the Invention The muting device of the present invention is composed of an integrating circuit, a transistor switch circuit, and a muting transistor switch provided in a signal path. The transistor switch circuit is turned on by the potential difference generated between the power supply voltage and the integration circuit.

The muting transistor switch is turned on by the output of the transistor switch circuit.

DESCRIPTION OF EMBODIMENTS FIG. 1 shows an embodiment of the muting device of the present invention, in which 1 is a power input terminal, 2 is a signal output terminal, and 3 is a muting device according to an embodiment of the present invention.
is a signal input terminal, and an integrating circuit 13 having a resistor 4, a diode 5, and a capacitor 6 connected in series is inserted between the power supply input terminal 1 and the ground. 14 is a transistor switch circuit whose base is connected to the first output terminal of the integrating circuit 13 (that is, the connection point between the resistor 4 and the diode 5) via the resistor 7, and whose emitter is connected to the power input terminal 1. a first PNP) transistor 8 whose base is connected to the first output terminal of the integrating circuit 13;
A second PNP transistor 9 whose emitter is connected to the second output terminal of the integrating circuit 13 (i.e., the connection point between the diode 5 and the capacitor 6) and whose collector is connected to the collector of the first PNP transistor 8. It is made up of. 15 is a muting transistor switch consisting of an NPN transistor 11 whose emitter is grounded;
NP) transistors 8 and 9, and the collector thereof is connected to one end of a resistor 12 inserted between the signal input/output terminals 2 and 3.

In such a configuration, when the power is turned on, the voltage at the power input terminal 1 changes as shown at time TIvc in FIG. 2. As a result, the output point of the integrating circuit 13 consisting of the resistor 4, diode 5, and capacitor 6 is the resistor 4 and diode 5. , - The voltage at the connection point of the wire 5 changes as shown in FIG. 2B. The output of this integrating circuit 13 is passed through the resistor 7 to the first PN
By applying an error to the base of the P transistor 8, the transistor switch circuit 14 constituted by the first PNP transistor 8 and the resistor 7 is turned on.

The output of this transistor switch circuit 14 is connected to the resistor 10.
The signal is supplied to a muting transistor switch 15 composed of a transistor 11, and muting is turned on as shown in FIG. 2C.

Due to this muting-on, the signal applied to the signal input terminal 3 is divided by the on-resistance between the resistor 12 and the collector-emitter of the transistor 11, and the signal applied to the signal input terminal 3 is divided by the on-resistance between the resistor 12 and the collector-emitter of the transistor 11,
is output to. At this time, since the on-resistance between the collector and emitter of the transistor 11 is low, no signal appears at the signal output terminal 2.

Further, the muting-on time interval is determined by the time constant of the integrating circuit 13.

On the other hand, when the power is turned off, the voltage at the power input terminal 1 changes as shown at time T2 for one person in FIG.

6be, -2' As a result, the diode 5 which is the output point of the integrating circuit 13 consisting of the resistor 4, diode 6 and capacitor 6
The voltage at the connection point between the capacitor 6 and the capacitor 6 changes as shown in FIG. 2B. The output of this integrating circuit 13 is the second PNP)
By being applied to the emitter of the transistor 9, the transistor switch circuit 14 made up of the resistor 4 and the second PNP transistor 9 is turned on. The output of this transistor switch circuit 14 is supplied to a muting transistor switch 15 composed of a resistor 10 and a transistor 11, and muting is turned on as shown in FIG. 2C. Due to this muting-on, the signal applied to the signal input terminal 3 is voltage-divided by the on-resistance between the resistor 12 and the collector-emitter of the transistor 11, and is output to the signal output terminal 2. At this time, since the on-resistance between the collector and emitter of the transistor 11 is low, no signal appears at the signal output terminal 2.

Note that when the muting switch is off, the off-resistance 7B between the collector and emitter of the transistor 11 is high and does not affect the signal at all.

Effects of the Invention As described above, according to the present invention, muting can be applied to the output signal path with almost no time delay when the power is turned on or off, and muting can be applied to the output signal path with almost no time delay when the power is turned on or off. It has the advantage that the time constant can be determined both during the off-time and off-time.

[Brief explanation of drawings]

FIG. 1 is a circuit diagram showing an embodiment of the muting device of the present invention, and FIG. 2 is an operation timing diagram of the same device. 1...Power input terminal, 2...Signal output terminal, 3°°...Signal input terminal, 13...
Integrating circuit, 14...Transistor circuit, 15...
...Transistor switch for muting. Name of agent: Patent attorney Toshio Nakao and one other person. Figure 1/j Figure 2

Claims (1)

[Claims] An integrating circuit including a first resistor, a diode, and a capacitor connected in series, and a first... The transistor switch circuit includes a transistor switch circuit including a second transistor and a second resistor, and a muting transistor switch including a third transistor and a third resistor operated by the output of the transistor switch circuit. a muting device configured to turn on the transistor switch circuit by a potential difference generated between the power supply voltage and the integration circuit when the transistor is turned on or off, and turn on the muting transistor switch by the output of the transistor switch circuit. .