JPS5911210A - Manufacture of ceramic substrate - Google Patents

Manufacture of ceramic substrate

Info

Publication number
JPS5911210A
JPS5911210A JP9933983A JP9933983A JPS5911210A JP S5911210 A JPS5911210 A JP S5911210A JP 9933983 A JP9933983 A JP 9933983A JP 9933983 A JP9933983 A JP 9933983A JP S5911210 A JPS5911210 A JP S5911210A
Authority
JP
Japan
Prior art keywords
ceramic
sheet
wiring
board
circular
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP9933983A
Other languages
Japanese (ja)
Inventor
寛治 大塚
元 村上
英治 山本
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Hitachi Ltd
Original Assignee
Hitachi Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Hitachi Ltd filed Critical Hitachi Ltd
Priority to JP9933983A priority Critical patent/JPS5911210A/en
Publication of JPS5911210A publication Critical patent/JPS5911210A/en
Pending legal-status Critical Current

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Abstract

(57)【要約】本公報は電子出願前の出願データであるた
め要約のデータは記録されません。
(57) [Summary] This bulletin contains application data before electronic filing, so abstract data is not recorded.

Description

【発明の詳細な説明】 本発明はセラミック基板の製造法に関するもので、主と
してデジタル腕時計に用いるセラミック多層配線基板の
製造法な対象とするものである。
DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a method for manufacturing a ceramic substrate, and is mainly directed to a method for manufacturing a ceramic multilayer wiring board used in a digital wristwatch.

一般にIC(集積回路装置)に用いる配線基板は、未焼
成セラミツクシート上面に高融点金属からなる導体ペー
ストを印刷した種々の配線シートを数枚種層し、1これ
を一体として焼成して多数個分のセラミック多層配線基
板を形成し、上記基板表面に露出する配線層に対してメ
ッキを施し、然る後各塙板な区別する縦横の境界線に沿
って直線状の分離溝を形成し、この線に沿って個々の方
形の配線基板に切断分離することにより形成する。
In general, wiring boards used in ICs (integrated circuit devices) are made by layering several different wiring sheets with conductor paste made of high-melting point metal printed on the top surface of unfired ceramic sheets, and then firing them as one piece to create a large number of wiring boards. forming a ceramic multilayer wiring board, plating the wiring layer exposed on the surface of the board, and then forming linear separation grooves along the vertical and horizontal boundaries that distinguish each board; It is formed by cutting and separating into individual rectangular wiring boards along this line.

ところで、デジタル腕時計は円形のセラミ、ンク配線基
板が用いられるが、このような円形セラミック配線基板
は、焼成後セラミ・ンクシートを各基板に分割する分離
溝に沿って切断分離しようとしても分離溝が曲線である
ため、切断応力がこの溝に集中しにくくウニ・・を損傷
することなく切断分離することは困難である。したかつ
て、一般には未焼成シートの状態で打抜き切断により切
断分離し各独立した円形の基板に形成していた。
By the way, a circular ceramic wiring board is used for digital watches, but even if you try to cut and separate such a circular ceramic wiring board after firing along the separation grooves that divide the ceramic sheet into each board, the separation grooves will not work. Since the groove is curved, cutting stress is difficult to concentrate in this groove, making it difficult to cut and separate the sea urchin without damaging it. In the past, the unfired sheet was generally cut and separated by punching and cutting to form individual circular substrates.

しかし、未焼成セラミツク配線基板の状態で独立した基
板にし7た場合には、その後の焼成及びメッキ処理等の
作柴は各基板がばらばらになっていることから、一体で
同時に処理かできず、また。
However, if the unfired ceramic wiring board is made into independent boards, the subsequent firing and plating processing cannot be done at the same time since each board is separated. Also.

処理を施すのに、ばらばらなものを一旦整列してから行
う必要があり工程が複雑になる。%に配線層へのメッキ
処理は電気メッキが困難で無電解メッキ法によらなけれ
ばならず、メッキ作業が複雑になる。
In order to perform the treatment, it is necessary to arrange the pieces in a row, which complicates the process. %, electroplating is difficult and electroless plating must be used to plate the wiring layer, which complicates the plating process.

また、上記製造法の場合には、各基板の各配線層が独立
していることから、断線、ショートの検査が煩雑になり
、焼成及びその後の処理も一つ−・つ個別に行なわれる
ことから、玉数が大幅にかかるという問題があった。
In addition, in the case of the above manufacturing method, since each wiring layer of each board is independent, inspection for disconnections and short circuits becomes complicated, and firing and subsequent processing are also performed individually. Therefore, there was a problem that the number of balls required was large.

本発明の目的は、1つのセラミックシートから1り「定
形状を有する複数のセラミック基板を容易に形成するこ
とができるセラミック基板の製造法を提供するものであ
る。
An object of the present invention is to provide a method for manufacturing a ceramic substrate that can easily form a plurality of ceramic substrates having a fixed shape from one ceramic sheet.

一ヒ記目的を達成¥るための本発明の基本構成は、1つ
のセラミックシートを、縦横の直線状境界線に沿って分
離させることによって、複数の所定形状の基板を形成′
1−るセラミック基板の製造法において、前記接散の所
定形状の基板に分離されるべき未焼成セラミック7−川
・を用意し、該未焼成セラミツクシー トに、前記縦横
の直線状境界線とは一致1〜ない線に沿って前記所定形
状の一部が規定されるように打抜き穴を形成し、しかる
後、前記シートを焼成し、前記縦横の直線状境界線に沿
って複数の所定形状の基板に分離することを特徴とする
The basic structure of the present invention for achieving the above objects is to form a plurality of substrates with predetermined shapes by separating one ceramic sheet along vertical and horizontal straight boundary lines.
1. In the method for manufacturing a ceramic substrate according to the present invention, an unfired ceramic sheet to be separated into the dispersed substrates of a predetermined shape is prepared, and the vertical and horizontal linear boundary lines and forming punched holes so that a portion of the predetermined shape is defined along lines 1 to 2, and then firing the sheet to form a plurality of predetermined shapes along the vertical and horizontal linear boundaries. It is characterized by being separated into two substrates.

以下本発明の一実施例を図面を参照しなから鉢体的に説
明する。
An embodiment of the present invention will be described below with reference to the drawings.

第1図は本発明デジタル時計用の円形状セラミック配線
裁板の製造を工程順に示したものである。
FIG. 1 shows the manufacturing process of a circular ceramic circuit board for a digital watch according to the present invention.

tal  グリーンシート(未焼成セラはツク7−ト)
を数枚用意する。これらソートには必要に応じて円形又
は方形の孔を形成する。各シートの表面にW、Mo等の
ごとき高融点金属ペーストを印刷塗布してそれぞれ所定
のパターンの配線層を形成し、これらシートを積層して
未焼成セラミック配線シート1を作る。
tal green sheet (unfired cera is 7-t)
Prepare several sheets. For these sorts, circular or square holes are formed as necessary. A high-melting point metal paste such as W, Mo, etc. is printed and coated on the surface of each sheet to form a wiring layer in a predetermined pattern, and these sheets are laminated to form an unfired ceramic wiring sheet 1.

この未焼成セラミツク配線シート1は形成しようとする
円形の基板2が隣り合う円形基板と相互に接し、かつ各
基板が縦横の直線X、yで区分される領域内に配INさ
れるように各基板を形成1−る。
This unfired ceramic wiring sheet 1 is arranged so that the circular substrates 2 to be formed are in contact with adjacent circular substrates, and each substrate is arranged in an area divided by vertical and horizontal straight lines X and y. Forming the substrate 1-.

各円形基板2が形177される位置には1例えば。For example, in the position where each circular substrate 2 is shaped 177.

電池を収納する円形の四部3、LSI(大集積回路装置
)を取付ける方形の四部4.コンデンサを取1勺けるコ
ンデンサ取付配線部5、水晶発振子を取付ける発振子取
付配線部6がそれぞれ形成される。
Four circular parts 3 for housing the battery, four square parts for mounting the LSI (Large Integrated Circuit Device) 4. A capacitor attachment wiring section 5 for attaching a capacitor and an oscillator attachment wiring section 6 for attaching a crystal oscillator are formed, respectively.

なお、各円形基板の表面に露出する配線層及び内部配線
層はシート1内部の配線層を介して相互に接続し、さら
にシート側部表面に配設された共通のメッキ用電極配線
層7に接続している。
The wiring layers and internal wiring layers exposed on the surface of each circular board are connected to each other via the wiring layer inside the sheet 1, and are further connected to a common plating electrode wiring layer 7 provided on the side surface of the sheet. Connected.

(bl  次に打抜き切断により円形基板2が残存する
ように不良部分を除去する。この時、形成しようとする
各円形基板が相互にWi、横に接続して連結するように
する。
(bl) Next, the defective parts are removed by punching and cutting so that the circular substrate 2 remains. At this time, the circular substrates to be formed are connected to each other laterally.

(c+  次に各基板毎に分離切断−1−るため、相互
に接する各基板間の表面に直線状の分離溝8を前記X。
(c+ Next, in order to separate and cut each substrate -1-, a linear separation groove 8 is formed on the surface between the mutually contacting substrates as described above.

yにそって形成する。なお、この分離溝を形成しても各
円形紙板2は、分離溝8が形成されている連結部のシー
ト内部の配線層により電気的にも接続されている。
Form along y. Note that even if this separation groove is formed, each circular paper board 2 is still electrically connected by the wiring layer inside the sheet at the connecting portion where the separation groove 8 is formed.

その後、この積層シート1を13ooc〜1.700C
で焼成し、未焼成積層セラミックシートを焼成種層セラ
ミックンートにする。
After that, this laminated sheet 1 was heated to 13ooc to 1.700C.
The unfired laminated ceramic sheet is fired to form a fired seed layer ceramic sheet.

fdl  積層シート1のメッキ用電極配線層7をメッ
キ用電極の一電一として電気メツキ法により積層シート
1表面に露出する配線層表面に例えばAuメッキを施す
fdl Using the plating electrode wiring layer 7 of the laminated sheet 1 as a plating electrode, the surface of the wiring layer exposed on the surface of the laminated sheet 1 is plated with, for example, Au by electroplating.

このメッキにより露出する配線層がメッキされない部分
があるときは、その配線層はメッキ用電極層7に接続さ
れてないことを示すものであり断線であることが!+)
明できる。したがって、このメッキ処理により積層シー
トの検査を同時に行な得る。
If there is a portion of the wiring layer exposed by this plating that is not plated, this indicates that the wiring layer is not connected to the plating electrode layer 7 and may be a disconnection! +)
I can explain. Therefore, by this plating process, the laminated sheet can be inspected at the same time.

(e+  その後各基板2毎に分離切断する分離溝8に
沿って、切断応力を加えて分離し円形セラミック配線基
板を得る。
(e+) Thereafter, each substrate 2 is separated by applying cutting stress along the separation groove 8 to obtain a circular ceramic wiring board.

なお、各基板毎に分離切断する直線状分離溝8は、積層
シートを焼成後の分離切断前にダイヤモンドカッタでけ
がいて形成するようにしてもよいっ本発明によれば、1
つのセラミックシートを未焼成セラミツクシートの状態
であらがじめ外形打抜きをし、焼成後打抜き穴を利用し
て切断分離するので、1r定形状を有する複数のセラミ
ック柄抜を容易罠かつ損傷なく形成することかできる。
Note that the linear separation grooves 8 to be separated and cut for each substrate may be formed by cutting the laminated sheet with a diamond cutter before separating and cutting the laminated sheet after firing.
Two ceramic sheets are pre-punched in an unfired ceramic sheet state, and after firing they are cut and separated using the punched holes, so multiple ceramic patterns having a 1R regular shape can be easily formed without any trapping or damage. I can do something.

また、上記実施例で説明したような本発明によれば、未
焼成セラミツクシートの状態であらかじめ外形打抜きし
て不要な部分を取除いて形成しようとする円形基板が直
線で分割できるようにしておき、その後焼成することか
ら、焼成後単に各基板が接している直線状接線に沿って
分離切断することにより形成しにくい円形画板を容易に
形成することがでる。
Further, according to the present invention as explained in the above embodiment, the circular substrate to be formed can be divided along straight lines by punching out the external shape of the unfired ceramic sheet and removing unnecessary parts. Since the substrate is then fired, it is possible to easily form a circular drawing board, which is difficult to form, by simply separating and cutting the substrates along the linear tangents that are in contact with each other after firing.

また1本発明によれば、最終工程まで各基板を電気的機
械的に接続しておくから、焼成及びメッキ処理、その他
の処理を一体の状態で処理でき。
Furthermore, according to the present invention, since each substrate is electrically and mechanically connected until the final process, firing, plating, and other treatments can be performed in an integrated state.

これらの処理作業が極めて簡単になる。特に配線層への
メッキ処理は電気メッギ法によりメッキを施Tことがで
きる。Lうになりメッキ作業を極めて簡単にすることが
できる。
These processing operations become extremely simple. In particular, plating on the wiring layer can be performed by electroplating. This makes the plating work extremely easy.

さらに本発明は基板の配線層の検査も一体になった状態
で検査を行なわれるから、配線層の断線。
Furthermore, in the present invention, the wiring layer of the board is inspected in an integrated state, so there is no possibility of disconnection in the wiring layer.

ショートの検査か容易になり、検査作業工数の大幅な低
減が図れる。
It becomes easier to inspect for short circuits, and the number of inspection work steps can be significantly reduced.

第2図は本発明の池の実施例である。FIG. 2 is an embodiment of the pond of the present invention.

この場合、相互に接する各基板間の間隔を広くして、各
基板間を接続する配線層を設けや1″り構造したもので
ある。この場合には各基板に分離切断するための分離溝
8は平行して二本形成する必要かある。
In this case, the spacing between the boards in contact with each other is widened, and a wiring layer is provided to connect each board.In this case, a separation groove is provided to separate and cut each board. Is it necessary to form two pieces of 8 in parallel?

上記実施例においては、いずれも円形セラミック配線基
板の製造法を説明したが1円形基板に限らず、一般に曲
面を有1−るセラミック基板の製造をする場合にも同様
な方法で製造できるものである。
In the above embodiments, the method of manufacturing a circular ceramic wiring board was explained, but the same method can be used to manufacture not only a circular board but also a ceramic board having a curved surface in general. be.

才だ1本発明はセラミック配線基板に限らず。This invention is not limited to ceramic wiring boards.

配線層がない拳なるセラミンク基板の製造の場合にも適
用できるものである。
It can also be applied to the production of ceramic ceramic substrates that do not have wiring layers.

【図面の簡単な説明】[Brief explanation of the drawing]

第1図は本発明の一実施例を示したもので、(a1〜i
elは各工程の平面図、第2図は本発明の池の実施例の
一工程の平面図である。 1・・・配線シート、2・・・円形基板、3・・・凹部
、4・・・T、 S I取付凹部、5・・・コンデンサ
取付配線部。 6・・・発撮子取付配線部、7・・・メッキ用電極配線
層、8・・・分離溝。 第  1  図 第  1  図 第  1  図 第2図
FIG. 1 shows an embodiment of the present invention, in which (a1 to i
el is a plan view of each step, and FIG. 2 is a plan view of one step of the embodiment of the pond of the present invention. DESCRIPTION OF SYMBOLS 1... Wiring sheet, 2... Circular board, 3... Recessed part, 4... T, SI mounting recessed part, 5... Capacitor mounting wiring part. 6... Shooter attachment wiring section, 7... Electrode wiring layer for plating, 8... Separation groove. Figure 1 Figure 1 Figure 1 Figure 2

Claims (1)

【特許請求の範囲】[Claims] 1つのセラミックシートを、縦横の直線状境界線に沿っ
て分離させることによって、複数の所定形状の基板を形
成するセラミック基板の製造法において、前記複数の所
定形状の基板に分離されるべき未焼成セラミツクシート
を用意し、該未焼成セラミツクシートに、前記縦横の直
線状境界線とは一致しない線に沿って前記所定形状の一
部が規定されるように打抜き穴を形成し、しかる後、前
記シートを焼成し、前記縦横の直線状境界線に沿って複
数のり「定形状の基板に分子11することを特徴とする
セラミック基板の製造法。
In a method for manufacturing a ceramic substrate in which a plurality of substrates having a predetermined shape are formed by separating one ceramic sheet along linear boundary lines in the vertical and horizontal directions, an unfired material to be separated into the plurality of substrates having a predetermined shape; A ceramic sheet is prepared, and a punched hole is formed in the unfired ceramic sheet so that a part of the predetermined shape is defined along a line that does not coincide with the vertical and horizontal linear boundary lines. A method for manufacturing a ceramic substrate, characterized in that a sheet is fired, and a plurality of molecules are formed into a regular-shaped substrate along the vertical and horizontal linear boundaries.
JP9933983A 1983-06-06 1983-06-06 Manufacture of ceramic substrate Pending JPS5911210A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP9933983A JPS5911210A (en) 1983-06-06 1983-06-06 Manufacture of ceramic substrate

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP9933983A JPS5911210A (en) 1983-06-06 1983-06-06 Manufacture of ceramic substrate

Publications (1)

Publication Number Publication Date
JPS5911210A true JPS5911210A (en) 1984-01-20

Family

ID=14244864

Family Applications (1)

Application Number Title Priority Date Filing Date
JP9933983A Pending JPS5911210A (en) 1983-06-06 1983-06-06 Manufacture of ceramic substrate

Country Status (1)

Country Link
JP (1) JPS5911210A (en)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS60226074A (en) * 1984-04-25 1985-11-11 Sony Corp Time code correcting circuit

Citations (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS4830653A (en) * 1971-08-23 1973-04-23
JPS4930991U (en) * 1972-06-20 1974-03-16

Patent Citations (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS4830653A (en) * 1971-08-23 1973-04-23
JPS4930991U (en) * 1972-06-20 1974-03-16

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS60226074A (en) * 1984-04-25 1985-11-11 Sony Corp Time code correcting circuit

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