JPS59112332A - Transmitting device of data - Google Patents

Abstract

(57) [Summary] This bulletin contains application data before electronic filing, so abstract data is not recorded.

Description

DETAILED DESCRIPTION OF THE INVENTION Field of the Invention The present invention relates to a data transmission device for transmitting data between a center and a terminal, and a data transmission device for transmitting data from a terminal device to a center without using an arithmetic processing unit in the terminal bag. This relates to a transmission device.

Prior Art and its Problems When a terminal has an input device such as a keyboard and input data is transmitted to a center, the terminal device is also provided with an arithmetic processing unit (hereinafter referred to as MPU). FIG. 1 shows an example of such a conventional terminal device. In this figure, a keyboard 1 having a maximum of 8×8 key switches connected in a matrix is connected to a keyboard/display interface LSI (hereinafter referred to as /D-LSI) 2. Keyboard 1/D-LSI
It is driven by the output of a 3-8 decoder 3 which decodes the binary signals at the output terminals SLO to SL3 of the digital LSI 2 into 8-bit parallel data, and the switch input is applied to the data input terminal PLO-RL7 of the digital LSI 2. K/D-LSI
2 converts data input from the keyboard 1 into 8-bit parallel data. Further, this terminal device is connected to a transmission control interface Sr4 for data transmission with the center. Transmission control interface LS
I4 is an interface circuit that converts this parallel data into serial data for transmission to the center. These/D-LSI2, transmission control interface L
SI4 is controlled by MPU5. That is, the MPU 5 controls the /D-LSI 2 and the transmission control interface LS 14 in response to polling from the center, and
-Gives a control signal for transmitting input data obtained to L SI2.

However, in such conventional terminal devices, M
Software was required to define the operating procedure of the PU5, and it took a lot of time to develop it. This has caused the manufacturing cost of the terminal device to become high.

Purpose of the Invention The present invention solves these conventional problems, and provides a data processing system that can transmit input data to a center using only a hardware control circuit without using an MPU in a terminal device. The purpose is to provide transmission equipment.

Structure and Effects of the Invention The present invention is a data transmission device for transmitting data between a center and a terminal device, and the terminal device encodes input data obtained from an input device and holds it internally, and also transmits a data holding signal. An interface circuit for outputting, a timing circuit having an operation time longer than IJ1 interval for reading data from the center to the terminal device, an AND circuit for ANDing the output of the timing circuit and the data holding output of the interface circuit, and an AND circuit. The present invention is characterized in that it includes a control circuit that provides a read signal to the interface circuit and sets a timing circuit.

According to the present invention having such characteristics, it becomes possible to transmit the data obtained to the input means to the center based on the timing of polling from the center without using an MPU. Therefore, there is no need to develop software for operating the MPU, and it becomes possible to configure the terminal device economically.

DESCRIPTION OF THE EMBODIMENT FIG. 2 is a circuit diagram showing an embodiment of the data transmission device according to the present invention. In this figure, the same parts as in the conventional example will be explained using the same reference numerals. First, it is assumed that the keyboard 1 is composed of a group of key switches connected in a matrix of maximum 8×8, as in the conventional keyboard. Keyboard 1/
It is driven by the output of a 3-8 decoder 3 that decodes the binary signals of SLO to SL3 of the D-LSI 2 in 8-bit parallel, and provides the input data to the terminal PLO-RL7 of the D-LSI 2. The K/D-LSI 2 converts data obtained from the keyboard 1 into 8-bit parallel data, and includes an 8-byte buffer circuit therein.

Data bus terminal DBO-DB7 of K/D-LSI2,
It is connected to the latch circuit 7 and the K/D-LSI initial setting circuit 8. The launch circuit 7 temporarily holds one byte of output data from the N/D-LSI 2 and transmits the data to the transmission control interface LSI 4. The oscillator 6 provides a clock signal to the /D-LSI 2, the transmission control interface LSI 4, and the counter circuit 9. The counter circuit 9 divides the clock signal to generate signals A and B of the same frequency with different duties. When there is an input from the keyboard 1, a signal indicating data retention is generated from the output terminal INT of the D-LSI2.
The signal held in the D-LSI 2 is read out. In the conventional example, this output was given to the MPU as an interrupt input, but in this embodiment, it is given to the NAND circuit 10. On the other hand, a transmission control interface LS is connected between the center and this terminal device via a receiver/driver circuit 11.
I4 is connected. Transmission control interface LSI4
has input ports P2.0 to P2.7, and when transmitting data from the terminal device to the center, the transmission control interface LSI4 has input ports P2.0 to P2.7.
The 8-bit parallel data obtained is converted into serial data, and the signal is transmitted from the receiver/driver circuit 11 to the center via a line. When a signal is transmitted from the center, the serial data is transmitted to the transmission control interface LSI 4 via the receiver/driver circuit 11 and converted into 8-bit parallel data.

Now, the center normally polls each terminal periodically, for example every 1 ma, but it may be impossible to poll a terminal because other processing takes time. In that case, a signal to that effect is transmitted via the line, and an output is obtained at the BUSY terminal of the transmission control interface LSI4. BUS
The Y output is added to the input of the NAND circuit 10. The NAND circuit 10 is further supplied with the Q output of the flip-flop 13, which generates an AND output which is a condition for reading data from the K/D-LSI 2, and supplies the output to the inverter 14 and the NOR circuit 15. . Inverter 14 provides its inverted output to the D input of flip-flop 12 and NAND circuits 16 and 17. NAND circuit 17 is inverter 14
and the Q output of the flip-flop 12, and the output is given to the monostable multi-bi break 18. Monostable multivibrator 18 Hani/D
- A timing circuit provided as a transmission waiting time timer to match the data read speed of LSI2 and the polling speed from the center, and its operating time is sufficiently longer than the time required to transmit data to the center. It is assumed that the operating time is set to be 3 ms, for example, in this embodiment. The output of the monostable multipipe rake 18 is given to the CLE terminal of the flip-flop 13.

NAND circuit 16, inverter 14 and flip-flop 1
2 and the A output of the counter circuit 9 to give the switch information reading timing to the /D-LSI 2, and the output is output to the /D-LSI 2.
2 lead terminal RD, the T input of the flip-flop 13 and the NAND circuit 19. The NAND circuit 19 performs an AND with the B output of the counter circuit 9 and provides a strobe signal to the latch circuit 7.

Next, the operation of the data transmission device of this embodiment will be explained with reference to waveform diagrams and flowcharts.

First, when the power is turned on, the power supply reset circuit 20 operates in step 21 to reset each part, and the initial setting control circuit 8 sets the /D-LSI 2 to the switch information reading mode. Then, in step 22, an INT signal is awaited from /DLSIZ.

Here, in FIG. 3 (al indicates the A output of the counter circuit 9, when the key on the keyboard 1 is pressed at t1, and then the switch is pressed again, /D-LSI2
Assuming that the first and second data are held in the buffer, the TNT output becomes the "■" level as shown in the figure at time t1.

Here, assuming that the busy signal BUSY is not given from the center, the flip-flop 13 is in the reset state and the Q
Since the output is H'', the AND output of the NAND circuit 10 causes the flip-flop 12 to be output as shown in FIG. 3 (C1).
is given D input.

Therefore, the flip-flop 12 generates a Q output in synchronization with the T input as shown in FIG. 3 fdl. This Q output triggers the monostable multivibrator 18 via the NAND circuit 17 (step 23), and as shown in FIG. The read signal RD is given to the /D-LSI2 by the Q output of the counter circuit 9 in synchronization with the A output of the counter circuit 9, as shown in FIG. The first key input data that is being input is the data bus terminal DB.
It will be read from O to DB7 (step 24
).

During this read period, a strobe signal STB is applied to the launch circuit 7 by logical AND with the B output of the counter circuit 9, as shown in FIG. 3ffl. Therefore, Figure 3 (11
At time t2, the launch circuit 7 is /D as shown in FIG.
-1 and the output signal of Si2 is held (step 25). After that, flip-flop 13 is set,
The Q output is given to the NAND circuit 10 and /D-LS
Reading data from I2 is prohibited. In this case, since the center is not generating a busy signal, polling is performed on this terminal device during the transmission waiting time by the monostable multi-by-break 18, and the data in the launch circuit 7 is transferred to the transmission control interface l, SI4. It will be transmitted to the center via.

Then, in step 26, the time-up of the monostable multi-bi break 18 is awaited, and if the output of the mono-stable multi-bi break 18 is inverted at time t3, the flip-flop 13 is reset as shown in FIG. 3 (hl). When the gate of the NAND circuit 10 is opened, the D input is applied to the flip-flop 12 by the TNT signal of the /D-LSI 2.Therefore, as in the previous case, the flip-flop 12 performs a Then, by the NAND circuit 16 /
A read signal RD is transmitted to the D-LSI2.

Therefore, at time t4, the output signal of /D-LSI2 is launched to the launch circuit 7, and the second data held in the buffer of /D-LSI2 is sent to the center by subsequent polling from the center. do.

As described above, in the present invention, by using a timing circuit, keyboard data is transmitted to the center while keeping timing with the polling speed of the center. If a busy signal is sent from the center here, the K/D
- Data is not read from LSI 2, and data transmission is performed after the busy state is released.

[Brief explanation of the drawing]

FIG. 1 is a circuit diagram showing a terminal device of a conventional data transmission device, FIG. 2 is a block diagram showing a circuit configuration of a terminal device of a data transmission device according to the present invention, and FIG.
FIG. 3 is a waveform diagram showing waveforms at various parts in the figure. FIG. 4 is a flowchart showing the operation. 1---------Keyboard 2--------K/
D-I-S 14--Transmission control interface LSI 7--Launch circuit 9--Counter circuit 10°16, 17. l 9---
-----Nand circuit 12.13---1---Flip-flop 1 B--------- Monostable multi 2 Pipe Lake patent applicant Tateishi Electric Co., Ltd. agent Patent attorney Kanki Okamoto (and 1 other person) ) 3

Claims (1)

[Claims] (1) A data transmission device that transmits data between a center and a terminal device, the terminal device having an interface circuit that encodes input data obtained from the input device and holds it internally, and outputs a data holding signal. a timing circuit having an operation time longer than the data read interval of the center for the terminal device; an AND circuit that performs an AND of the output of the timing circuit and the data holding output of the interface circuit; A data transmission device comprising: a control circuit that provides a read signal to the interface circuit and controls the timing circuit.