JPH0432407B2 - - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION Field of the Invention The present invention relates to a data transmission device that transmits data between a center and a terminal, and more particularly to a data transmission device that transmits data to a center without using an arithmetic processing unit.

Conventional technology and its problems When a terminal has an input device such as a keyboard and input data is sent to the center, the data transmission device also has a processing unit (hereinafter referred to as MPU).
is provided. FIG. 1 shows an example of such a conventional data transmission device. In this figure, a keyboard 1 with a maximum of 8 x 8 key switches connected in a matrix is a keyboard/display interface LSI (hereinafter referred to as K/D・LSI).
)2. Keyboard 1 is K/
It is driven by the output of the 3-8 decoder 3 that decodes the binary signals of the output terminals SL0 to SL3 of the D・LSI2 into 8-bit parallel, and the switch input is given to the data input terminals RL0 to RL7 of the K/D・LSI2. . The K/D LSI 2 converts data input from the keyboard 1 into 8-bit parallel data. Further, a transmission control interface LSI 4 for transmitting data with the center is connected to this data transmission device. The transmission control interface LSI 4 is an interface circuit that converts this parallel data into serial data in order to transmit it to the center. These K/D LSI 2 and transmission control interface LSI 4 are controlled by MPU 5. That is, the MPU 5 controls the K/D LSI 2 and the transmission control interface LSI 4 in response to polling from the center, and provides a control signal for transmitting input data obtained to the K/D LSI 2.

However, such a conventional data transmission device requires software to define the operating procedure of the MPU 5, and it takes a lot of time to develop it. This has led to an increase in the manufacturing cost of the data transmission device.

Purpose of the Invention The present invention solves these conventional problems, and is capable of transmitting input data to a center using only a hardware control circuit without using an MPU as a data transmission device. The purpose is to provide a data transmission device.

Structure and Effects of the Invention The present invention is a data transmission device that transmits data between a center to which a data read signal is transmitted at a predetermined timing, and which encodes input data from an input device and holds it internally. an interface circuit that outputs a data holding signal when the data is held and also outputs held data when a read signal is applied; and a timing circuit that has an operating time longer than the data read interval of the center for the data transmission device an AND circuit that takes an AND of the output of the timing circuit and a data holding signal of the interface circuit; a control circuit that provides a read signal to the interface circuit based on the output of the AND circuit and sets the timing circuit; The apparatus is characterized by comprising a transmission control means for latching the signal read from the interface circuit and transmitting data based on the data read signal from the center.

According to the present invention having such characteristics, when data is obtained from the input device, the data transmission device encodes the data using the interface circuit and holds it internally, indicating that the data is held. Outputs the data holding signal to the AND circuit.
The AND circuit performs an AND of this output and the output of the timing circuit, and a read signal is given from the control circuit to the interface circuit based on this AND signal. In this way, data can be read from the interface circuit. If a data read signal is transmitted from the center, data is read out during this time. Since the operating time of the timing circuit is set to be longer than the data read signal periodically obtained from the center, data can be read and transmitted to the center within the operating time. Therefore, there is no need to develop software for operating the MRU, and it becomes possible to configure the data transmission device economically.

DESCRIPTION OF EMBODIMENTS FIG. 2 is a circuit diagram showing an embodiment of a data transmission device according to the present invention. In this figure, the same parts as in the conventional example will be explained using the same reference numerals. First, it is assumed that the keyboard 1 is composed of a group of keyswitches connected in a matrix of maximum 8.times.8, as in the conventional keyboard. Keyboard 1 is K/D・LSI2
It is driven by the output of the 3-8 decoder 3 which decodes the binary signals of SL0 to SL3 in 8-bit parallel, and the input data is applied to the input terminals RL0 to RL7 of the K/D LSI 2. The K/D LSI 2 converts data obtained from the keyboard 1 into 8-bit parallel data, and includes an 8-byte buffer circuit therein. K/
Data bus terminals DB0 to DB7 of the D.LSI 2 are connected to a latch circuit 7 and a K/D.LSI initial setting circuit 8. The latch circuit 7 temporarily holds one byte of output data from the K/D LSI 2, and transfers the data to the transmission control interface LSI.
Tell 4. The oscillator 6 converts the clock signal into K/D.
It is applied to the LSI 2, the transmission control interface LSI 4, and the counter circuit 9. The counter circuit 9 divides the frequency of the clock signal to generate signals A and B of the same frequency with different duties. When an input is received from the keyboard 1, a signal indicating data retention is generated from the output terminal INT of the K/D LSI 2, and reading of the signal held in the K/D LSI 2 is requested. In the conventional example, this output was given to the MPU as an interrupt input, but in this embodiment, it is given to the NAND circuit 10. On the other hand, this data transmission device is provided with a receiver driver circuit on a line connected to the center, and a transmission control interface LSI 4 is connected to this. The transmission control interface LSI 4 has input ports P2.0 to P2.7, and when transmitting data from the data transmission device to the center, the transmission control interface LSI 4 has input ports P2.0 to P2.7. The obtained 8-bit parallel data is converted into serial data, and the signal is transmitted from the receiver/driver circuit 11 to the center via a line. When a signal is transmitted from the center, the serial data is transmitted to the transmission control interface LSI 4 via the receiver/driver circuit 11 and converted into 8-bit parallel data.

Now, the center normally polls each terminal periodically, for example every 1 ms, but it may not be possible to poll a terminal because other processing takes time. In that case, a signal to that effect is transmitted via the line, and an output is obtained at the terminal of the transmission control interface LSI 4. The output is applied to the input of a NAND circuit 10. The NAND circuit 10 is further supplied with the output of a flip-flop 13, which generates an AND output which is a condition for reading data from the K/D LSI 2, and supplies the output to an inverter 14 and a NOR circuit 15. The inverter 14 transfers its inverted output to the D of the flip-flop 12.
It is applied to the input and NAND circuits 16 and 17. The NAND circuit 17 performs an AND operation between the output of the inverter 14 and the Q output of the flip-flop 12.
The output is given to a monostable multivibrator 18. Monostable multivibrator 18 is K/D・
A timing circuit provided as a transmission waiting time timer to match the data read speed of LSI 2 and the polling speed from the center,
The operating time is set to be sufficiently longer than the time required to transmit data to the center, for example, 3 ms in this embodiment. The output of monostable multivibrator 18 is applied to the terminal of flip-flop 13.
The NAND circuit 16 calculates the AND of the inverter 14, the E output of the flip-flop 12, and the output of the counter circuit 9 to give the K/D LSI 2 the timing for reading switch information, and outputs the output to the K/D LSI 2. It is applied to the lead terminal of LSI 2, the T input of flip-flop 13, and NAND circuit 19. The NAND circuit 19 performs an AND with the B output of the counter circuit 9 and provides a strobe signal to the latch circuit 7.

Next, the operation of the data transmission device of this embodiment will be explained with reference to waveform diagrams and flowcharts.
First, when the power is turned on, the power reset circuit 20 operates in step 21 to reset each part.
The initial setting control circuit 8 sets the K/D LSI 2 to switch information reading mode. Then, in step 22, an INT signal is awaited from the K/D LSI 2. Here, FIG. 3a shows A of the counter circuit 9.
The key on keyboard 1 is pressed at the current time t1, and then the switch is pressed again, and the first and second keys are input to the buffer of K/D LSI 2.
Assuming that the data of is retained, at time t1
The INT output becomes "H" level as shown.
Assuming that no busy signal is given from the center, the flip-flop 13 is in the reset state and the output is "H", so the AND output of the NAND circuit 10 causes the flip-flop 12 to be turned on as shown in FIG. 3c. D input is given.
Therefore, flip-flop 12 produces a Q output in synchronization with the T input as shown in FIG. 3d. This Q output triggers the monostable multivibrator 18 via the NAND circuit 17 (step 23).
As shown in Figure 3g, the transmission waiting time T, here
Continues operation for 3ms. Also flip-flop 12
A read signal is given to the K/D LSI 2 in synchronization with the output of the counter circuit 9 as shown in FIG. 3e by the Q output of the counter circuit 9. Then K/D・
The first key input data held in the internal buffer of LSI2 is transferred to its data bus terminals DB0 to DB.
7 (step 24).
During this read period, a strobe signal is applied to the latch circuit 7 by ANDing it with the B output of the counter circuit 9, as shown in FIG. 3f. Therefore, as shown in FIG. 3i, the latch circuit 7 holds the output signal of the K/D LSI 2 at time t2 (step 25). After that, flip-flop 13 is set and its output is NAND circuit 1.
When set to 0, reading data from the K/D LSI 2 is prohibited. In this case, since the center is not generating a busy signal, the data transmission device is polled during the transmission waiting time by the monostable multivibrator 18, and the latch circuit 7
The data will be transmitted to the center via the transmission control interface LSI 4.

Then, in step 26, the time-up of the monostable multivibrator 18 is awaited, and if the output of the monostable multivibrator 18 is inverted at time t3, the flip-flop 13
is reset as shown in FIG. 3h. Therefore, the gate of NAND circuit 10 opens and K/D LSI 2
A D input is given to the flip-flop 12 by the INT signal of the flip-flop 12. Therefore, as in the case described above, the flip-flop 12 is set in synchronization with the A output of the counter circuit 9, and then a read signal is transmitted from the NAND circuit 16 to the K/D LSI 2.
Therefore, at time t4, the output signal of the K/D LSI 2 is latched in the latch circuit 7, and the second data held in the buffer of the K/D LSI 2 is sent to the center by subsequent polling from the center. .

As described above, in the present invention, by using a timing circuit, keyboard data is transmitted to the center while keeping the timing with the polling speed of the center. If a busy signal is sent from the center here, no data is read from the K/D LSI 2, and data transmission is performed after the busy state is released.

[Brief explanation of drawings]

Figure 1 is a circuit diagram showing a conventional data transmission device.
FIG. 2 is a block diagram showing the circuit configuration of a data transmission device according to the present invention, and FIGS. 3 a to 3 are waveform diagrams showing waveforms at various parts in FIG. 2. FIG. 4 is a flowchart showing the operation. 1... Keyboard, 2... K/D LSI, 4... Transmission control interface LSI, 7... Latch circuit,
9... Counter circuit, 10, 16, 17, 19... NAND circuit, 12, 13... Flip-flop, 18
…monostable multivibrator.

Claims (1)

[Scope of Claims] 1. A data transmission device that transmits data between a center and a center to which a data read signal is transmitted at a predetermined timing, which encodes input data from an input device and holds it internally, and stores the data internally. an interface circuit that outputs a data holding signal when data is held and also outputs held data when a read signal is applied; a timing circuit that has an operating time that is longer than the data read interval of the center for the data transmission device; an AND circuit that takes an AND of the output of the timing circuit and a data holding signal of the interface circuit; and a AND circuit that provides a read signal to the interface circuit based on the output of the AND circuit and sets the timing circuit. A data transmission device comprising: a control circuit for holding a signal read from the interface circuit, and transmission control means for transmitting data based on a data read signal from the center.