JPS5911532U - frequency conversion circuit - Google Patents
frequency conversion circuitInfo
- Publication number
- JPS5911532U JPS5911532U JP10784582U JP10784582U JPS5911532U JP S5911532 U JPS5911532 U JP S5911532U JP 10784582 U JP10784582 U JP 10784582U JP 10784582 U JP10784582 U JP 10784582U JP S5911532 U JPS5911532 U JP S5911532U
- Authority
- JP
- Japan
- Prior art keywords
- predetermined level
- detection
- frequency conversion
- pulse signal
- conversion circuit
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Granted
Links
Landscapes
- Analogue/Digital Conversion (AREA)
Abstract
(57)【要約】本公報は電子出願前の出願データであるた
め要約のデータは記録されません。(57) [Summary] This bulletin contains application data before electronic filing, so abstract data is not recorded.
Description
・ 第１図はこの考案の一実施例を示す周波数変換回
路の接続図、第２図は第１図に示す実施例回路の動作を
説明すやための信号波形図である。
１・２：入力端子、３：増幅器（積分用）、４・５：比
較器、６：ワンショットマルチ回路、７：スイッチング
トランジスタ、８：増幅器（コントロール用）、ＶＳ：
設定電源、９・１０：出力端子。- Fig. 1 is a connection diagram of a frequency conversion circuit showing an embodiment of this invention, and Fig. 2 is a signal waveform diagram for explaining the operation of the embodiment circuit shown in Fig. 1. 1/2: Input terminal, 3: Amplifier (for integration), 4/5: Comparator, 6: One-shot multi-circuit, 7: Switching transistor, 8: Amplifier (for control), VS:
Setting power supply, 9/10: Output terminal.
Claims (1)
正極性出力電圧が第１の所定レベルに達したことを検出
する第１検出回路と、前記積分回路の負極性出力電圧が
第２の所定レベルに達したことを検出する第２検出回路
と、これら検出回路による第１所定レベルの検出もしく
は第２の所定レベル検出でオンするスイッチング手段′
と、この 。 スイッチング手段がオンすると前記積分回路の出力電圧
を前記第１所定レベルと第２所定レベル間に存する第３
の所定レベルにコントロールする手段と、前記第１所定
レベルもしくは第２の所定レベルの検出に同期してパル
ス信号を発生する手段とを備え、前記積分回路が前記ス
イッチング手段のオフ・オフの繰り返しで前記第３所定
レベルから第１所定レベルまでの、または前記第３所定
レベルから第２所定レベルまでの積分動作を繰り返すこ
とにより、前記パルス信号発生手段は入力電圧に応じた
周波数のパルス信号を出力することを特徴とする周波数
変換回路。[Claims for Utility Model Registration] An integrating circuit that receives and integrates an input voltage, a first detection circuit that detects that the positive output voltage of this integrating circuit has reached a first predetermined level, and a second detection circuit that detects that the negative output voltage has reached a second predetermined level, and a switching means that is turned on when the first predetermined level is detected by these detection circuits or the second predetermined level is detected by these detection circuits.
And this. When the switching means is turned on, the output voltage of the integrating circuit is changed to a third level between the first predetermined level and the second predetermined level.
and means for generating a pulse signal in synchronization with detection of the first predetermined level or the second predetermined level; By repeating the integration operation from the third predetermined level to the first predetermined level or from the third predetermined level to the second predetermined level, the pulse signal generating means outputs a pulse signal with a frequency corresponding to the input voltage. A frequency conversion circuit characterized by:
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP10784582U JPS5911532U (en) | 1982-07-15 | 1982-07-15 | frequency conversion circuit |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP10784582U JPS5911532U (en) | 1982-07-15 | 1982-07-15 | frequency conversion circuit |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| JPS5911532U true JPS5911532U (en) | 1984-01-24 |
| JPH0218601Y2 JPH0218601Y2 (en) | 1990-05-24 |
Family
ID=30251836
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP10784582U Granted JPS5911532U (en) | 1982-07-15 | 1982-07-15 | frequency conversion circuit |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPS5911532U (en) |
-
1982
- 1982-07-15 JP JP10784582U patent/JPS5911532U/en active Granted
Also Published As
| Publication number | Publication date |
|---|---|
| JPH0218601Y2 (en) | 1990-05-24 |
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