JPS59116876A - Control system for execution of signal processor instruction in multiprocessor system - Google Patents

Abstract

PURPOSE:To perform secure control over competition in the execution of signal processor instructions and to improve the processing efficiency of a system by providing a signal processor instruction control bit in the control register of every system. CONSTITUTION:Control bits 2 and 5 in control registers 1 and 4 represents a signal processor instruction control bit SIGP BUSY. When the high priority computer of a system 0 sends an instruction SIGP to the low priority computer of a system 1, its microprogram mu1 is started. When the computer of the system 1 sends the instruction SIGP to the computer of the system 0, the bit SIGP BUSY of the high priority computer of the other system is checked firstly. When the bit is off, it is judged that there is no competition, and the instruction SIGP of its system is presumed as effective and executed. Thus, the control bit is provided in the control register of each system to perform the secure control over competition, improving the processing efficiency of the system.

Description

Detailed Description of the Invention [Technical Field of the Invention] The present invention relates to the transmission of signal processor instructions (5ils) between microprogram computers of a multiprocessor system.
The present invention relates to an execution control method for an rLal processor instruction (herein abbreviated as a 5IGP instruction), and particularly to a priority control method when a 5IGP instruction conflicts between both microprogram computers.

[Technology background]

Generally, in a multiprocessor system, the 5IGP command is provided as a communication function between computers to mutually start, stop, and otherwise control the other computer.
The osIGP command includes the address of the other computer and control details, and is used as an effective means for quickly and smoothly cooperating between computers.

By the way, 2 cars total 3! In a multiprocessor system consisting of # machines, when each computer simultaneously attempts to execute 5 IGP instructions to the other computer, a so-called conflict situation occurs. For this reason, a method is used in which high and low priorities are assigned to each computer in advance, and the execution order is controlled according to the priorities. However, the process of checking whether the 5IGP command has been issued in the 9 partner machines, and the process of setting the own computer to the 5IGP command issuing state after confirming the non-conflict state, both take a non-negligible amount of time. Therefore, for example, when a high-priority computer attempts to execute a 5IGP instruction after checking that there is no contention, at that point a low-priority computer has already executed the 5IGP instruction.
In some cases, the P command is being executed, which causes problems in that reliable control is not possible and wasteful control occurs.

[Object and structure of the invention]

The purpose of the present invention is to enable two microprogram computers to
An object of the present invention is to provide a control method that enables reliable priority control even at the timing position in the execution of a 5IGP instruction.

The present invention has a configuration for this purpose, in which, in a multiprocessor system consisting of two microprogram computers that have high and low priorities for the execution of the signal processor instruction 5IGP, some microprograms of the computer in its own system can only be written, while others can write. Signal processor instruction control pit 5IGP BU that can only be read depending on the microprogram of the system computer
SYe is provided in the control register of each system, and when exchanging the signal processor instruction 5IGP' between both systems, the high priority system uses its own control pin 1-8IGPBUS.
After a predetermined time after setting Y to ON, turn SIGPBUSY (control pin of other system) SIGP I (read USY, and if it is ON, control pin of own system) to O.
Reset to F F, and control bit 5IGI of other system
)B [5IG above only when JSY is OFF”
P instruction is executed, and on the other hand, in the low priority system, the control bit (SIGP BUSY) of the other system is read, and if it is OF' F, the control bit 5IG of the own system is read.
It is characterized by microprogram control so that the above-mentioned 5 IGP instructions are executed only when PHUSY is set to ON and the control pin (SIGP BUSY) of the other system is ON.

[Practice of the inventionff! l) The present invention will be explained below based on examples.

FIG. 1 is a block diagram of an embodiment of the present invention. In the same figure,
The circuit on the left is a 0# series microprogram computer, and the circuit on the right is a 1# series microprogram 1-t.
x machine is shown. In addition, μoit “0” series microprograms, μmtri “1” series microprograms,
SvP is a service processor, 1 is a 10" system control register, and 4 is a "1" system control register. Control bits 2 and 5 in control registers 1 and 4 are 5IGP.
BUSY bit, 3.6 represents the CPU BUSY bit. In addition, 7 and 8 are their own microprograms /'[5IGP BUSY from l+μm
The bit write signal lines 9.10 and 11.10 are microprograms of other systems, respectively. 5IGP BUS from μ0
Y bit read signal line, 11.12 is the CPU BUSY bit write signal line from the service processor SvP, 13.111 is the CPU BUS from the own microprogram /'0 + /j1 and SvP, respectively.
It represents the Y-bit read signal line.

5IGP BUSY bit 2.5 is used as a core means to prevent conflicts between two computers when 5IGP instructions are issued to each other, and CPU BUSY bit 3.6 is , two computers issue 5IGP instructions to SVP, and 5VI
) is used as a means to prevent conflicts when requesting control of the other party's computer. ○ Figure 2 (a), (b) U, 5IGP HUSY
C is a flow diagram of a "0" series and "1" series microprogram/'On/'i for controlling the priority of 5IGP instruction history rows using bits. Note that in this embodiment, the "0" series as a high priority and “1”
The system is assigned to low priority.

The operation of the embodiment will be described below with reference to the flow shown in FIG.

In FIG. 2(α), when a 1-priority computer in the “0” system issues a 5IGP instruction to a low-priority computer in the “1” system, its microprogram/l port is activated. First, in order to exercise the high priority of own system, 5IGP B' [JSY bit 2
is set to "ON" unconditionally, and then for a predetermined period of time (n
+2n') Waits for a time of τ.

.tau. is the clock period, rLf'i is the execution time in .mu.m, discussed below, and .tau. is the time required to transmit the 5 IGP BUSY bit read signal between systems. This time wait is for waiting for the value of the 5IGP BUSY bit 5 of the other system to be determined. Here, 5 of other systems
Read the IGP BUSY bit and it is “ON”
, the other system with low priority is 5IGP
Determines that the instruction is being executed, exercises high priority right 1, and invalidates the 5 IGP instruction of the own system. On the other hand, if the other system's 5IGP BUSY bit is "OFF", the own system's 5IGP instruction is executed as is, valid.

In Figure 2 (h), the low priority computer of the “1#” system is 5I against the high priority computer of the “0” system.
When a GP command is issued, the 5IGP of the own system is unconditionally issued, as in the case of the 0# system ^priority calculator mentioned above.
Do not set the BUSY bit to @ON#,
First, 5IGP BU of another high priority computer
Check the SY bit and if it is “ON”,
Recognizes the high priority of other systems and invalidates the 5IGP command of the own system. However, if the 5IGp BUSY bit of the other system is "OFF", it is determined that there is no conflict, and the 5IGP instruction of the own system is validated and executed.

Figures 3 to 6 are timing diagrams showing operation examples of the various parts of the above-mentioned flow.
By setting the waiting time of tL+2tL')τ, "(1
7Io in the ``1'' series indicates that the determined value of the 5IGPBUSY bit in the "1" series can always be read.

In Figure 3, 70 of the @0# system is the 5IGP BU of the department.
When the SY bit is set to “ON”, almost simultaneously “
1# series (DIJ1ka"Q" series (7,) SIGP
Indicates that the BUSY bit "01?F" signal is received.

“1# system 111 is KSIGP BUS after ryr time.
Since the Y bit is set to “ON”, μ0 of the 'o' system
reads the "1" series 5IGP BUSY bit (FL+2 rL') one hour later, the "1" series 5IGP BUSY bit has been determined.

Figure 4 shows that the μm of the “1#” system is 5IGPBU of the “0” system.
The SY bit "OFF" signal is turned "ON" by the 7 no 0 after the case in Figure 3, which turns the 5IGP BUSY bit of the own system "ON".
This indicates that the Uke is taken just before being set. In this case, the waiting time (W+2n')τ is close to the allowable limit, and! 1t) n, 1” series 5IGP BLI
The data will be read immediately after the SY bit is determined to be “ON”.

Figure 5 shows that the 5IGP BUSY bit of the “0” thread is “
μm receives the signal immediately after it turns on, and sends it to its own system (7
) SIGP BUSY bit '@OFF' (DII
This shows the case where K is confirmed.

Figure 6 shows that the 5IGP BUSY bit of @0”
Long before it is set to ON'', 〃1 is set to
The CPU in Figure 1 at 0th order shows the case where the F” value is received.
The functions of BIJSY bits 3 and 6 will be explained.

When a process is requested to SvP using a standalone computer or a 5IGP command, SvP sets the CPU BUSY bit of the system opposite to the system on which the process is executed. When requesting processing to SvP with an S I GP command for another system, first, use a method similar to the flow shown in Figure 3 to request processing from the CPU BIJ of the own system using a microprogram.
SY pin) k is read, and if it is "ON", the 5IGP command is invalidated as BTJ SY, and processing is not requested to SVP.

〔Effect of the invention〕

As described above, according to the present invention, contention during execution of signal processor instructions in a multiprocessor system can be reliably controlled, and the processing efficiency of the system can be improved.

[Brief explanation of the drawing]

Figure 1 is a configuration diagram of an embodiment of the present invention, Figure 2 (α), (h)
is a control flow diagram thereof, and FIGS. 3 to 6 are timing diagrams of examples of its operation. In the figure, 1 and 4 are control registers, 2 and 5 are 5IGPBUS
Y bit, 3,6 UCPU BUSY bits, μ0 represents a ``θ'' system microprogram, μm represents a ``1#'' system microprogram, and SvP represents a service processor. 11-

Claims (1)

[Claims] In a multiprocessor system consisting of two microprogram computers with high and low priorities for the execution of the signal processor instruction 5IGP, depending on the microprogram of the computer in its own system, it is possible to only glance at it, and by the microprogram in the computer in another system. The signal processor command control bit S GPBUSY, which can only be read, is provided in the control register of the system system, and the signal processor command 5IGP is exchanged between both systems.
After a predetermined time after setting GP BUSY to 0NlC, read the control bit (SIGP BUSY) of the other system, and if it is ON, set the control bit 5IG of the own system.
P BUSY is reset to OFF', and the above 5 IGP instruction is executed only when the control bit 5 IGP BUSY of the other system is OFF. On the other hand, in the low priority system, the control bit 5 IGP BUSY of the other system is reset. If it is OFF, set the control pin of the own system) SIGP BUSY to ON, and set the control pin of the other system). A signal processor instruction execution control method characterized by program control.