JPS59119863A - Semiconductor device - Google Patents

Abstract

(57) [Abstract] This bulletin contains application data before electronic filing, so abstract data is not recorded.

Description

[Detailed description of the invention] The present invention relates to internal wiring of a semiconductor device.

In conventional silicon gate (CMO8) semiconductors, when polysilicon is used as wiring, impurity diffusion of the polysilicon wiring is performed at the same time as the impurity diffusion process when forming the source and drain of the transistor, so P channel regions are exposed to P such as boron. A P-type polysilicon wiring containing type impurities is formed in the N channel region, and an N-type polysilicon wiring containing N-type impurities such as phosphorus is formed in the N channel region. When P-type polysilicon and N-type polysilicon come into contact, a PN junction is formed at the junction, which results in rectification and cannot be used as wiring. For this reason, conventionally, in the post-process, as shown in Figure 6, a hole is made by etching in the interlayer insulating film (usually 51O2) at the polysilicon bonding area, and aluminum, which is used as the second layer wiring, is vapor-deposited on the bonding area. This shorts the PN junction and eliminates the effect of the barrier.
It was -7. This conventional method requires a place to short-circuit the joint, and because a second layer of aluminum wiring cannot be placed above the joint, it is not possible to set strict design rules when designing circuit patterns. However, there was a serious drawback in that the wiring method was restricted.

In order to eliminate such drawbacks, the present invention has devised the structure and formation method of polysilicon wiring, and will be described in detail below.

In the manufacturing process of a semiconductor integrated circuit, the process up to the deposition of polysilicon is completely the same as the conventional process. In the present invention, next, about 100X of high melting point metal 2 such as molybdenum is deposited on polysilicon 1 and patterned. If it is desired to ignore variations in the threshold voltage in this step, it is also possible to add a step in which the refractory metal is not deposited only on the gate portion of the transistor.

Next, as shown in Fig. 1, a P-type impurity 3 containing boron% is added to the P-channel region, and an N-type impurity 4 such as phosphorus is added to the N-channel region.
is introduced through the high melting point metal by ion implantation.

Thereafter, the process is carried out in exactly the same manner as in the conventional method, including a heat treatment step for activating the implanted ions.

Through the above steps, the polysilicon wiring has a structure in which the junction of the P-type polysilicon 5 and the N-type polysilicon is short-circuited by the silicide 7 of a high-melting point metal, as shown in FIG. As a result, as shown in FIG. This greatly contributes to increased integration and ease of design. Furthermore, since polysilicon contains silicides of high-melting point metals, it is possible to form interconnects with lower resistance than the basic P-type and N-type polysilicon interconnects, making it possible to create high-speed integrated circuits.

As described above, according to the present invention, it is possible to create a silicon gate CMO3 integrated circuit with significantly higher integration and higher speed than in the past.

[Brief explanation of the drawing]

FIG. 1 shows the process of forming polysilicon wiring according to the present invention. FIG. 2 is a final cross-sectional view of the polysilicon wiring. FIG. 6 is a conventional polysilicon wiring diagram.

Claims (1)

[Claims] In the manufacturing process of semiconductor integrated circuits, after forming a polysilicon wiring pattern, a high melting point metal is thinly deposited on the polysilicon, and then P-type and N-type metals are deposited on the polysilicon through the high melting point metal. P-type by introducing impurities by ion implantation. A semiconductor device characterized by forming a low-resistance polysilicon wiring having no rectifying property despite the presence of N-type impurities.