JPS59129986A - Memory circuit - Google Patents

Abstract

PURPOSE:To attain automatic data retention by connecting transistors (TRs) for chip selection and an electric power supply voltage detection or the like in series so as to reduce the power consumption in the stand-by and the data retention state. CONSTITUTION:P type TRs Q311-Q31n for potential drop, a P type TRQ33, a high resistance N type TRQ34 turned on by a power supply voltage in series connection and a P type TRQ32 operated in response to a chip selecting signal are connected in series between the TRs Q31n and Q33 in a power supply voltage detecting circuit B31. The TRQ32 is turned off at non-selection and the TRQ33 is turned off at power supply voltage drop, the node N31 goes to a low level, and an internal chip selecting output from an inverter A31 goes to a high level corresponding to the stand-by state. No current flows from the power supply voltage VCC to ground at the same time in this case and the power consumption in the stand-by data retention is reduced. Further, when the power voltage is lowered, the automatic data retention is attained.

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a memory circuit having a chip selection signal and a low voltage data retention function.

Generally, in a static type memory circuit, the memory circuit is in a non-selected state (hereinafter referred to as a standby state) vc
In order to achieve low power consumption, it is preferable to have a function of completely lowering the power supply voltage to enter a low voltage data retention state (hereinafter referred to as data retention state).

However, these days, even when a chip selection signal is input to a memory circuit, simply lowering the power supply voltage completely can
There is a desire for a function (hereinafter referred to as the auto data 977737 function) that automatically enters a data retention state when the voltage is below a predetermined voltage, and various proposals have been made.

Hajirai example (1) First, conventional theory F! A’t.

FIG. 1 is a partial circuit diagram of a first conventional memory circuit.
The internal chip selection signal generation circuit is shown.

In Figure 1, Qll is a P-channel MO8) transistor, R11, R12, and Rta are resistors, A11 is an inverter circuit, A12 is a NOR circuit, B11 is a power supply voltage detection circuit, C81 is a chip selection signal, and C81' is a chip Internal circuit signal of selection signal C81, Nil and N12 are nodes, Vc
cFi power supply voltage.Next, the automatic data retention function in this circuit VC will be explained with full reference to FIG.

First, the resistor R11 and the resistor R12 are connected in series and have a power supply voltage V. 0 voltage divider circuit is constructed.

Here, the ratio between the resistor R11 and the resistor R12 is set as follows. That is, the power supply voltage V. 0 is the normal operating voltage of the memory circuit, the power supply voltage ■. The potential difference between C and the potential of node N11 is greater than the absolute value of the threshold voltage (hereinafter referred to as vTP) of the P-channel MOS transistor, and the ON resistance value of P-channel transistor Q11 is sufficiently smaller than the resistance of resistor R13. , Therefore, the ratio is set such that the potential of the node N12 is at the n l I+ level.

In this way, the power supply voltage ■. When 0 is the normal operating voltage, one input of the NOR circuit A12 connected to the output of the inverter A11 is '0', and C8I' is determined only by the chip selection signal C81.

On the other hand, the power supply voltage V. 0 decreases from the normal operating voltage of the memory circuit and the potential of Vll becomes a value of 1■TP1 or less, the P-channel MOS transistor Q11 becomes OF'.
F' to do. At this time, the power supply voltage Vcc is expressed by the following equation.

P-channel MO8) Since transistor Q11 turns off, the potential at node N12 changes from the ``1'' level to ``0''.
When the level becomes low, it is detected that the power supply voltage VCC is below a predetermined voltage. The node N12o potential "o" level, via the inverter circuit AiH-, the NOR circuit A1
It is transmitted to the input terminal of No. 2 as a "1" level. That is,
Even if the potential of the chip selection signal C81 is in the selected state "'0" level, the potential of C8I' is in the non-selected state "1".
“It’s going to be on the level.

Therefore, in the first conventional example, even if the chip selection signal C81 is at the 'O' level, the power supply voltage V.

By completely lowering the voltage to below a predetermined voltage VC″f′, it is possible to automatically set it to a non-selected state, and it has an automatic data retention function.

The first conventional example has been described above.

Conventional Example (2) FIG. 2 is a partial circuit diagram of a memory circuit of a second conventional example.
Similar to FIG. 1, an internal chip selection signal generation circuit is shown.

In the vJ2 diagram, C211-C21n, C22 are P
Channel MO8) transistor, R21 is a resistor, A21 is an inverter circuit, 822 is a NOR circuit, B21 is a power supply voltage detection circuit, C82 is a chip selection signal, C82' is an internal circuit signal of the chip selection signal C82, N21 is a node .

Next, the automatic data retention function in this circuit VC will be explained with full reference to FIG. 2.

First, when the power supply voltage cc is a normal operating voltage of (n+1)l TP1 or more, the P channel MOS transistors Q211 to Q2 tn and C22 are all turned on.

At this time, if the resistance value of the resistor R21 is set so that the potential of the node N21 is at the 1'' level, the logic level of C82' is determined only by the chip selection signal C82.

However, the power supply voltage ■. 0 decreases from the normal operating voltage of the memory circuit and becomes less than (n+1) IVTpl, P
Channel MOS transistor Q22 is turned OFF'. Therefore, the potential of node N21 changes from the '1' level to '0'.
level, and it is detected that the power supply voltage V0° is below a predetermined voltage.

The potential "0" level of the node N21 is applied to the input terminal of the NOR circuit A22 via the inverter circuit A21.
It is transmitted as 1 lebel. That is, the potential of C82' is
Even if the potential of the chip selection signal C82 is at the "0" level in the selected state, it becomes the +1" level in the non-selected state.

Therefore, it is clear that the second conventional example also has an automatic data retention function like the first conventional example.

The above is a detailed description of the second conventional example.

Disadvantages of conventional example Next, the drawbacks of the memory circuit shown in the conventional example will be described.

That is, in the first conventional example shown in FIG. 1, whether the memory circuit is in the selected state or in the non-selected state, the resistor 11. Ground VC via R1,2'i
DC current flows into it.

Also, in the second conventional example shown in FIG. 2, the power supply voltage is the normal operating voltage (in the state of 1, normally from the VC1 power supply to the P channel MO8) transistor Q21°Q22.
Q23. Q24, fully connect resistor R2 to ground D
C current flows into it.

Generally, standby state or data retention state O
This function is to reduce power consumption, and in particular, in a battery backup system, low power consumption is an essential condition in such a state.

However, as mentioned above, in conventional memory circuits with automatic data retention function,
The drawback was that the originally required low power consumption could not be achieved.

OBJECTS OF THE INVENTION An object of the present invention is to provide an entire memory circuit that has an automatic data retention function and consumes low power in both standby and data retention states.

Structure The memory circuit according to the present invention has a chip selection signal, a low voltage data retention function, and a power supply voltage detection circuit for detecting that the power supply voltage is below a predetermined voltage. In the memory circuit, the power supply voltage detection circuit includes n unidirectional elements having a potential drop, a MOS) transistor whose gate input signal is used as a chip selection signal, a MOS) transistor whose gates are all connected to the second power supply, as well as,
It is characterized in that it is configured by connecting resistive elements in series, and has a function of inhibiting a chip selection signal when the first power supply voltage is below a predetermined voltage.

In the memory circuit, the power supply voltage detection circuit includes first to nth MOS transistors whose gates and drains are all connected, an (n+1)th MOS transistor whose chip selection signal is an input signal to all gates, and In the n+2 MOS transistor whose gates are all connected to the second power supply, by connecting all the drains and sources, the n+2 MOS transistors are all connected in series, and the first MOS transistor
In addition to connecting all the sources of the S transistors to the first power supply,
the first to r++-th gates, the first power source being connected to the gate;
2 MO8I - transistors and different nth conduction channels
In the case of +3 MOS transistor, all the sources are the second
connected to the power supply, and the drain of the n+2 MO
S) It is characterized in that it is connected to the drain of a transistor, and the connection point is configured as an output terminal.

Embodiment (1) Next, a first embodiment of the present invention will be explained in detail with reference to all the drawings.

FIG. 3 is a partial circuit diagram of the memory circuit of the first embodiment, showing an internal chip selection signal generation circuit.

In FIG. 3, C311-Q31 n, Q32.
Q3 a is P channel MO8) transistor, C34 is N
Channel MO8) transistor, A31 is an inverter circuit, B31 is a power supply voltage detection circuit, C83 is a chip selection signal, C83' internal circuit signal, and N31 is a node.

The automatic data retention function of the first embodiment of the present invention will be explained with full reference to FIG.

Here, the N-channel MO8) transistor Q34 has a gate power supply voltage V. By applying 0, it is always in the ON state and operates as a high resistance element.

First, the circuit operation when the power supply voltage cc is the normal operating voltage of the memory circuit will be described by dividing the memory circuit into a non-selected state and a selected state.

First, to make the memory circuit non-selected, the potential of the chip selection signal C83 is set to the 1" level. Then, the P-channel MO8) transistor Q32 is turned off. That is, the potential of the node N31 is set to the 0" level. Yes, the potential of C83' is set to the non-selected state via the inverter circuit A31.
Becomes 1″ level.

Note that the high-level input voltage (hereinafter referred to as vIHO8) of the chip selection signal C83 can be expressed by the following equation.

VxHcs=Voo-(n+'1)IVTPl Therefore,
VIHO8 is the number n of P-channel MO8) transistors.
According to Vc, it is possible to set it arbitrarily.

When the second VC, the memory circuit, is to be in the selected state VC, the potential of the chip selection signal C83 is set to the '0' level. Then, the P-channel MO8) transistor Q32 is turned on.

That is, the potential at the node N31 is active at the 1" level, and the potential at the node C83' becomes the selected state "0" level via the inverter circuit A31i.

Next, a case will be described in which when the potential of the chip selection signal C8a is 0'' and the chip is in the selected state, the power supply voltage V.0 drops from the normal operating voltage.

Power supply voltage V. 0 decreases to below (n+2)lVTPl, P-channel MO8) transistor Q33 turns OFF.
do. Therefore, the potential at the node N31, which was at the '1' level, drops to the '0' level, and it is detected that the power supply voltage VCC is below the predetermined voltage. The potential "o" level of the node N31 is transmitted to C83' through the entire inverter circuit A31, and the potential of C83' changes from the selected state "0" level to the non-selected state "1" level.

Therefore, in the first embodiment of the present invention, the power supply voltage V is maintained even when the memory circuit is in the selected state. . By completely lowering the voltage to a predetermined voltage or less, it is possible to automatically set it to a non-selected state, and it has an automatic data retention function.

The automatic data retention function of the first embodiment of the present invention has been described above.

In the first embodiment of the present invention, in the standby state, the P-channel MO8) transistor Q32 is in the OFF state. Also, in the data retention state, the P channel MO8) transistor Q33 is in the OFF' state. Therefore, the first embodiment of the invention provides that under standby and data retention conditions, U, the DC flowing from the power supply to ground.
There is no current.

That is, the first embodiment of the present invention consumes low power in the standby state and data retention state, and
It has an automatic data retention function.

Example (2) Next, a second embodiment of the invention will be described.

FIG. 4 shows a partial circuit A of the memory circuit of the second embodiment.
The internal chip selection signal generation circuit is shown.

In FIG. 4, C41 is a P-channel MO8) transistor, Q, i2. C4a, C441 to Q44n are N-channel MO8) transistors, N41 is an inverter circuit, B41 is an electric voltage detection circuit, C34Fi chip selection signal, C84' is an internal circuit signal of chip selection signal C84, and N41 is a node.

The memory circuit of the second embodiment includes a power supply voltage detection circuit 841
is M constituting the power supply voltage detection circuit B31 in FIG.
OS) The entire feature is that the polarity of the transistor is reversed.

Therefore, the memory circuit of the second embodiment also has the VC1 auto data retention function like the memory circuit of the first embodiment, and has low portable power consumption in the standby state and data retention state. , it is clear that
Detailed explanation here will be omitted.

The second embodiment of the present invention has been described above.

Example (3) Next, a third embodiment of the present invention will be described.

The third embodiment relates to a memory circuit having two chip selection signals.

FIG. 5 is a partial circuit diagram of the memory circuit of the third embodiment, showing an internal chip selection signal generation circuit.

In Figure 5, A51 is an inverter circuit, A52 is an N
The OR circuit B51 is a military circuit signal (hereinafter referred to as C85') having a circuit configuration similar to that of the power supply voltage detection circuit B31 shown in FIG. 3 above.

The automatic data retention function of the third embodiment will be explained with reference to FIG.

The power supply voltage detection circuit B51 and the inverter circuit A51 are
The configuration is similar to that shown in FIG. 3 above. That is, when the power supply voltage decreases from the operating potential of the memory circuit and becomes below a predetermined voltage, control of the chip selection signal C851 is completely inhibited, the potential of the output terminal of the inverter circuit A5z becomes '1'' level, and the N
OR circuit A32VC is transmitted.

Therefore, the potential of %C8s' is not dependent on the other input signal C852vC of the NOR circuit 2, but becomes the non-selected state "1" level rC.

That is, the third performance output side also has an automatic data retention function. Furthermore, it is clear that the power consumption is low in the Vc1 standby state and data retention state as in the second embodiment.

Summary Above, the first aspect of the present invention. The second and third embodiments have been described.

As is clear from the above description, the present invention provides a memory circuit that consumes low power in standby state and data retention state and has an automatic data retention function.
It can be achieved with a simple configuration, and the practical soil effect is extremely impressive.

Incidentally, non-invention is defined in the above-mentioned No. 1. It goes without saying that the present invention is not limited to the second and third embodiments, but can be applied to various ranges that satisfy the spirit of the present invention.

[Brief explanation of drawings]

FIG. 1 is a partial circuit diagram of the first conventional example, and FIG. 2 is a partial circuit diagram of the second conventional example.
3 is a partial circuit diagram of the first embodiment of the present invention, FIG. 4 is a partial circuit diagram of the second embodiment of the present invention, and FIG. 5 is a partial circuit diagram of the second embodiment of the present invention. FIG. 3 is a partial circuit diagram of a third embodiment of the present invention. In addition, in the figure, Qll, Qzxx~Qztn, Q22. Q3
11-Q3'in, Qa 2. Qa a, Q4
1 is a P-channel MOS transistor IQa4. Q4
2. Q43. Q, i41 to Q44n are -N channel MO8) transistors, R11, R12, R13 are resistors, All, A21. A31. A41. A51
is an inverter circuit, A12. &22. &52 is NOR,
Circuit, B11°B21. R31, R41, Bst are power supply voltage detection circuits, Sl, CM2. to S3. C
S4. CS51. C852 is a chip selection signal, C8
s', C82', C83', C84',
C85' is an internal circuit signal of a chip selection signal, N11.
Nl 2°N21. N31. There are N41 nodes.萬 1 Figure Z Figure L-1111--1 Leaf 3 Figure 1' ,,J Mother-in-law Δ-Cause

Claims (1)

[Claims] (1) Chip selection signal The power supply voltage detection circuit that has a low voltage data retention function and fully detects that the supplied VC and power supply voltage is below a predetermined voltage. The circuit includes a series circuit including n unidirectional elements having a potential drop and an MO8 transistor that uses a chip selection signal as a gate input signal, and when the power supply voltage is below a predetermined voltage, the chip selection signal is used. A memory circuit characterized by having a function of completely inhibiting operation.