JPS59132245A - Semiconductor integrated circuit device - Google Patents

Abstract

PURPOSE:To make the input frequency of the 1st stage equal to a possible maximum frequency by bringing a voltage between a drain side terminal and a source side terminal of a frequency division circuit cell of each stage to a range possible for normal operation in a prescaler IC. CONSTITUTION:A resistive element having respectively prescribed resistance values r1, r2 is inserted between a power supply terminal 1 and a drain side terminal or a source side terminal of a 1/2 frequency dividing circuit cell S1 of the 1st stage and between drains or sources of the 1/2 frequency dividing circuit cell S1 of at least the 1st stage and a 1/2 frequency division circuit cell S2 of the 2nd stage respectively. Since a voltage between the drain side terminals and source side terminals of the 1/2 frequency division circuit cells S1-Sn of each stage is brought to a voltage value within the voltage range between the drain side terminals and source side terminals possible for normal operation when a prescribed voltage is applied to the power supply terminal 1, the possible maximum frequency of normal operation of the frequency dividing circuit cell S1 is made nearly equal to the input signal frequency of the frequency dividing circuit cell S1 of the 1st stage.

Description

[Detailed Description of the Invention] [Technical Field of the Invention] The present invention relates to a semiconductor integrated circuit device (rC), and relates to a semiconductor integrated circuit device (rC), which is an enhanced type field effect transistor (hereinafter referred to as rK).
-Master-slave type JK using FETJ)
This invention relates to a prescaler IC configured by cascading a plurality of external frequency dividing circuit cells each consisting of 70 flip blocks.

[Prior art]

FIG. 1 is a circuit diagram showing the configuration of an example of a conventional prescaler IC.

In the figure, S, +82. e ----+ Sn is formed on the main surface of a gallium arsenide (GaAs) substrate. It consists of a master-slave type JK flip-flop using E-PET as a basic element, and successively cascaded solder P.
In the I-structure external frequency divider cell (hereinafter abbreviated as "frequency divider cell"), fil is commonly connected to the drain side terminals of the frequency divider cells S, , S2゜----+Sn. (2) is a power supply terminal for applying the voltage ■DD to the drain side terminal of the frequency dividing circuit cells s, , s2. ---
, s.

(3a) is the frequency f of the first-stage frequency dividing circuit cell S1. C terminal to which the signal of (3
b) is the C terminal to which a complementary signal of the signal input to the C terminal (3a) of the frequency divider cell S1 is input, and (4a) is the C terminal of the frequency divider cell Sn in the final stage (nth stage). Circuit cell S,
The frequency f input to the C terminal (3a) of. The signal is divided by each frequency dividing circuit cell S, , S2゜---, Sn to obtain a frequency f. /2 n signal is output from the C terminal, (4b) is the frequency dividing circuit cell Sn, and the frequency dividing circuit cell S
The frequency f input to the C terminal (3b) of 1. The signal is divided by each frequency dividing circuit cell S1, s2', ---, sn to a frequency f. /2n signal and output
It is a terminal.

By the way, in the configuration of this conventional example, each frequency dividing circuit cell s1
．． s2. ---, the input signal frequency of sn is fo+
fo/2. ---1, fJz, so the distribution range of the input signal frequency of these cells Sat S2+ ---, Sn is extremely wide, and each frequency divider circuit cell S1゜S
Since the drain side terminals of 21---+S are commonly connected to the power supply terminal +1+, these cells S1゜S2. ---, the drain side terminal voltage of Sn is all uniformly equal to the voltage DD of the power supply terminal ft). Moreover, each frequency dividing circuit cell s1. s2. ---+ Since the structures of sn are the same, these cells s1. s2. ---
− and sn have the same upper limit of the drain side terminal voltage range that allows normal operation with respect to the input signal frequency.

FIG. 2 shows frequency divider circuit cells S, S2. ---
In the figure, the horizontal axis is the input signal frequency (unit: GH2), and the vertical axis is the drain side terminal voltage (unit: GH2). unit ■), and the curve (a)
and (b) respectively indicate the upper limit, 7, and lower limit of the drain side terminal voltage range in which normal operation is possible.

As shown in FIG. 2, although the first-stage frequency divider cell S1 with the highest input signal frequency can operate normally up to an input signal frequency of 3[)H2 or more, the frequency divider cell S1 has the highest input signal frequency. Since the upper limit of the drain side terminal voltage is limited to be equal to the upper limit of the drain side terminal voltage of the frequency dividing circuit cell Sn having the lowest input signal frequency, the input signal frequency is limited to 20H2 or less.

In this way, in this conventional example, the first stage frequency dividing circuit cell S1
The disadvantage is that the input signal frequency must be significantly lower than the maximum frequency at which normal operation is possible.

[Summary of the invention]

The present invention was made with the purpose of improving such drawbacks, and is aimed at connecting the power supply terminal and the drain side (or source side) terminal of the first stage frequency divider cell having the highest input signal frequency, and at least the first stage frequency dividing circuit cell. By inserting resistance elements each having a predetermined resistance value between the drain side (or source side) terminals of the circuit cell and the second stage frequency divider cell, the input of the first stage frequency divider circuit cell can be The object of the present invention is to provide a Gleascale C in which the signal frequency is approximately equal to the maximum frequency at which the first stage frequency dividing circuit cell can operate normally.

[Embodiments of the invention]

FIG. 3 is a circuit diagram showing the configuration of a grease scaler C according to an embodiment of the present invention.

In the figure, the same reference numerals as those in the conventional example shown in FIG. 1 indicate equivalent parts. rl is connected between the power supply terminal (1) and the drain side terminal of the first stage frequency dividing circuit cell S1, and has a resistance value r
1, r2 + r3+---, rn are connected between the drain side terminal of frequency divider circuit cell S1 and the drain side terminal of frequency divider circuit cell S2, and between the drain side terminal of frequency divider circuit cell S2 and the divider, respectively. Between the drain side terminal of the frequency dividing circuit cell S3 (not shown) Between the drain side terminal of the 1-1-1 frequency dividing circuit cell 5n-1 (not shown) and the drain side terminal of the frequency dividing circuit cell Sn connected to resistance value 2”z + r3 +
---+ r . These resistance elements r1. r2. r3---rn is a semiconductor resistance element formed on the main surface of the GaAs substrate on which the frequency dividing circuit cell S1+ 82 + ---+ 8 is formed, or a thin film resistance element formed on the main surface of this GaAs substrate. It is.

The configuration of this example is the resistance element rIT r21 r31
--1+ rn The configuration is the same as that of the conventional example shown in FIG. 1 except for rn.

In this embodiment, when voltage ■DD is applied to the power supply terminal 11), each frequency dividing circuit cell s,, s21−−−+S
The voltage values applied to the drain side terminals of n can be made to have two different values depending on the resistance elements r''-''-''n, respectively.

For example, in FIG. 3, since the structures of the frequency dividing circuit cells SST2'-""Sn are the same, these cells s
,, s2. ---, The resistance value between the drain side terminal and the source side terminal of Sn was uniformly approximated to R8, and the resistance value of the drain side terminal part of the cells after frequency dividing circuit cell S3 was set to zero. In this case, the circuit configuration shown in FIG.
It can be approximated as a DC circuit as shown in FIG. 4.

In FIG. 4, 1□, 1°, and 13 are respectively between the drain side and source side terminals of the frequency divider cell S1 and the drain side and source side of the frequency divider cell S2 when voltage vDD is applied to the power supply terminal fi+. Between terminals and frequency divider circuit cell S3. --- is the sum of the currents flowing between the drain side and source side terminals of Sn. These currents 11.1□
, 13 are expressed by the following formula.

From the above CD equation, the voltage between the drain side and source side terminals of frequency divider circuit cell S, v19, and the drain side of frequency divider circuit cell s2,
Voltage between source side terminals v2 and frequency divider circuit cell 5 ---,
The voltage v3 between the drain side and source side terminals 1 of i3n is given by the following formula.

For example, r 1 = r 2 = r 3 = r≧ and n =
6/1/(1=-17/64 If the frequency division is 0, the voltage between the drain side and source side terminals v,, '
v2. v3 is expressed by the following formula.

However, K=r/Ro.

Here, as an example, ■DD""・5V, K = 0.
Considering the case where 5, it becomes.

In such a /64 frequency divider C, as shown in Figure 2, the maximum input that allows normal operation when the voltage v1 between the drain side and source side terminals of the first stage frequency divider circuit cell S is 5 OV. The signal frequency is 3GH.

Therefore, when the input signal frequency of the frequency dividing circuit cell s1 is set to 3GH, the voltage between the drain side and source side terminals of the second stage frequency dividing circuit cell S1 becomes 3. '75■, the input signal frequency becomes 1.50H2, and the voltage between the drain side and source side terminals of the frequency dividing circuit cells s, s, s s from the third stage onwards is Va + V4 + Vs
+Va is all 1.07V, and the input signal frequency is 1.07V. ,'i'5GH2,0,3'750H2,0,188
GH2,0,094GH. These frequency divider circuit cells s2. s3. s,,s5. It can be seen from FIG. 2 that s6 can operate normally.

As described above, in this embodiment, the voltage ■ is applied to the power supply terminal +1+. When , is applied to each frequency divider circuit cell S,.

S2. ---, the voltage between the drain-side and source-side terminals of Sn is set by the resistance element r1W r2 *-1-+ rn, and the drain $1 of these cells S S ---, which allows normal operation of Sn. can be made to have a voltage value within the voltage range between the side and source side terminals, so the input signal frequency of the first stage frequency divider circuit cell S1 can be set to the maximum frequency at which this first stage frequency divider circuit cell S1 can normally operate. They can be made almost equal.

In this embodiment, frequency divider circuit cells S, , S2 . ---
.

The drain side terminal of Sn was connected to the power supply terminal (1) and the source side terminal was connected to the ground terminal (2), but in contrast, the source side terminal was connected to the power supply terminal fll and the drain side terminal was connected to the ground terminal (2). 2) may be connected.

In addition, in this embodiment, the frequency dividing circuit cells S1, S2, --
-, 5 nt-GaAs substrate, but this does not necessarily have to be a GaAs substrate, and other semiconductor substrates may be used.

〔Effect of the invention〕

As explained above, according to the present invention, a plurality of V2 frequency divider circuit cells each consisting of a master fist slave type JK flip-flop using E-ICT are connected in cascade, and the outer frequency divider circuit cells are In a prescaler C having a power supply terminal for applying a power supply voltage to the drain side (or source side terminal), the drain side terminal (or source side terminal) of the above-mentioned outer frequency dividing circuit cell in the first stage and the above power supply terminal are connected. and between the drain/r side (or source side) terminals of the external frequency divider circuit cell in the first stage and the external frequency divider circuit cell in the second stage, each having a resistance value of about 100%. The input signal frequency of the first stage external frequency divider circuit cell is set to the voltage value within the voltage range between the drain side and source side terminals in which the element can be operated normally. The frequency can be made approximately equal to the maximum frequency at which the four-frequency frequency divider circuit cell can normally operate.

[Brief explanation of drawings]

FIG. 1 is a circuit diagram showing the configuration of an example of a conventional Briscaler E-C, and FIG. 2 is an example of a relationship curve between the input signal frequency of the frequency divider circuit cell of the above-mentioned conventional example and the drain side terminal voltage that allows normal operation. 3 is a circuit diagram showing the configuration of a grease scaler IC according to an embodiment of the present invention, and FIG. 4 is a DC equivalent circuit diagram showing an example of the circuit configuration of the above embodiment. In the figure, (1) is a power supply terminal, Sl, S2. -m-,
Sn is an outer frequency divider circuit cell, rH* r2. ---
, r is a resistance element. Note that the same reference numerals in the figures indicate the same or corresponding parts. Agent Tsukuda Kuzuno - (1 other person) Figure 1

Claims (1)

[Claims] The outer frequency divider circuit is constructed by cascading a plurality of X/4 frequency divider cells each consisting of a master/slave type JK7 lip-frog using a +0 enhancement type booster transistor. In a prescaler integrated circuit device having a power supply terminal for applying a power supply voltage to a drain side terminal (or source side terminal), the drain side terminal (or source side terminal) of the above-mentioned sylloscope frequency divider circuit cell of the first stage and the above power supply terminal and at least the drain side (or source side) of the above-mentioned frequency dividing circuit cell of the first stage and the above-mentioned external frequency dividing circuit cell of the second stage.
A semiconductor integrated circuit device characterized in that σ\ resistance elements each having a sufficient resistance value are inserted between terminals.