JPS59144164A - Manufacture of hybrid integrated circuit - Google Patents

Manufacture of hybrid integrated circuit

Info

Publication number
JPS59144164A
JPS59144164A JP58019220A JP1922083A JPS59144164A JP S59144164 A JPS59144164 A JP S59144164A JP 58019220 A JP58019220 A JP 58019220A JP 1922083 A JP1922083 A JP 1922083A JP S59144164 A JPS59144164 A JP S59144164A
Authority
JP
Japan
Prior art keywords
pattern
resistor
circuit
thin film
anodic oxidation
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP58019220A
Other languages
Japanese (ja)
Inventor
Yasushi Suda
康司 須田
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
NEC Corp
Original Assignee
NEC Corp
Nippon Electric Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by NEC Corp, Nippon Electric Co Ltd filed Critical NEC Corp
Priority to JP58019220A priority Critical patent/JPS59144164A/en
Publication of JPS59144164A publication Critical patent/JPS59144164A/en
Pending legal-status Critical Current

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  • Apparatuses And Processes For Manufacturing Resistors (AREA)
  • Fixed Capacitors And Capacitor Manufacturing Machines (AREA)

Abstract

PURPOSE:To prevent the disconnection due to the leakage of compound solution of resistance pattern or improper pinholes by locally exposing the vicinity of the connection of a resistance circuit network connected to an anodic oxidation continuity circuit. CONSTITUTION:A resistor tantalum thin film 5 is bonded on a substrate 1, and a resistor pattern is formed by selective etching. A resist pattern 3 exposed on the surface of the resistance pattern in the vicinity of the resistor pattern connection unit is formed, an anodic oxidation is performed on an etching stop layer 4, and an anodic oxidation layer 6 is formed. Then, the exposed resistance pattern unit is oxidatively broken to become disconnected state. Then, electrode metal film 7 which is made of nichrome alloy, palladium and gold is bonded to the entire substrate, and the oxidized breakdown part is conducted.

Description

【発明の詳細な説明】 本発明は混成集積回路の製造方法にかかシ、特に信頼性
の優れた高品質なタンタル薄膜RC回路の製造方法に関
するものでおる。
DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a method of manufacturing a hybrid integrated circuit, and more particularly to a method of manufacturing a high quality tantalum thin film RC circuit with excellent reliability.

従来、同一基板上に形成された薄膜コンデンサと薄膜抵
抗からなる薄膜回路の製造方法は大路次のとおりである
Conventionally, a method for manufacturing a thin film circuit consisting of a thin film capacitor and a thin film resistor formed on the same substrate is as follows.

先ずガラス又はセラミック等の絶縁基板上にベータ又は
アル7アータンタル層をスパッター法により被着させ、
該タンタル層を選択エツチングによシ所望のコンデンサ
パターン全形成する。次にコンデンサとして用いるべく
定められた領域中の該タンタル層を選択的に陽極酸化し
、エツチングストップ層を形成し、この後、上記基板全
体にスパッター法によシ抵抗体用タ/タル薄膜を被着生
成する。次に該抵抗体用薄膜全7オトレジスト処理をエ
ツチング技術により所望とする抵抗回路網を形成した後
、前記コンデンサー領域の所定の箇所をポジ型フォトレ
ジストを保護マスクとし、再び陽極酸化し、コンデンサ
ー膜を形成する。該保護マスクは公知の方法で剥離除去
する。次に、上記によシ得られた基板の全体にニクロム
合金、パラジューム、金からなる上部電極を真空蒸着又
はマグネトロンスパッター法で被着生成し、フォトレジ
スト処理によシ所望のパターンを形成した後、タンタル
抵抗I、くターン面を陽極酸化又は、レーザトリミング
方法によシ所望の抵抗値調節することによシ薄膜回路を
製造する。
First, a beta or al-7 artantalum layer is deposited on an insulating substrate such as glass or ceramic by sputtering,
The tantalum layer is selectively etched to form the entire desired capacitor pattern. Next, the tantalum layer in the area defined to be used as a capacitor is selectively anodized to form an etching stop layer, and then a resistor thin film is deposited over the entire substrate by sputtering. Forms adhesion. Next, a desired resistor network is formed by etching all seven thin film resistors for the resistor, and then a predetermined portion of the capacitor region is anodized again using a positive photoresist as a protective mask, and the capacitor film is form. The protective mask is peeled off using a known method. Next, an upper electrode made of nichrome alloy, palladium, and gold is deposited on the entire substrate obtained above by vacuum evaporation or magnetron sputtering, and a desired pattern is formed by photoresist treatment. A thin film circuit is manufactured by adjusting the desired resistance value of the tantalum resistor I by anodizing the tantalum surface or by laser trimming.

しかしながら上記の製造方法によれば、特に微細傾向化
が進むパターン設計に於いては大きな支障が生じてくる
。すなわち、微細化になるにつれ、コンデンサ及び抵抗
パターンは複雑となシ、シかも、小型化に伴う、抵抗回
路網形成空間の減少によシ、パターン設計に以下のよう
な無理が生じてくる。
However, according to the above-mentioned manufacturing method, a major problem arises, especially in pattern design where the trend towards finer patterns is progressing. That is, as miniaturization progresses, capacitor and resistor patterns may become more complex, and as miniaturization accompanies a reduction in the space for forming a resistor network, the following difficulties arise in pattern design.

薄膜回路は同一基板内にコンデンサ及び抵抗が複数個形
成されることで品質特性全満足させている。しかも、微
細化になることで該抵抗回路網を自然と密集化し、コン
デンサ全陽極酸化するためにあらかじめ形成されている
化成回路パターンに接続が避けられない抵抗回路網が生
じてくる。この場合、前記した如く、コンデンサーとな
るべき所定領域を7オトレジストを保護マスクとし陽極
酸化する際、該保護マスクの耐圧、密着性等が非常に重
要視される。すなわち、酸性溶液中で1〜2時間陽極酸
化するため、抵抗回路上に形成された保論マスクに欠陥
があシ表面リーク等によシ、液が抵抗膜面に触れると急
激に電流が流れることによシ酸化破壊し、該抵抗回路は
断線し、薄膜回路基板そのものが不良となる。この現象
は、前記方法では避けられない問題である。
Thin film circuits satisfy all quality characteristics by forming multiple capacitors and resistors on the same substrate. Moreover, miniaturization naturally makes the resistor network denser, resulting in a resistor network that is inevitably connected to a chemical circuit pattern previously formed for fully anodizing the capacitor. In this case, as described above, when a predetermined region to become a capacitor is anodized using a 7-otoresist as a protective mask, the pressure resistance, adhesion, etc. of the protective mask are very important. In other words, since anodization is performed in an acidic solution for 1 to 2 hours, the mask formed on the resistor circuit may be defective, causing surface leaks, etc., and when the solution touches the resistive film surface, a sudden current flows. In particular, oxidation damage occurs, the resistance circuit is disconnected, and the thin film circuit board itself becomes defective. This phenomenon is an unavoidable problem in the above method.

本発明の目的は上記製造方法の欠点を是正した混成集積
回路の製造方法を提供することにある。
SUMMARY OF THE INVENTION An object of the present invention is to provide a method for manufacturing a hybrid integrated circuit that corrects the drawbacks of the above-mentioned manufacturing methods.

すなわち、抵抗回路網を形成した後、所定佃域のコンデ
ンサパターン部を7オトレジストを保護マスクとして酸
性溶液中で陽極酸化する際、該保護マスクパターンを所
定のコンデンサ領域部に加え、更に陽極酸化用導通回路
に接続されて形成されている抵抗回路の接続部近傍を算
出形成することによシ、陽極酸化処理開始と同時に集中
電圧をかけることによシ酸化破壊させ、同抵抗回路パタ
ーン部の化成液リーク等による断線をなくすこと?特徴
とする混成集積回路の製造方法である。
That is, after forming a resistor network, when anodic oxidizing a capacitor pattern portion in a predetermined area in an acidic solution using a 7-otoresist as a protective mask, the protective mask pattern is added to the predetermined capacitor region portion, and a By calculating and forming the vicinity of the connection part of the resistor circuit that is formed by being connected to the conductive circuit, by applying a concentrated voltage at the same time as the start of the anodizing process, it is oxidized and destroyed, and the chemical formation of the resistor circuit pattern part is performed. Eliminating disconnections due to liquid leaks, etc.? This is a method for manufacturing a hybrid integrated circuit.

以下、本発明をタンタル薄膜RC回路の製造?例とし、
図面によし詳細に説明する。
Hereinafter, the present invention will be explained about the production of tantalum thin film RC circuit. As an example,
This is explained in detail in the drawings.

第1図から第碕図は本発明による混成集積回路の製造工
程に於ける断面図である。充分に洗浄された部分ダレー
ズ絶縁基板1上にスパッタリング法によシタンタル系薄
膜2を約400OAの厚さに形成する(第1図)。次に
公知のフォトエツチング法に基づいてタンタル系薄膜2
をエツチング液、所望のコンデンサパターンを形成する
(第2図)。次にボージ型フォトレジスト3例えば東京
応化製のOF’PR−7RFを約12〜15μm塗布し
た後、赤外線乾燥炉中で100℃、30分のプリベーク
をし、該レジスト膜を、選択的に露光し、現像液例えば
東京応化製0FPR,−7Rを用いて、感光部を溶解し
、誘電体となるべきタンタル系薄膜が露出するべき所望
とするレジストパターンを形成する(第3図)。次に前
記基板を0.0196クエン酸溶液中150V、10分
の定電圧化成条件で陽極酸化することによシ肪電体とな
るべき箇所に酸化膜を形成し、メンタルエツチング液の
エツチングストップ層4を形成する(第4図)。次にス
パッタリング法によシ抵抗体用タンタル系薄膜5を約3
0OA基板上全面に付着せしめ(第5図)、フッ酸、硝
酸混合溶液を用い選択エツチングで所望とする抵抗体パ
ターンを形成する(第6図ン。次にエツチングストップ
層形成方法と同条件でエツチングストップ層表面と更に
、陽極酸化用導通回路パターンと接続している抵抗パタ
ーンの接続部近傍の該抵抗パターン表面を約40μ程度
露出したレジストパターン3を形成しく第7図)、再度
0.01%クエン酸溶液中200V、2時間の定電圧化
成条件で陽極酸化することによりエツチングストップ層
上に陽極酸化を施し、陽極酸化膜6を形成すると共に、
陽極酸化開始と同時にエツチングストップ層のない上記
露出抵抗パターン部に前記エツチングストップ層生成条
件の電圧が急激にかかることによシ該露出抵抗パターン
部を酸化破壊させ断線     ゛状態とする(第3図
)。次に基板全体にスパッタリング法によシニクロム合
金、パラジューム及び金からなる上部電極用金属膜7を
付着せしめ、前記酸化破壊部を導通させるべく公知の7
オトエツチング技術で形成しく第9 図)、コンデンサ
及び抵抗を含む回路網を得る。最後に大気中で安定化熱
処理?施した後、レーザトリミング法にょp抵抗値の調
節を行う。
FIGS. 1 to 1 are cross-sectional views in the manufacturing process of a hybrid integrated circuit according to the present invention. A tantalum thin film 2 having a thickness of about 400 OA is formed by sputtering on a thoroughly cleaned partially undulated insulating substrate 1 (FIG. 1). Next, a tantalum-based thin film 2 is formed using a known photoetching method.
using an etching solution to form the desired capacitor pattern (FIG. 2). Next, a Borge type photoresist 3, for example, OF'PR-7RF manufactured by Tokyo Ohka Co., Ltd., is applied to a thickness of about 12 to 15 μm, and then prebaked at 100°C for 30 minutes in an infrared drying oven, and the resist film is selectively exposed to light. Then, using a developer such as 0FPR, -7R manufactured by Tokyo Ohka Chemical Co., Ltd., the photosensitive area is dissolved and a desired resist pattern is formed in which the tantalum thin film to be the dielectric is exposed (FIG. 3). Next, the substrate is anodized in a 0.0196 citric acid solution at a constant voltage of 150 V for 10 minutes to form an oxide film at the portions that are to become the electrolyte, and an etching stop layer for the mental etching solution. 4 (Figure 4). Next, a tantalum-based thin film 5 for a resistor is deposited by sputtering.
It is deposited on the entire surface of the 0OA substrate (Fig. 5), and a desired resistor pattern is formed by selective etching using a mixed solution of hydrofluoric acid and nitric acid (Fig. 6).Next, under the same conditions as the etching stop layer formation method. A resist pattern 3 is formed which exposes the surface of the etching stop layer and the surface of the resistor pattern in the vicinity of the connecting portion of the resistor pattern connected to the conductive circuit pattern for anodic oxidation by about 40 μm (FIG. 7). % citric acid solution under constant voltage anodization conditions of 200 V for 2 hours, the etching stop layer is anodized to form an anodic oxide film 6.
Simultaneously with the start of anodic oxidation, a voltage under the conditions for forming the etching stop layer is rapidly applied to the exposed resistor pattern portion without the etching stop layer, causing the exposed resistor pattern portion to be oxidized and destroyed, resulting in a disconnection state (Fig. 3). ). Next, a metal film 7 for an upper electrode made of a synichrome alloy, palladium, and gold is deposited on the entire substrate by sputtering, and a well-known 7
By using etching techniques (FIG. 9), a circuit network including capacitors and resistors is obtained. Finally, stabilization heat treatment in the atmosphere? After this, the p resistance value is adjusted using a laser trimming method.

以上の如く、本発明の方法によれば陽極酸化用導通回路
パターンに接続している抵抗パターンは、接続部近傍を
陽極化成開始と同時に集中電圧を急激にかけ破壊断線さ
せることで該抵抗パターンは化成液リークでの断憩又は
ビンホール不良が皆無となpl しかも上部電極膜のパ
ターン形成の際、断線部の接続は容易であシ何んら品質
の変わらぬ信頼性の優れた混成集積回路の製造が可能と
なる。
As described above, according to the method of the present invention, the resistance pattern connected to the conductive circuit pattern for anodization is destroyed by rapidly applying a concentrated voltage to the vicinity of the connection part at the same time as the start of anodization, causing the resistance pattern to break. There are no breaks or bottle hole defects due to liquid leaks.Furthermore, when forming the pattern of the upper electrode film, it is easy to connect the broken wires.Production of highly reliable hybrid integrated circuits with no change in quality. becomes possible.

又、微細化及び小型化に伴う抵抗回路網の設計も容易と
なる。
Furthermore, it becomes easier to design a resistor network as miniaturization and miniaturization occur.

【図面の簡単な説明】[Brief explanation of the drawing]

第1図から第(ロ)図は本発明の詳細な説明する為の混
成集積回路の製造工程の断面図である。 尚、図に於いて、1・・・・・・部分ダレーズセラミッ
ク基板、2・・・・・・タンタル系薄膜、3・・・・・
・ポジ型フォトレジスト、4・・・・・・エツチングス
トップ層、5・・・・・・抵抗体用タンタル薄膜、6・
・・・・・陽極酸化膜、7・・・・・・ニクロム、 )
’d 、 ku購成膜でめる。
FIG. 1 to FIG. 1B are cross-sectional views of the manufacturing process of a hybrid integrated circuit for explaining the present invention in detail. In the figure, 1... Partially dalesed ceramic substrate, 2... Tantalum thin film, 3...
・Positive photoresist, 4...Etching stop layer, 5...Tantalum thin film for resistor, 6.
...Anodic oxide film, 7...Nichrome, )
'd, ku purchased and deposited.

Claims (1)

【特許請求の範囲】[Claims] 絶縁基板上にRC回路を形成する上で、コンデンサーと
なるべき所望パターン部を7オトレジスト処理で選択的
に酸性溶液中で陽極酸化させる工程に於いて、該陽極酸
化用導通回路に接続された抵抗回路網の接続部近傍を局
部的に露出させることを特徴とした混成集積回路の製造
方法。
When forming an RC circuit on an insulating substrate, a resistor connected to the conductive circuit for anodizing is used in the step of selectively anodizing a desired pattern portion that will become a capacitor in an acidic solution using a 7-otoresist process. A method of manufacturing a hybrid integrated circuit characterized by locally exposing the vicinity of a connection part of a circuit network.
JP58019220A 1983-02-08 1983-02-08 Manufacture of hybrid integrated circuit Pending JPS59144164A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP58019220A JPS59144164A (en) 1983-02-08 1983-02-08 Manufacture of hybrid integrated circuit

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP58019220A JPS59144164A (en) 1983-02-08 1983-02-08 Manufacture of hybrid integrated circuit

Publications (1)

Publication Number Publication Date
JPS59144164A true JPS59144164A (en) 1984-08-18

Family

ID=11993280

Family Applications (1)

Application Number Title Priority Date Filing Date
JP58019220A Pending JPS59144164A (en) 1983-02-08 1983-02-08 Manufacture of hybrid integrated circuit

Country Status (1)

Country Link
JP (1) JPS59144164A (en)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH0648974U (en) * 1992-12-16 1994-07-05 小原株式会社 Shock absorber in pressurizing cylinder for welding machine

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH0648974U (en) * 1992-12-16 1994-07-05 小原株式会社 Shock absorber in pressurizing cylinder for welding machine

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