JPS5915323A - パルス遅延方法及び装置 - Google Patents

パルス遅延方法及び装置

Info

Publication number
JPS5915323A
JPS5915323A JP57123023A JP12302382A JPS5915323A JP S5915323 A JPS5915323 A JP S5915323A JP 57123023 A JP57123023 A JP 57123023A JP 12302382 A JP12302382 A JP 12302382A JP S5915323 A JPS5915323 A JP S5915323A
Authority
JP
Japan
Prior art keywords
pulse
write
delay time
address
read
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
JP57123023A
Other languages
English (en)
Japanese (ja)
Other versions
JPH0221694B2 (2
Inventor
Satoshi Inomata
猪俣　敏
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
SPC Electronics Corp
Shimada Rika Kogyo KK
Original Assignee
SPC Electronics Corp
Shimada Rika Kogyo KK
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by SPC Electronics Corp, Shimada Rika Kogyo KK filed Critical SPC Electronics Corp
Priority to JP57123023A priority Critical patent/JPS5915323A/ja
Publication of JPS5915323A publication Critical patent/JPS5915323A/ja
Publication of JPH0221694B2 publication Critical patent/JPH0221694B2/ja
Granted legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03K—PULSE TECHNIQUE
    • H03K5/00—Manipulating of pulses not covered by one of the other main groups of this subclass
    • H03K5/13—Arrangements having a single output and transforming input signals into pulses delivered at desired time intervals
    • H03K5/131—Digitally controlled
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03K—PULSE TECHNIQUE
    • H03K5/00—Manipulating of pulses not covered by one of the other main groups of this subclass
    • H03K2005/00013—Delay, i.e. output pulse is delayed after input pulse and pulse length of output pulse is dependent on pulse length of input pulse
    • H03K2005/0015—Layout of the delay element
    • H03K2005/00234—Layout of the delay element using circuits having two logic levels
    • H03K2005/0026—Layout of the delay element using circuits having two logic levels using memories or FIFO's

Landscapes

  • Physics & Mathematics (AREA)
  • Nonlinear Science (AREA)
  • Electronic Switches (AREA)
  • Pulse Circuits (AREA)
JP57123023A 1982-07-16 1982-07-16 パルス遅延方法及び装置 Granted JPS5915323A (ja)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP57123023A JPS5915323A (ja) 1982-07-16 1982-07-16 パルス遅延方法及び装置

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP57123023A JPS5915323A (ja) 1982-07-16 1982-07-16 パルス遅延方法及び装置

Publications (2)

Publication Number Publication Date
JPS5915323A true JPS5915323A (ja) 1984-01-26
JPH0221694B2 JPH0221694B2 (2) 1990-05-15

Family

ID=14850303

Family Applications (1)

Application Number Title Priority Date Filing Date
JP57123023A Granted JPS5915323A (ja) 1982-07-16 1982-07-16 パルス遅延方法及び装置

Country Status (1)

Country Link
JP (1) JPS5915323A (2)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS61163437U (2) * 1985-03-30 1986-10-09

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS61163437U (2) * 1985-03-30 1986-10-09

Also Published As

Publication number Publication date
JPH0221694B2 (2) 1990-05-15

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