JPS59156018A - Pulse delay circuit - Google Patents

Abstract

PURPOSE:To delay stably a signal to be delayed with less circuit constitution by providing an integration whose charging/discharging is controlled depending on the logical state between an output of a D type flip-flop DFF of a delay circuit and the signal to be delayed. CONSTITUTION:When the signal A to be delayed is changed from a low level to a high level, an output of an exclusive OR circuit EXOR goes from a low level to a high level, and the integration circuit 6 starts charging. When an output voltage of the integration circuit exceeds a reference voltage attended with the charging, an output D of an analog comparator 4 goes to a high level and a Q output E of the DFF1 is changed into a high level, an output B of the EXOR is inverted to a low level and the integration circuit 6 performs discharging. When the signal A to be delayed is changed into a low level after that, the output B of the EXOR goes to the high level, and when an output voltage of the integration circuit 6 exceeds the reference voltage, the output D of the analog comparator goes to a high level, the Q output E of the DFF1 is changed to the low level, the output B of the EXOR is inverted to the low level and the integration circuit performs the discharging.

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a pulse delay circuit using a D-type 1f921f021 circuit.

FIG. 1 is a block diagram of a conventional pulse delay circuit. In the figure, 1 is a D-tie 1F921F021 circuit (hereinafter abbreviated as DFF), 2 is a differential circuit, and 3 is a mono staple multipipulator (hereinafter abbreviated as mono multi). S is the signal to be delayed. The differentiating circuits used in the figure can be roughly divided into two types: analog differentiating circuits and digital differentiating circuits.

When using an analog differential circuit, it is generally capacitance.

Although a CR differentiator circuit consisting of a resistor is used, this method may not operate stably due to changes in ambient conditions such as power supply voltage and temperature. On the other hand, when using a digital differentiator circuit, there is a drawback that a large number of circuits, mainly several 7-lip, 70-tube circuits, are required.

An object of the present invention is to provide a pulse delay circuit that does not require the use of a differentiating circuit.

Hereinafter, one embodiment of the present invention will be explained with reference to FIG.
The data input of the FI is connected to the delayed signal and its clock input to the output of the analog comparator 4. In this example, the output of the DFF is inputted with the clock delay signal and the non-inverted output (hereinafter abbreviated as Q output) of the FF 1 mentioned above, and its output is connected to the accumulated charge discharging circuit of the integrating circuit 6. .

In this example, discharge is performed when the EXOR5 output is at a low level, and charging is performed when the output is at a high level. The output of the integrating circuit 6 is connected to the non-inverting output of the analog comparator 4, and the inverting input of the analog comparator 4 receives a reference voltage VIQF set as necessary.

In the circuit configuration as described above, when a signal as shown in FIG. 3A is input as a delayed signal, when this signal changes from low level to high level, the EXOR output changes from low level to high level. As a result, the integrating circuit starts charging. When the output voltage of the integrating circuit exceeds the reference voltage due to charging, the analog comparator output becomes high level, the Q output E of DFF changes to high level, and the EXOR output B output changes to high level, and the integrating circuit 6 performs a discharge.

After that, when delayed signal A changes to low level, EXO
R output B output is not level, integrate circuit 6 as above
When the output voltage exceeds the reference voltage, the output of the analog comparator becomes high level, the DFF+7)Q output E changes to low level, the EXOR output B output changes to low level, and the integrating circuit is discharged.

As can be seen from the above explanation, the Norculus delay circuit of the present invention requires only a small circuit configuration that does not include a differentiating circuit, and can stably transmit the delayed signal for a certain period of time (the time specified by the output of the integrating circuit). ), which is extremely effective. Furthermore, when it is desired to vary the delay time as necessary, a variable resistor is often used as the resistor used in the integrating circuit, and the time can be set programmably.

Note that the above embodiment is not used, and for example, if the change in DFF is a falling edge of the clock input, and if discharging is performed when the EXOR output is 7-element in the integrating circuit, a semiconductor may be used in the discharging circuit of the integrating circuit. It is clear that modifications such as when using an analog converter or when the non-inverting input of the analog converter is connected to the reference voltage and the output of the integrating circuit is connected to the inverting input are within the scope of the present invention. It is.

[Brief explanation of the drawing]

FIG. 1 is a block diagram of a conventional pulse delay circuit, and FIG. 2 is a block diagram showing an embodiment of the pulse delay circuit of the present invention.
FIG. 3 is a time waveform diagram showing signal waveforms of various parts in the pulse delay circuit of FIG. 2. 1...D type flip-flop circuit, 2...
...Differential circuit, 3...Mono table multipipulator, 4...Analog comparator,
5...Exclusive logic circuit, 6...Integrator circuit.

Claims (1)

[Claims] A pulse delay characterized in that an integrating circuit is provided in which charging and discharging are controlled according to the logical state of the output of the flip-flop and the signal to be delayed, and the delay time is controlled by the output of this integrating circuit. circuit.