JPH03201721A - Digital/analog converter - Google Patents

Abstract

(57) [Summary] This bulletin contains application data before electronic filing, so abstract data is not recorded.

Description

DETAILED DESCRIPTION OF THE INVENTION [Industrial Application Field] The present invention relates to a digital-to-analog converter (hereinafter referred to as a D/A converter) that converts a digital signal into an analog signal.

[Prior Art] Figure 4 is, for example, page 87 of Electronic Science Series 22 "Transistor DA-AD Converter" (Sanpo Publishing), Figure 3.
Conventional shown in 2 - Ladder shape D/used in the shell
FIG. 3 is a circuit diagram showing an A converter. This D/A converter converts digital data D by a timing signal.
A latch circuit (lO) that takes in n, a resistor with a resistance value r (ro~rn-2), and a resistor with a resistance value 2r (Ro-R
an analog switch (SWn-3W.-I) controlled by a resistor network (llr) constituted by n+1) and a digital data output from a latch circuit (10);
).

Next, the operation of the above conventional example will be explained. The digital data Dn is transferred to the latch circuit (
10). Analog signal Sochi (SW(1)
-5Wn-1) is the output data bn of the latch circuit (10)
-1bn-2 .

When the output data is bk・1 (0≦≦nt) and all other digits are 0, the output voltage Vk is determined by connecting the connection point between the resistors (rk) and (Rk) to Pk. Then, the analog conversion circuit (11
The equivalent circuit of > is shown in Figure 5, so vk=vS7
It becomes 3. In Figure 5, Pk+ next to the output side of point Pk
The output voltage Vk+1 at one point is expressed by. Considering the same way, the output terminal, that is, P. The voltage Vn-1 at the -1 point is expressed by the following equation.

Vn-FVk(n-1-k)" 2., -1-kVk
The above explained the case where only bh is l, but
When multiple digits of bn-1bn-2...bk...bO are 1, the value is the sum of the output voltages that occur when each digit is 1, so the digital A voltage proportional to an arbitrary value of data D11 is obtained.

[Problems to be Solved by the Invention] In the conventional D/A converter as described above, among the analog switches (swQ to 5Wn-1), one that changes from on to off and one that changes from off to on occur at the same time. Digital data D that exists. If a change occurs,
Digital data D due to the difference in operating time of analog switch (SWU-SWn=1). An analog signal having an invalid value outside the range between the old value before the change and the new value after the change is generated. For example, in a 4-bit D/A converter, the old value is r 100OJ, and the new value is rollJ.
If the off-time Tafs of the analog switch (S!■~5Wn-1) of the analog conversion circuit (11) is longer than the on-time T0°, first, a new signal is applied.

The lower 3 bits with a value of 1 are turned on, and then the upper 1 bits with a new value of 0 are turned off. Therefore, an analog signal corresponding to the value "IIIJ" is output during the period from the moment when the lower 3 bits turn on until the upper 1 bit turns off. There was a problem that it caused malfunction.

A filter circuit can be used to remove the above-mentioned invalid analog signals, but since using a filter circuit reduces the rate of change of the analog signal, high-speed response is required. could not be applied to the system.

The present invention was made to solve the above-mentioned problems, and it is an object of the present invention to provide a D/A converter that does not output incorrect analog signals and has high-speed response.

[Means for Solving the Problems] A digital-to-analog converter according to the present invention includes a latch circuit that receives and holds digital data, and an analog conversion circuit that outputs an analog signal proportional to the digital data output from the latch circuit. a first D/A converter section and a second D/A converter section connected in parallel to each other; an output of the first D/A converter section and an output of the second D/A converter section;
A high-order priority circuit receives the output of the /A converter section and outputs a higher-order analog signal, and transfers the digital data to a latch circuit of the first D/A converter section and a second D/A converter section. A control circuit that causes the latch circuits to hold the latch circuit alternately and resets the latch circuit that does not hold the latch circuit after a predetermined time elapses from the latch operation of the latch circuit that holds the latch circuit.

[Function] The control circuit according to the present invention causes the latch circuits of the pair of D/A converters to hold digital data alternately,
The latch circuit that is not held is then reset. The analog conversion circuit thereby changes the switching state in only one direction, either from off to on or from on to off. The high order priority circuit outputs the higher order of the analog outputs of the pair of D/A converters.

[Example] FIG. 1 is a block diagram showing one embodiment of the present invention.

In the figure, a first D/A converter (1) includes a latch circuit (la) for receiving and holding digital data Dn, and converting the digital data output from the latch circuit (la) into an analog signal. and an analog conversion circuit (lb) for The internal circuit of the analog conversion circuit (lb) is constructed as shown in FIG. Since this is the same as the configuration shown in FIG. 4 in the conventional example, the explanation thereof will be omitted. Similarly, the second D/A converter (2) includes a latch circuit (2a) and an analog conversion circuit (2b), and is connected in parallel with the first D/A converter (1). The high priority circuit (3) connects the first D/A converter (1) and the second D/A converter (1).
From each of the analog signal outputs S1 and S2 of the A converter, the higher level one (the one with larger voltage) is selected and output. Control circuit (4> is a latch circuit.

A flip-flop circuit (4a) that provides the operation mode of (1a, 2a), a delay circuit (4b) that delays the timing signal for the latch circuit (la, 2a), a delay circuit (4b) and a flip-flop circuit. (4a) from each output signal and timing signal to the latch circuit (la
, 2a), AND circuits (4c, 4d,
4e, 4f).

Next, the operation of the above embodiment will be explained. Figure 3 shows
Digital data Dn is transferred from Dno to Dnl, Dn2. D
. 3 is a time chart showing signals of each part when changing in the order of 3. Digital data D. The size of is Dn
It is assumed that there is a relationship O<Dy12<Dnl<Dn3, and digital data D. 0 is already held in the second D/A converter (2) and the first D/A converter (1
)'s latch circuit (la) is set to O by the reset signal R1.
, and the Q of the flip-flop circuit (4a) is
Assume that the output is l. When the time reaches tl from this state, the digital data Dn is read from DnO. I
A timing signal and digital data Dnl are applied to change the timing signal, and the following first to tenth operations are performed continuously according to the timing signal.

mass, the first operation, that is, the first D/A converter (
1) new digital data D. The operation of outputting an analog signal proportional to l will be explained. Since the Q output of the flip-flop circuit (4a) is 1, the timing signal R is supplied to the latch circuit (la) through the AND circuit (4c) as the latch signal Ll. The latch signal L1 transfers the digital data Dn1 to the latch circuit (
la) and retained digital data D. 1
An analog quantity proportional to is produced by the analog conversion circuit (1b) and becomes an analog signal output S1.

During the above first operation, in the process where the digital data Del becomes the analog signal S1 by the analog conversion circuit (1b), the output value of the latch circuit (la) until just before that is O, so the digital data onl is Regardless of the value, each analog switch (SWO to 5Wn-1 in FIG. 2) in the analog conversion circuit (1b) either changes from off to on or does not operate. Therefore, the analog switch ( Even if things that should change from OFF to ON during SWO~5Wn-1) do not turn on at the same time due to a mismatch in operating time, the transient change in the analog quantity will always follow the increasing direction and the predetermined analog quantity will change. , and no decreasing action occurs.

Next, the second operation, the new value of the digital data. The operation in which an analog signal proportional to 1 is output will be explained. In the analog signal S1 after the first operation is completed, the digital data Dn+ is the digital data D. Since it is larger than the mouth, it is larger than the analog signal S2 of the second D/A converter (2). Therefore, the high priority circuit (3)
Digital data D. An analog quantity proportional to l is selectively output, and analog output 5out is digital data D. It changes from a value proportional to 0 to a value proportional to digital data Dn+.

Next, the third operation, that is, the second D/A humbater (
The operation of resetting the latch circuit (2a) in 2) will be explained. Immediately after the completion of the second operation, the delay circuit (4b
) outputs a signal R with a predetermined time delay from the timing signal. Since the Q output of the flip-flop (4a) is 1, this signal R is sent to the AND circuit (4f).
A reset signal R2 is applied to the latch circuit (2a) of the second D/A humbverter (2) via the latch circuit (2a). The latch circuit (2a) is reset by this reset signal R2, and its output becomes O. As a result, the analog conversion circuit (2b
) is O.

In the process in which the output S2 of the analog conversion circuit (2b) reaches 0, the digital data D held in the latch circuit (2a). Regardless of the value of 0, each analog switch (SWO to Sl
l'n-1) either changes from on to off or is inactive. Therefore, the analog switch (S
vI] ~ 5vn-+), even if they do not turn off at the same time due to a discrepancy in operating time of the objects that should change from on to off, the transient change in the analog quantity always follows a decreasing direction and O , and no increasing action occurs.

Next, the fourth operation, that is, the first D/A converter (
1) The operation of converting the analog signal S1 to the analog output 5out will be explained. The value of the analog signal S2 after the completion of the third operation is 0, and the relationship S2<St is always established between it and the other analog signals S1, so the high priority circuit (3) The analog signal port of /A funverter (1) is selected and output, and the analog output Sout
becomes. In addition, digital data is on.

In the above operation in which Dn+ and Dn+ are in the relationship Dnl<Dnl, the analog signal St has already appeared as the analog output Sout in the second operation, but Dno>
In the case of a Dnl relationship, the analog signal S1 appears for the first time as an analog output 5out in this fourth operation.

Next, the fifth operation, that is, the latch circuit (la, 2a
) will be explained.

The output signal R of the delay circuit (4b) is given to the flip-flop circuit (4a) as a clock signal.The flip-flop circuit (4a) takes in its own Q output at the falling edge of the output signal R, so the Q output is from 1 to O
In this state, the following sixth to first O operations are performed.

The sixth operation, that is, the operation of causing the second D/A converter (2) to output an analog signal proportional to the new digital data Dn2 will be explained.

Since the Q output of the flip-flop circuit (4a) is O, the timing signal is supplied to the latch circuit (2a) as the latch signal L2 through the AND circuit (4e).The latch signal L2 causes the digital data Dn2 to be transferred to the latch circuit ( 2a) and retained digital data D
The analog quantity proportional to n2 is the analog conversion circuit (2b)
, and becomes an analog signal output S2.

During the sixth operation described above, the digital data D is converted by the analog conversion circuit (2b). In the process where 2 becomes the analog signal S2, the output value of the latch circuit (2a) just before that becomes O due to the third operation, so the analog conversion circuit (2b) Each analog switch (5W (1-
5Wn-1) either changes from off to on or does not operate. Therefore, the analog switch (
Even if things that should change from off to on during SWo~5Wn-1) do not turn on at the same time due to a discrepancy in operating time, the transient change in the analog quantity will always follow the increasing direction and change to the predetermined analog value. The amount is reached and no decreasing action occurs.

Next, the seventh operation, that is, the operation in which an analog signal proportional to the new value Dn2 of digital data is output will be described. The analog signal S2 after the completion of the sixth operation is digital data D. 1 is digital data DI+2
Since it is larger, it is smaller than the analog signal S1 of the first D/A converter (1). Therefore, the high priority circuit (3
) selects and outputs an analog quantity proportional to the digital data Dn1, and the analog output 5out is the digital data D. ■Continue to produce a value proportional to.

Next, the eighth operation, that is, the first D/A converter (
The operation of resetting the latch circuit (1a) in 1) will be explained. Immediately after completing the seventh operation, the delay circuit (4b
) outputs a signal R with a predetermined time delay from the timing signal. Since the Q output of the flip-flop circuit (4a) is 1, this signal R is generated by the AND circuit (4a).
d), a reset signal R1 is applied to the latch circuit (la) of the first D/A converter (1). The latch circuit (la) is reset by this reset signal R1, and its output becomes O. As a result, the analog conversion circuit (
1b), the value of the output Sl becomes O.

During the process in which the output Sl reaches 0 in the analog conversion circuit (lb), the digital data D held in the latch circuit (la). Regardless of the value of 1, each analog switch (SWO to Sl
l'n-1> either changes from on to off or does not operate. Therefore, the analog switch (S
Even if things that should change from on to off during W[l~5vn-+) do not turn off at the same time due to a mismatch in operating time, the transient change in analog quantity always follows a decreasing direction. It reaches O and does not cause any increasing action.

Next, the ninth operation, that is, the second D/A humbater (
The operation of converting the analog signal S2 into the analog output 5out in 2) will be explained. The value of the analog signal S1 after the completion of the eighth operation is O, and the relationship sl<s2 is always established between the analog signal S1 and the other analog signal S2, so the high priority circuit (3) /A converter (1) analog signal Sl, that is, digital data H. The analog signal corresponding to 2 is selected and output, and the analog output 5ou
It becomes t.

Next, the tenth operation, that is, the latch circuit (la, 2
The operation of switching the operation mode in a) will be explained.

The output signal R of the delay circuit (4b) is given to the flip-flop circuit (4a) as a clock signal. The flip-flop circuit (4a) captures its own Q output at the falling edge of the output signal R, so the Q output varies from O to 1.
and enters a state in which the first to fifth operations are performed.

When the tenth operation is completed, the first operation is in a standby state, and from then on, the first to first O operations are performed according to the timing signal.
Repeat the action.

[Effects of the Invention] As described above, according to the present invention, a pair of D/A converters are connected in parallel to each other, and digital data is transferred to each D/A converter section.
A control circuit is provided to control the latch circuits of the /A converter section to hold the output alternately, and the latch circuit that is not held to reset the higher one of the analog outputs of the pair of D/A converter sections. A high-level priority circuit that always outputs data is provided, so when updating digital data, the D/A
Changes in the switching state in the analog conversion circuit of the converter section occur only in one direction, either from off to on or from on to off. Therefore, there is an effect that an incorrect signal will not be output in a transient state during switching. Moreover, this effect can be obtained without any loss in the high speed of digital/analog conversion processing, so it has a great practical effect.

[Brief explanation of drawings]

FIG. 1 is a block diagram showing an embodiment of the present invention, FIG. 2 is an internal circuit diagram of the analog conversion circuit (1b> or (2b) in FIG. 1, and FIG. 3 is a block diagram showing the digital data in FIG. 1. A time chart showing the signals of each part when changing Dn in the order of DnO, Dnl, Dn2, and Dn3. Figure 4 is a circuit diagram showing a conventional D/A converter. Figure 5 is centered on point Pk in Figure 4. Analog conversion circuit (11)
FIG. In the figure, (1) is the first D/A converter, (2)
is the second D/A converter, (la, 2a) crawl/nochi circuit, (lb, 2b) is the analog conversion circuit, (3)
is a high priority circuit, and (4) is a control circuit. Note that the same reference numerals in each figure indicate the same or corresponding parts.

Claims (1)

[Claims] (1) A first digital circuit that is connected in parallel to each other and includes a latch circuit that receives and holds digital data, and an analog conversion circuit that outputs an analog signal proportional to the digital data output from this latch circuit. an analog converter section, a second digital-to-analog converter section, an output from the first digital-to-analog converter section and an output from the second digital-to-analog converter section, and outputs a higher-order analog signal; and the digital data is alternately held in the latch circuit of the first digital-analog converter section and the latch circuit of the second digital-analog converter section, and the latch circuit that is not held is held by the latch circuit that is held. A digital-to-analog converter equipped with a control circuit that resets after a predetermined period of time has elapsed from operation.