JPS59181769A - Interface circuit - Google Patents

Abstract

PURPOSE:To execute easily an input of an image data of a graphic, etc. to an information processing device from a facsimile device by providing a circuit for outputting a continuation permitting/inhibiting signal of a scan operation, and a circuit for stopping a scan operation of the facsimile device by on/off of its signal. CONSTITUTION:A Japanese language word processor is set to a connectable state (ready state) to a facsimile (FAX 1), an original is set to the FAX, and a read mechanism of the FAX is operated. When a scan is started, a clock signal TIM6 and an image data signal SPIX7 are outputted from the FAX in a fixed range, synchronizing with each other. Said TIM6 and SPIX7 are sent to a serial/ parallel converting circuit SP21, and inputted as an image data. An FAX control part 31 sends a status information 38 to a CPU23 when a data is collected to a byte unit. The CPU23 transfers a data in a BUF33 to a memory in accordance with the status information.

Description

DETAILED DESCRIPTION OF THE INVENTION [Technical Field of the Invention] The present invention relates to an in-97142 circuit for importing image data from a facsimile device into an information processing device.

[Technical Background of the Invention and Problems There are many demands for processing image data such as figures on an information processing device. There are many dedicated image processing devices that can process image data input from optical equipment or image data created on a processing device (although some have been developed).
There are few simple methods for inputting images drawn on paper into general information processing devices.

For example, there is a demand for document creation devices to handle graphical images such as graphs in the same way as created documents.

[Object of the Invention] In view of the above-mentioned problems, the present invention uses a facsimile machine as a means for inputting image data, and an object of the present invention is to provide an interface circuit for connecting the facsimile machine and an information processing device. .

[Summary of the Invention] The interface circuit of the present invention includes a serial-parallel converting circuit that converts serial image data obtained from a facsimile machine into parallel data, and a parallel converting circuit that transfers the converted parallel data to a record +11 device of an information processing device. - equipped with a circuit. In a facsimile machine, a scan start signal is generated to start scanning paper, but it is necessary to control the acquisition of serial image data depending on the transfer status and data processing status of the transfer circuit. The face circuit includes a circuit for outputting a signal for allowing/inhibiting the continuation of the scanning operation, and a circuit for stopping the scanning operation of the facsimile machine by the 0N10FF of this signal.

[Embodiment 1 of the Invention] The present invention will be described in detail below using an embodiment in which a Japanese word processor is used as an information processing device.

FIG. 1 is a connection ink face signal diagram between a facsimile machine and a Japanese word processor.

1 is) 1 Kushimiri device ('△X), 2 is Japanese word processor <JWP), 7, 11 is U:AXl
12 is a terminal control unit (S-CPtJ). In F A X 1, the binary image data output from PMCll is 5-
Processed by the CPU 12, the transmission control unit (not shown) (M
-CPU). In the connection with JWP 2 in this embodiment, an interface intervenes between PMCII and S-CPU 12 and receives image data 16. 3 is a scan start signal (88>), which is generated every time one line scan is started. SS3 is generated every 4.999 m5 cycles. 4 is a step ready signal (SR),
On the JWP2 side, the copy star h signal (O3>5 is detected and generated, and when the JWP2 status is ready and off, the OF
This is a signal that is subjected to F. 6 is an image data readout tally signal (Q<1''I M ) in units of 1 pixel, which is generated at a regular cycle of 1.33 μs in this embodiment.

, 7 is an image data signal (SP[X). 8 is a document size Do signal, and 9 is a D1 signal as well. (Dl
, DO) = (0, O) is A, (Dl, Do) = (0
, 1) is defined as B4 size, and (Dl, DO)=(1, O) is defined as A3 size specification. Reference numeral 10 denotes a paper detection signal (S''), which is turned on at the leading edge of the document and turned off at the trailing edge.

FIG. 2 is a block diagram of the Japanese word processor. 21 is a 1-parallel converter (SP), and 5 in serial format.
PIX7 inputs. At 5P21, serial image data is converted to parallel data. 22 is a bus control unit (Bus INTF); 23 is a voice control unit (CPU);
). 24 is a storage device (MEM), and 25 is a kanji pattern memory (KPM) in which kanji pattern data is stored.
It is. 26 is a printer control unit (PRTO), and 27 is a printer device (PRT). 28 is the FDO control unit (
FDC), 29 is a floppy disk device (FDD).

30 is a data bus line.

FIG. 3 is a detailed block diagram of the interface circuit between FAX1 and JWP2. Signals and circuits common to FIG. 1 and FIG. 2 are given the same reference numerals. 5P2
1 is the byte counter 211, shift register (S, RE
It consists of three G>212 and a register (REQ) 213. The REG 213 has a FAX control section 31
A clock signal (CK
B) 32 enters. t< The byte data held in the EQ 213 is temporarily held in the buffer (BUF) 33. The data stored in the BUF33 is transferred to the ME by the CPU23 via the L-Bus34 by I10B1]tuk transfer.
Written to M24. 35 is a 1-BUS:] control unit that controls the use of L-8LJS 34, and uses deg 36.
The base number is J') and is assigned to AIH. FAX
Control section 31, L-Bus control 1 call section, 3
j) is input with the status information 37 of [:AXl. FAX
The control section 31 sends data status information 38 to the CPU 23 via the register 39. 40
is a 1-slice counter that counts TIM6 and records data input for 1 slice, and 41 is a 1-slice counter that counts TIM6 and 24
This is a 24-slice counter that monitors the input for each slice. 42 is a flip-flop (F') in which the output signal of the 27'l slice counter is set. The output signal of the 1-slice counter 40, F[42 is input to the FAX control unit 31 as information indicating the status of input data. do.

The timing chart ↑・- is shown in Figure 4 (a) and (b) below.
1 to 2 are shown, and the operation of the embodiment can be explained. Figure 4<a)
Figure 4(b) shows the overall operation of the interface circuit.
indicates the operation when scanning one line.

JWP2 can be connected to FAXl OL state (ready state)
5F10 becomes active when a document is set on the FAX1. Next, when the Aberator activates copy start using the FAxl switch, C85 is turned ON. When the PMCll detects the ON of C85, the PMCll
generates the 883 signal and activates the FAX1 reading mechanism. This C85 is also input to the FAX control unit 31 via the signal line 37. At this time, unless JWP2 is in the ready state, SR4 will not become active, so SS3 will enter the s-cpu i8.
is a dynamic f[shi. When SR4 becomes active, SS3 is sent to the 5-CPU 1.2, and the FAX1 scan operation is started. The SS3 cycle corresponds to one line of scanning. When the scan starts, 11
M6 and 5PIX7 are outputted from FA and X1 at a predetermined period while being synchronized with each other. This T 1M
6 and 5PIX7 are sent to 5P21 and taken in as image data. FAX:J-N1~The roll unit 31 sends the status information 38 to the CPU 23 when the data is arranged in byte units. The status information includes block completion status in units of 24 lines, paper completion status, paper reuse information, copy start status, and the like. The CPU 23 transfers the 13U f-33 medium data to the MEM 24 according to this status information.

On the other hand, in order to connect FAX1 and JWP2, it is necessary to control the stopping and restarting of transfer on a line-by-line basis due to restrictions on transfer fees, time, and processing capacity.

The SR4 is used for this control. By turning off SR4 in the invalid area of the line, as shown at the timing @A in FIG. 4(a), it is possible to temporarily stop data input from the FAX1.

P RT27 image data held in MEM24
If you want to output more, the operation will be as follows. For example, if the PRT27 prints 24 dots x 24 dots per character, one line (25
6 bytes) x 24 information is stored in MEM24 as one block.
The data is read from the KPM23 and written to the KPM23. KPM2
The data written to 3 is sent to PRT via PRTC26.
27.

Also, when saving image data stored in the MEM24, this data is transferred to the FDD29 via the FDC2&.
will be written to.

[Advantageous Effects of the Invention 1] As explained above, according to the present invention, image data such as graphics can be easily input to an information processing device from a facsimile machine.

[Brief explanation of the drawing]

FIG. 1 is a signal diagram of a connection intercois circuit between the Fun7 Kushimiri equipment direct and the Japan TN word processor. FIG. 2 is a block diagram of the Japan II+I word blog in the embodiment. Fig. 3 is a block diagram of the interface circuit between the Nofu-Kushimiri device and the Japanese word processor, and Fig. 4 is an operational timing chart of the embodiment.・・・・・・Japanese word processor 3・・・・・・
Scanning star 1 to signal 4...Step ready signal 21...1 Parallel conversion circuit 23...CPU, 24...Storage device θ
25... Kanji pattern memory 31... F A, X control section 3...
... L-Bus Control 1~Roll Department (7317) Agent Patent Attorney Norichika Kasuke (and 1 other person) Bo 3 Ward No. 4 Figure (α) SS3-]] T Ding-Ding--------- -Ding-τ≠ (S) SS3 Heat Th lower 1+1
116J1 Torou----------=----------
11 mouths m5PIX7 ------------------------
--ko=D】TX=fi7cho'-糎BI

Claims (1)

[Claims] Provided between a facsimile device that scans paper to generate serial image data in response to input of a scan start signal and an information processing device that captures this serial image data into a storage device, the device converts the serial image data into parallel data. a parallel-to-parallel conversion circuit, a circuit for transferring the parallel data obtained by the parallel-to-parallel conversion circuit to the storage device, and a circuit for outputting a scan operation continuation permission/inhibition signal according to the transfer state of the transfer circuit. , this permission/inhibition signal causes the scanning start signal to be set to 0N10.
FF and a circuit for stopping the scan operation of the facsimile lff1.