JPS59183449A - Memory space extending system of microcomputer system - Google Patents

Memory space extending system of microcomputer system

Info

Publication number
JPS59183449A
JPS59183449A JP58055057A JP5505783A JPS59183449A JP S59183449 A JPS59183449 A JP S59183449A JP 58055057 A JP58055057 A JP 58055057A JP 5505783 A JP5505783 A JP 5505783A JP S59183449 A JPS59183449 A JP S59183449A
Authority
JP
Japan
Prior art keywords
memory
instruction
memories
sets
microcomputer
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP58055057A
Other languages
Japanese (ja)
Inventor
Takashi Kojima
隆 小島
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Hitachi Ltd
Original Assignee
Hitachi Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Hitachi Ltd filed Critical Hitachi Ltd
Priority to JP58055057A priority Critical patent/JPS59183449A/en
Publication of JPS59183449A publication Critical patent/JPS59183449A/en
Pending legal-status Critical Current

Links

Classifications

    • GPHYSICS
    • G06COMPUTING OR CALCULATING; COUNTING
    • G06FELECTRIC DIGITAL DATA PROCESSING
    • G06F13/00Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units

Landscapes

  • Engineering & Computer Science (AREA)
  • Theoretical Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • General Engineering & Computer Science (AREA)
  • General Physics & Mathematics (AREA)
  • Microcomputers (AREA)

Abstract

PURPOSE:To extend easily a memory space by using an existing microcomputer with addition of a circuit outside of a ready-made microcomputer. CONSTITUTION:When a memory space is extended, the program memory space is allotted to 16 sets of memories (00000) with the RAM space alloted to 16 sets of memories (10000) and (20000) respectively. The instruction which gives accesses to RAM space of each 16 sets of memories (10000) and (20000) is decided among MOVE, LOAD and STORE instructions of an existing microcomputer i- 8085. This decided instruction is registered to an instruction word analysis switch indicating part 205. While an upper address (1) 16 of the 16 sets of memories (10000) is stored to a memory upper address storage part 206 with each pio instruction when an access is given to the 16 sets of memories (10000) for program production. While an address (2) 16 is stored to the part 206 with the pio instruction when an access is given to the 16 sets of memories (20000). Then the memory access is carried out by programming.

Description

【発明の詳細な説明】 〔発明の対象〕 本発明はマイクロコンピユータラ用いタシステムに係り
、特に既製のマイクロコンピュータを用い外部に回路を
付加することで、メモリ空間を容易に拡張するのに好適
な方式に関する。
[Detailed Description of the Invention] [Subject of the Invention] The present invention relates to a microcomputer system, and particularly to a microcomputer system suitable for easily expanding memory space by using an off-the-shelf microcomputer and adding an external circuit. Regarding the method.

〔発明の背景〕[Background of the invention]

従来のメモリ拡張力法には、第1図に示す様にメモリを
基本メモリ部1o1と拡張メモリ部102〜104に分
け、必要に応じて拡張メモリ部102〜104のうち1
つを選択して、メモリ柴間の拡張を図るものがあるが、
プログラムエリアの拡張には不向きである。拡張メモリ
の空間分だけ基本メモリ空間が狭(なる等の欠点があっ
た。
In the conventional memory expansion method, the memory is divided into a basic memory section 1o1 and extended memory sections 102 to 104, as shown in FIG.
There are some that aim to expand the memory space by selecting one.
It is not suitable for expanding the program area. There were drawbacks such as the basic memory space becoming narrower due to the expanded memory space.

〔発明の目的〕[Purpose of the invention]

本発明の目的は一既製マイクロコンピュータを用い、外
部に回路を付加することにより、容易に広いメモリ空間
を提供することにある。
An object of the present invention is to easily provide a wide memory space by using a ready-made microcomputer and adding an external circuit.

〔発明の棚、要〕[Shelf of inventions, essential]

マイクロコンピュータは、常時、メモリからの読出しあ
るいはメモリへの書込み(メモリアクセス)を繰返して
いるが、どのアドレスをアクセスするかは、命令語の内
容により一義的に決定される。しかし、本来マイクロコ
ンビニーりが備えているメモリ空間を超えてメモリアク
セスさせようとすれば、命令語によりアドレスが一義的
には定まらなくなり、マイクロコンビ九−夕の外部から
、上位アドレスを付加してやらねばならない。社の上位
アドレス付加に関し、命令語を解析してその内容に応じ
た上位アドレス付加を行えば、メモリ空間を拡張できる
だけでなく、スステム拡張性を向上させることができる
A microcomputer constantly repeats reading from or writing to memory (memory access), and which address to access is uniquely determined by the contents of the instruction word. However, if you try to access memory beyond the memory space originally provided by the Microcombi, the address will no longer be uniquely determined by the instruction word, and you will have to add an upper address from outside the Microcombi. Must be. Regarding the addition of higher-order addresses, if the instruction word is analyzed and the upper-order addresses are added according to its contents, it is possible not only to expand the memory space but also to improve system expandability.

〔発明の実施例〕[Embodiments of the invention]

以下、本発明の一実施例を第2図に説明する。 An embodiment of the present invention will be described below with reference to FIG.

但し、説明をより具体的なものとするために、マイクロ
コンピュータはi −8085又は相当品およびその命
令語により説明する。
However, in order to make the explanation more concrete, the microcomputer will be explained using an i-8085 or an equivalent product and its instruction words.

本メモリ拡張を有するマイクロコンピュータシステムは
、マイクロコンピュータ201およびアドレス(ooo
oo)、6〜(o F F F FCl2てわたりアク
セス可能なメモリ202の他に、アドレス(10000
)+a〜(IFFFF)+eアクセス可能なメモリ20
3から、(n0000)、6台アクセス可能なメモリ2
04までの拡張メモリ、゛さらにマイクロコンピュータ
の命令語を解析してメモリの上位アドレス切替指示を出
ス部分205、このメモリ上位アドレスをマイクロコン
ピュータからのp1o命令に従って記憶−[る部分20
6より成る。
A microcomputer system having this memory expansion includes a microcomputer 201 and an address (ooo
oo), 6~(o F F F FCl2 In addition to the globally accessible memory 202, the address (10000
)+a~(IFFFF)+eAccessible memory 20
3 to (n0000), memory 2 that can be accessed by 6 devices
Expansion memory up to 04, part 205 that further analyzes the command word of the microcomputer and issues an instruction to switch the upper address of the memory, and a part 205 that stores this upper address of the memory according to the p1o command from the microcomputer.
Consists of 6.

今、メモリ空間を拡張するに肖たり、プログラムメモリ
空間を(00000)+e代メモリ、RAM空間を(1
0000)re代および(20000)+e代メモリに
割付けるとする。次に、i−8085の持つMOVE、
LOAD−5TORE命令のうち、RAM空間(100
00)la台および(20000) la台をアクセス
する時に使用する命令を決め、その命令語を、命令語1
ψT析切替指示部に登録する。今、仮にニモニックLl
)AXD−5TAXBにより、アクセスすると決め、各
々の命令語(l A ) re、(02)+6を登録す
る。一方プログラム作成に当たり、(1oooo)、a
代をアクセスする場合には、pio  命令により(1
0000)Ha代メモリ上位アドレスである(’)la
を、(20000)、。
Now, when expanding the memory space, the program memory space is (00000) + e memory, and the RAM space is (1).
0000) re memory and (20000)+e memory. Next, MOVE of i-8085,
RAM space (100
Decide the command to be used when accessing the 00) la machine and the (20000) la machine, and change the command word to instruction word 1.
Register in the ψT analysis switching instruction section. Now, if Mnemonic Ll
)AXD-5TAXB, it is decided to access, and each instruction word (l A ) re, (02)+6 is registered. On the other hand, when creating a program, (1oooo), a
When accessing the data, use the pio command (1
0000)Ha is the upper memory address (')la
(20000).

代をアクセスする場合には、(2)laを、各hpiO
命令によりメモリ上位アドレス記憶部に記憶させてから
、メモリアクセスする様プログラミングする。アドレス
(12545)、、からデータをLOADfるには、ま
ずpio命令でLDAXD用のメモリ上位アドレス(’
)+sを記憶部に書込み、次に(DE)レジスタに(2
345)、6を格納してからLDAXDを発行する。L
DAXDの命令語である(IA)reは、プログラムメ
モリ空間(00000)、e代から読出されるが、命令
語解析切替指示部は、この命令語が、あらかじめ登録さ
れている命令語であるかどうかチェックし、登録済の(
IA)+6であることから、メモリ上位アドレスをLD
AXD用に記憶された(1)16に切替る。l−808
5は(DE)レジスタに格納された(2345)、eを
アクセスすべく、アドレスバスに(2345) 、6を
送出するが、メモリ上位アドレスが(’)reであるた
め、アドレス(12345)、、がアクセスされ、ここ
に格納されているデータが読出される。5TAXBの場
合も同様に、こんどは5TAXB用の上位アドレスを、
仮に(2)reとすれば、これをp1o命令により、メ
モリ上位アドレス記憶部に記憶させる。
(2) la for each hpiO
Programming is performed so that the memory is accessed after being stored in the memory upper address storage section by a command. To load data from address (12545), , first use the pio instruction to access the upper memory address for LDAXD ('
)+s to the memory, then write (2) to the (DE) register.
345), 6 is stored and then LDAXD is issued. L
The DAXD instruction word (IA)re is read from the program memory space (00000), e-range, but the instruction word analysis switching instruction unit checks whether this instruction word is a pre-registered instruction word. Please check and register (
IA)+6, so the upper memory address is set to LD.
Switch to (1) 16 stored for AXD. l-808
5 sends 6 to the address bus (2345) in order to access e stored in the (DE) register (2345), but since the upper memory address is (')re, the address (12345), , is accessed and the data stored there is read. Similarly, in the case of 5TAXB, the upper address for 5TAXB is
If (2)re is set, this is stored in the memory upper address storage section by the p1o instruction.

次に(+3 C)レジスタに(6789) 、、を格納
し5TAXB命令を発行すると、アドレス(267a 
q ) laにデータが書き込まれる。
Next, store (6789), , in the (+3C) register and issue the 5TAXB command, the address (267a
q) Data is written to la.

以上をまとめて、プログラムに沿った説明図を第5〜5
図に示す。$3図は、通常メモリ拡張を行わ7fい場合
の、読出しを示す。また、第4.5図に示した様にメモ
リ読出しく LDAXl))用の上位アドレス、メモリ
書込み(STAX iJ )用の上位アドレスの2つを
サボー1−fれは、最大64にバイトのメモリーメモリ
の転送もriJ能となる。これらのメモリ空間の拡張は
、命令語解析切替指示部の変更により、上記データに関
−[るメモリ空間の拡張以外に、スタックツーリア、プ
ログラムエリア1.さらにpio命令にも応用し、拡張
することができろ。
Summarizing the above, we will create explanatory diagrams according to the program in sections 5 to 5.
As shown in the figure. Figure $3 shows reading when normal memory expansion is performed and 7f is left. In addition, as shown in Figure 4.5, the upper address for memory read (LDAXl)) and the upper address for memory write (STAX iJ) are set to 1-f. Memory transfer also becomes an RIJ function. In addition to expanding the memory space related to the data mentioned above, the expansion of these memory spaces is due to changes in the instruction word analysis switching instruction section. Furthermore, it can be extended by applying it to the pio instruction.

〔発明の効果〕〔Effect of the invention〕

以上説明した本発明によれば、マイクロコンピュータの
メモIJ 2間を理論上無限に拡張でき2)ので、マイ
クロコンピュータ応用のシステム拡張性を飛躍的に向上
させることができる。
According to the present invention described above, the memo IJ 2 of a microcomputer can theoretically be expanded infinitely (2), so that the system expandability of microcomputer applications can be dramatically improved.

【図面の簡単な説明】[Brief explanation of drawings]

第1図は従来公知のコンピュータシステムの概略図、第
2図は本発明の1実施例を示すンステノ・概略図、第3
〜5図は、第2図に示したシステムσ)プログラム説明
図である。 205:命令語解析およびメモリ上位アドレス切替指示
部、206:メモリ上位アドレス記憶部。 芋  1  図 届
FIG. 1 is a schematic diagram of a conventionally known computer system, FIG. 2 is a schematic diagram of an embodiment of the present invention, and FIG.
5 are explanatory diagrams of the system σ) program shown in FIG. 2. 205: Instruction word analysis and memory upper address switching instruction unit; 206: Memory upper address storage unit. Potato 1 illustration

Claims (1)

【特許請求の範囲】[Claims] マイクロコンピュータによるシステムにおいて、通常の
システム構成の外に、マイクロコンピュータの命令語解
析、およびメモリ上位アドレス切替部、メモリ上位アド
レス記憶部を設けたことを特徴とするマイクロコンピュ
ータシステムのメモリ空間拡張方式。
A memory space expansion method for a microcomputer system, characterized in that the microcomputer system includes a microcomputer instruction word analysis, a memory upper address switching section, and a memory upper address storage section in addition to the normal system configuration.
JP58055057A 1983-04-01 1983-04-01 Memory space extending system of microcomputer system Pending JPS59183449A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP58055057A JPS59183449A (en) 1983-04-01 1983-04-01 Memory space extending system of microcomputer system

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP58055057A JPS59183449A (en) 1983-04-01 1983-04-01 Memory space extending system of microcomputer system

Publications (1)

Publication Number Publication Date
JPS59183449A true JPS59183449A (en) 1984-10-18

Family

ID=12988045

Family Applications (1)

Application Number Title Priority Date Filing Date
JP58055057A Pending JPS59183449A (en) 1983-04-01 1983-04-01 Memory space extending system of microcomputer system

Country Status (1)

Country Link
JP (1) JPS59183449A (en)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH01173143A (en) * 1987-12-26 1989-07-07 Toshiba Corp Memory management unit

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH01173143A (en) * 1987-12-26 1989-07-07 Toshiba Corp Memory management unit

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