JPS5918655A - Manufacture of semiconductor device - Google Patents

Abstract

PURPOSE:To obtain insulation isolation films whose height is larger than the width by a method wherein an insulation film is provided selectively on an Si substrate, an epitaxial layer and the first flattening film are superposed, the second film is superposed by removing the first film above the insulation film and in the neighborhood of the film, and the flat surface is etched at an equal speed. CONSTITUTION:The pattern of the SiO2 12 whose height is larger than the width is formed on the P type Si substrate 11, the P type epitaxial layer 13 is superposed, and positive type resist 14 is spin-coated. The part above the film 12 and the neighborhood thereof are removed by selective exposure. Successively, resist 15 is spin-coated over the entire surface. Reactive ion etching is performed on the perfectly flatted surface, thus choosing a condition that the etching speeds of the epitaxial layer 13 and the resists 14, 15 are approximately equal, and the etching is continued until the SiO2 film 12 is exposed. The burial of the SiO2 film 12 whose height is larger than the width in the Si layer 13 and the element formation at isolated regions by this constitution enalbe to contrive to improve the characteristic of various kind of IC elements.

Description

DETAILED DESCRIPTION OF THE INVENTION [Technical Field of the Invention] The present invention relates to a method for manufacturing a semiconductor device, and particularly to an improvement in an insulating film separation method.

[Technical background of the invention and its problems]

BACKGROUND ART In a semiconductor integrated circuit (IC), circuit elements such as transistors, diodes, and resistors are packed into a single semiconductor pellet, so it is necessary to separate and manufacture these elements in an isolated state. This is called isolation, and the PN junction isolation method, insulation isolation method, etc. are widely used for this isolation. Conventional insulation isolation techniques include a method using a selective oxide film for insulation as shown in FIG. 1, and a method using a buried oxide film for insulation as shown in FIG. Note that in the figure, 1 indicates a silicon substrate, and 2 and 3 indicate oxide films. .

By the way, the conventional method shown in FIG. 1 has the problem of the generation of bird's beaks and bird's heads, and is known to have a limit to high integration. On the other hand, the conventional method shown in Fig. 2 solves problems such as bird's beaks, nozzles, and dots, but it requires the formation of a buried oxide film that is taller than the width required for future fine devices. is difficult.

The insulating isolation film, which is large in width and height, is necessary to reduce leakage current caused by parasitic transistors that use the insulating isolation film as a dirt insulating film, and to solve the problem of chia lag in C-MOS-RAM. It is approved. For this reason, there is a strong demand for a technique that can form an insulating separation film that is taller than its width, but no method for realizing this has been reported yet.

[Purpose of the invention]

SUMMARY OF THE INVENTION An object of the present invention is to manufacture a semiconductor device that can form an insulating separation film with a height greater than its width, and which can contribute to improving the characteristics of various semiconductor integrated circuits. After selectively forming an insulating film according to the desired element isolation region/turn, a semiconductor crystal layer is epitaxially grown on the upper surface thereof, and then a first planarizing film is formed on this semiconductor crystal layer. Then, a portion of the first planarizing film above the insulating film and its vicinity is removed, and then a second planarizing film is formed on these upper surfaces and the surface thereof is planarized, and then the above-mentioned In this method, the entire surface of the insulating film is etched under conditions in which the etching rates of the semiconductor crystal layer and the first and second planarizing films are approximately equal until the upper surface of the insulating film is exposed.

Here, the insulating film may be selectively formed by depositing or growing an oxide film or the like on the semiconductor substrate, and then patterning the oxide film or the like by dry etching or the like. Further, as the first planarization film, a resist film such as a photoresist or an electron beam resist, or an inorganic film can be used. When using a positive photoresist as the first planarizing film, as a selective removal step of the first planarizing film, after exposing the upper part of the insulating film of the resist and its vicinity, the resist is removed. All you have to do is use K to develop the image. The second planarizing film may have an etching rate that is approximately the same as that of the first planarizing film and the semiconductor crystal layer under certain conditions, and is the same as the first planarizing film. A photoresist may also be used.

When the entire surface is etched under the above-mentioned conditions after the formation of the second planarizing film, a structure is obtained in which the semiconductor crystal layer is separated by the insulating film, and the surface thereof becomes a planarized shape. That is, a structure in which an insulating separation film is embedded within a semiconductor crystal layer is realized. The width and height of this insulating film can be arbitrarily determined during the above-described insulating film formation and patterning. Furthermore, even if the height and width of the insulating film are larger than the width, it is possible to realize a structure in which the semiconductor crystal layer is separated by the insulating film and its surface is flattened by the process described above. be. Therefore, it becomes possible to embed an insulating separation film whose height is larger than its width in the semiconductor crystal layer.

〔Effect of the invention〕

According to the present invention, it is possible to form an insulating isolation film that is larger in width and height, and it is also possible to embed this insulating isolation film with a flat surface in a semiconductor crystal layer used for device formation. . Therefore, it has great effects in reducing the leakage current of the parasitic transistors mentioned above and preventing chipping, chipping, and chipping in C-MOS-RAM, and also has tremendous effects such as improving the element characteristics of various semiconductor integrated circuits. be effective.

[Embodiments of the invention]

FIG. 3(,) to (h) are MOs according to an embodiment of the present invention.
FIG. 3 is a cross-sectional view showing the S-RAM manufacturing process. First, the third
As shown in the figure (,), a thickness of 2.0 mm was deposited on a P-type silicon substrate (semiconductor substrate) 11 with a plane orientation (i.o.o.) using thermal oxidation technology.
．． An oxide film (insulating film) 12 having a thickness of 5 [μm] is formed. Next, using well-known exposure and etching techniques, the image shown in Figure 3 (
As shown in b), a pattern of the oxide film 12 having a width of about 1 [μm3 and a larger height is formed. Next, a P-type epitaxial layer (semiconductor crystal layer) 13 is grown on the entire surface as shown in FIG. The flattening film (1) 14 is applied by spin coating. As a result, the surface of the sample is substantially flattened. Next, using a light exposure technique, the upper part of the oxide film 12 and its vicinity of the resist 14 are removed as shown in FIG. 3(d). Subsequently, as shown in FIG. 3(e)K, a photoresist (second flattening film) 15 is spin-coated over the entire surface. As a result, the surface of the sample is almost completely flattened. The reason why the planarization process is performed twice using the resists 14 and 15 is that complete planarization cannot be achieved by only using resist No. 4, especially when the width of the recess is wide.

Next, using a reactive ion etching technique, the entire surface of the semiconductor crystal layer 13 and the resist 14, 15 are etched under conditions where the etching rates are approximately equal. By continuing this entire surface etching until the oxide film 12 is exposed, the oxide film 12 is buried in the semiconductor crystal layer 13 with a height greater than its width and the surface is flat, as shown in FIG. 3(f). A standardized structure was realized.

Using the sample in which the insulating separation film was embedded in this way, the separated six-layer taxial layer 13 was coated with a third layer using a well-known technique.
As shown in Figure (h), N-channel MOS transistors were formed in each case. Furthermore, as a result of forming a desired wiring pattern, etc., it was possible to realize a MOS-■ζ structure with less leakage current due to parasitic transistors. In addition, the third
In the figure, 16 indicates a dirt oxide film, 17 indicates a dirt electrode, and 18 indicates a diffusion region. Further, each of the separated epitaxial layers 13 is selectively doped with N
C-MO that does not cause latch-up by forming transistors (channel and P-channel MOS)
It was possible to realize S-RAM.

Note that the present invention is not limited to the embodiments described above, and can be implemented with various modifications without departing from the gist thereof. For example, as the first and second planarizing films, it is possible to use not only the optical resist) but also an electron beam resist or an inorganic film. Further, the method for forming the oxide film as the insulating film is not limited to thermal oxidation, and may be CVD or the like. Furthermore, MOS-R
Of course, the present invention is applicable not only to AM manufacturing but also to various semiconductor devices.

[Brief explanation of the drawing]

FIGS. 1 and 2 are cross-sectional views for explaining the conventional insulation isolation method, and FIGS. 3 (,) to (h) are cross-sectional views showing the MOS-RAM manufacturing process according to an embodiment of the present invention. It is. 11... Silicon substrate (semiconductor substrate), 12... Oxide film (insulating film), 13... Epitaxial layer (semiconductor crystal layer), 14... Photoresist (first planarization film), 15... Photoresist (second planarization film), 1
6... Dirt oxide film, 17... Dirt electrode, 18.
...Diffusion layer. Applicant's Representative Patent Attorney Takehiko Suzue Figure 1 Figure 3 Figure 3 Figure 1 Figure 3

Claims (2)

[Claims] (1) A step of forming an insulating film on a semiconductor substrate according to a desired element isolation region pattern yK, a step of epitaxially growing a semiconductor crystal layer on the semiconductor substrate and the insulating film, and a step of epitaxially growing a semiconductor crystal layer on the semiconductor crystal layer. forming a planarizing film; removing a portion of the first planarizing film above the insulating film and its vicinity; and then forming a planarizing film on the semiconductor crystal layer and the first planarizing film. Step 2 of forming a planarizing film and planarizing its surface, and then etching the entire surface under conditions in which the etching rates of the semiconductor crystal layer, the first and second planarizing films are approximately equal, and 7. A method for manufacturing a semiconductor device, comprising the step of exposing the upper surface of an insulating film. (2) The step of selectively removing the first planarizing film uses a positive photoresist as the film, exposes the upper part of the insulating film and its vicinity, and then removes the resist. A method for manufacturing a semiconductor device according to claim 1, characterized in that the method comprises developing the semiconductor device.