JPS59200973A - Demand transducer - Google Patents

Abstract

PURPOSE:To make a demand measurement such as of AC current and electric power easy by obtaining an output voltage proportional to a DC input at a time limit characteristic to be optionally selected. CONSTITUTION:A subtractor 1 calculates an output proportional to the difference between an input voltage Ei and an output voltage Eo and inputs the output to a pulse width modulating circuit 2. The modulating circuit 2 outputs a pulse having a duty ratio proportional to the output of the subtractor 1. A counter 4 counts up pulses of an oscillation circuit 3 when the output of the modulating circuit 2 is the H level and counts down the pulses at the L level. The output of the counter 4 is converted into an analog value by a D/A converter 5 and outputted to output terminals 10, 11 through maximum and minimum value holding circuits 8, 9. The time limit characteristic of the output voltage can be easily set up by changing the constants of respective circuits 1-5. If an AC/DC transducer is connected to the input side, a demand measurement such as of AC current and electric power can be easily obtained.

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a demand transducer used for measuring demand of alternating current or electric power.

Generally, when measuring current in a circuit where the load fluctuates rapidly, such as during welding, it is difficult to read the reading with a general-purpose ammeter because the reading changes rapidly. To avoid this, conventionally, instruments with slow response speeds (large time constants), such as thermal instruments using bimetals, have been used.

By the way, instruments using bimetal require high accuracy in order to make the instrument time constant (hereinafter referred to as time limit) uniform, but there are major limitations in the selection and processing of the bimetal material. is recieving. Still, this instrument accepts the secondary voltage ACII of the instrument transformer as an input signal.
Since OV, AC5A current, etc. are often input, so-called remote measurement, where the measurement site and monitoring location are far apart, has a large line loss between the measurement site and the instrument, and is therefore not suitable for such measurement methods. Met. Furthermore, there have been problems such as the inability to supply data to electronic computer-like mechanisms such as data loggers, which have become rapidly popular in recent years.

The present invention has been made in view of the above points, and an object of the present invention is to provide a demand transducer having a uniform time characteristic with a simple circuit configuration. In other words, if the output DC voltage (or current) is measured in proportion to the input DC voltage (or current) using a time characteristic that can be carried arbitrarily, cloak measurements can be easily performed, and remote measurement can also be supported. It becomes possible to supply data to a data logger, etc.

Hereinafter, a demand transducer according to the present invention will be explained with reference to the drawings.

First, as shown in Figure 1, the horizontal axis is time t, and the vertical axis is output E.
In the graph representing o, the output E when time 1=00
Starting from o=0, 1=1. When EomEOI
, 1=12, then EO=EO2,...Consider the trajectory. As shown in Fig. 1, this trajectory shows that if the time t becomes sufficiently large, the output Eo approaches the convergence value Ei as much as possible, and the time t2 r t3...
For tl= t2- t1= t3- t2=
t, -t3-...:=:Jin (where n: positive integer, τ: constant), the locus of this curve can be expressed by the following equation (1).

0°==9i.

E(, m=E(, m-1+ (E i E(, m −
1) 'Eom "" Eon-++ " (E i
E6 n -1)' (tap, m is a positive integer and E(,
(m and E6m indicate the outputs of the m-th and (m-1) buds, respectively) When expressed only by the right side kJDi and n of the equation (1), the equation (2) is obtained.

The right sides of Eom and Eon in equation (2) are opened.

-! -(++(t-") 10-+(1-L)n')-n
n
n(1-(i--!-))((1+(1--!-)+・
...+n n(1--
! -)n')-1-(1-!-)nn
n,',E6m=(1-(
1--! −)m)Ei −−(3)Eoh= (1−
(1-1!-)n)E 1--(4)n The demand transducer described below has a time-output characteristic as shown by the curve in FIG. Since the output E when the input Ei is continuously applied to the user for a time t is the τ value when m='n in the above equation (3), it is expressed by the following equation.

Here, in Fig. 1 and equation (1), if the number of divisions n in the interval τ is made sufficiently large, the above equation (6) is
1828). For example, when n=10', 2.71842, when n=10', 2.71828
It is. Therefore, equation (6) can be easily modified like Shintsu's CR integration circuit as shown in equation (7) below.
That is, when a certain interval τ is divided into n parts sufficiently finely as shown in FIG. 1 and equation (1), the (m-1)th and mth outputs Eom -1 and E. The relationship between m is E(
, m=E6m-1+1(E i -Eom-t), and by configuring the electronic circuit as expressed by Eq. Furthermore, it is possible to supply data to a data logger, etc., making it extremely effective as a demand transducer.

The configuration of the demand transducer '5L according to the present invention will be explained below.

FIG. 2 shows an example of a demand transducer according to the present invention. In the same figure, (1) is a subtraction circuit, and the difference between the input voltage Ei and the output voltage E (Ei - Eo)
This is a circuit that obtains an output proportional to . (2) is a pulse width modulation (hereinafter abbreviated as PWM) circuit, and a subtraction circuit (1
) is a circuit that obtains a pulse output with a duty ratio proportional to the output (Ei-Eo), and if the period where the output is at logic level ``H'' is T1, and the period where the output is at logic level ''L'' is T2, then
Assume that the following equation (8) is summed.

T, -T, -z-Kt (Ei Eo) ・-・(8) (Kt
; constant) (3) is an oscillation circuit that outputs a pulse with a sufficiently shorter period (higher frequency f) than the period (T1 + T2) of the PWM circuit (2). (4) is a counter that counts the pulses of the oscillation circuit (3), and its counting direction changes depending on the output state of the PWM circuit (2), so that the output of the PWM circuit (2) is 'H#, that is, T ,
In the section, count up, and when IL', that is, T
The second section is designed to count down.

(5) is a digital-to-analog converter (hereinafter referred to as D/
It is abbreviated as A converter. ) to convert the digital output of the counter (4) into an analog voltage. (6
) is an input terminal, and (7) is an output terminal.

t8) and (9) are a maximum value hold circuit and a minimum value hold circuit, respectively, and (101 and (ill) are maximum value and minimum value output terminals, respectively.

Next, the maximum value and minimum value hold circuit (8)
, The operation of the circuit excluding (9) will be explained with reference to FIG.

The counter (4) counts up the pulses of the oscillation circuit (3) when the output of the PWM circuit (2) is 'H', that is, in the T1 period ((B), (C)), and the output becomes IL'. , that is, in the T2 interval. Therefore, the output Q of the counter (4) when the frequency of the output pulse of the oscillation circuit (3) is f ((5) in the figure) and the pulse of frequency f is counted up by the time t. Qo
= K2f t , the period of the oscillation circuit (3) is 1/
Since f is sufficiently small compared to the period (Tl + T2) of the PWM circuit (2), the output of the counter (4) when the input Ei is continuously applied to the input terminal (6) for a time t is as follows (9) Let them wear it at the ceremony.

Q,=2ft 1-T2=2f”TI+T2・−KIKzf (Ei −Eo) t −−(9)
(Substitute equation (8) '-') As shown in equation (9), the output Qo of the counter (4) is proportional to the difference between the input Ei and the output E of the D/A converter (5).

Therefore, when input Ei is applied to input terminal (6),
As shown in Fig. 1 and equation (1), the interval τ is divided into n parts sufficiently finely, and the output of the counter (4) at the (m-1)th point is Qom ts The output of the D/A converter (5) is E
om-1, the output Qom of the counter (4) and the output E(, m
are as follows.

Qom=Qom-10KIK2f(Ei-E(1m-
t)・-(10) Output EO of D/A converter (5)
The relationship between the output Qo of the counter (4) and the output Qo of the counter (4) is expressed as EomKs Q
o (K3; constant), Egm = 3Qgm, = Egm 1 + KIK2 = 3f r-! −(Ei −
E, 1m-1)...(111(',' Eom-1=
3Q6m-1) In formula (11), KI K2 K
3 If f = ', the equation (11) becomes τ the same as the equation (1) above, and its time-output characteristic is the first
It will look like the figure.

In the circuit of Fig. 2, the subtraction circuit (11), the PWM circuit (
2), the oscillator circuit (3), the counter (4), the D/A converter (5), etc. can all be realized relatively easily using well-known electronic circuits, so we will not discuss the specific circuits here. Omitted. Each of the above circuits (1) to (5) can easily be
The constants Kl, K2f, of each circuit (1) to (5) that determine the time limit τ described above
K3 etc. can be easily and precisely set by simply changing the resistance values used in each circuit (1) to (5). In the above explanation, only the rising characteristic corresponding to the charging curve in the CR4% circuit as shown in FIG.
, i-E.

)-〇, Tl>T2 when (Ei-Eo)>0, and TI<T2 when (Ei-Eo)<0, similarly, (Ei- Eo)
<0 corresponds to a discharge curve, exhibiting a falling characteristic with the same time constant τ.

Next, a maximum value and minimum value hold circuit (8).

The structure and function of (9) will be explained with reference to FIG.

In the figure, (81) is a digital comparator, and (82j) is a latch circuit, and the output Qo of the counter (4) is applied to one input terminal INI of the digital comparator system and the input terminal IN of the latch circuit (82j). C,
The other input terminal IN of the digital comparator (81)
2 is applied with the output QM of the latch circuit (@). The digital comparator (81) u Qo > Q
A trigger pulse is output from the output terminal OUT only when M is selected.The trigger pulse is input to the terminal CP of the latch circuit (82), the input QO of the input terminal IN is latched, and the output terminal OUT, that is, the output terminal Qo is output to (10). The latch circuit (82) does not change the state of its output terminal OUT unless a trigger pulse is applied to the terminal CP.
The maximum value of the outputs of the counter (4) is held as the output of the counter (4). In addition, in the circuit of FIG. 4, the digital comparator (81) is connected to its output terminal O only when Qo<QM.
If the trigger pulse is output from the UT, the circuit can be configured as a minimum value hold circuit (9).

FIG. 5 shows a modification of the maximum value hold circuit (8). In the figure, (83) is an analog converter, (84) is a latch circuit, and (85) is a D/A converter. Analog comparator (83) Iri
D/A Coy Output Eo and D/A of node (5)
It determines the magnitude of the output EM of the converter (85), and outputs a trigger pulse only when EO>EM. The latch circuit (84) latches the output of the counter (4) with the output trigger pulse of the analog comparator (83), and when there is no trigger pulse, the output does not change. The D/A converter (85) converts the digital output of the latch circuit (84) into an analog value.

In this configuration, the output of the latch circuit (84) is
/A converter (5) and (85) output EO and EM, each time EO>EM, counter (4)
) output is latched. Therefore, the latch circuit (8
The maximum value of the outputs of the counter (4) is held as the output of the counter (4). Furthermore, in this circuit, if the analog comparator (83) is configured to output a trigger pulse only when EO<EM, the circuit can be configured as a minimum value hold circuit (9).

As described above, the demand transducer according to the present invention does not require special parts or circuits, and has a relatively low
81 A simple circuit can provide an output with uniform and arbitrarily selectable time characteristics, and the output can be an analog voltage or the output of a counter can be taken out and used as a digital value. In addition, since it is possible to hold the maximum or minimum output value, it is extremely effective for measuring demand and can be widely used as data for data loggers, which have become rapidly popular in recent years, and also for remote measurement. It is.

[Brief explanation of drawings]

FIG. 1 is a time-output characteristic diagram used to explain the demand transducer according to the present invention, FIG. 2 is a block diagram showing an example of the demand transducer according to the present invention, and FIG. 3 is a diagram showing the same demand transducer. Fig. 4 is a block diagram showing one embodiment of the maximum value hold circuit and minimum value hold circuit, and Fig. 5 shows a modified example of the maximum value hold circuit and minimum value hold circuit. It is a block diagram. (1)...Subtraction circuit, (2)...Pulse width change i1J
circuit, (3)... oscillation circuit, (4)... counter,
(5)...Digital-to-analog converter, (6)
...Input terminal, (7)...Output terminal, (8)...
Maximum value hold circuit, (9)...Minimum value bold circuit, (81)...Digital comparator, (82)
, (84), (i15)...Latch circuit, (8
3)...Analog comparator. Note that the same reference numerals in the figures indicate the same or corresponding parts. Agent Oiwa J = i4f: 1st knee” 2nd (ri1

Claims (3)

[Claims] (1) A subtraction circuit that obtains an output proportional to the difference between input and output, a pulse width modulation circuit that generates a pulse with a duty ratio proportional to the output of the subtraction circuit, and a pulse period of this pulse width modulation circuit. an oscillation circuit that outputs short-cycle pulses; an output terminal of the pulse width modulation circuit is connected to the up-count/down-count switching input terminal; and an output terminal of the oscillation circuit is connected to the clock pulse input terminal. A counter and digital output of the counter.
1. Record the maximum value and/or minimum value of the outputs of the first digital-to-analog converter that performs analog conversion and the digital-to-analog converter of the counter or nest 1. 1. A demand transducer comprising: a hold circuit configured to hold the output of the first digital-to-analog converter, and to adjust the output in proportion to the input with a time constant that can be arbitrarily selected from the output limit of the first digital-to-analog converter. (2) The hold circuit consists of a latch circuit and a digital comparator, and a digital comparator compares the output of the counter and the output of the latch circuit to determine whether the output is large or small, and the output of the digital comparator is used to connect the latch circuit to the latch circuit. The demand transducer according to claim 1, wherein the maximum value and/or minimum value of the output of the counter is stored. (3) The hold circuit includes a latch circuit, a second digital converter that converts the output of the latch circuit into digital/analog, and a digital/analog converter that converts the output of the second digital/analog converter and the first digital/analog converter. A clock comprising an analog comparator that compares the magnitude of the output and stores the maximum 11H and/or minimum value of the output of the PIIJ counter in the latch circuit using the output of the analog comparator.Claim 1
Demand transducer described in section.