JPS5920742U

JPS5920742U - signal isolation circuit

Info

Publication number: JPS5920742U
Application number: JP1982112811U
Authority: JP
Inventors: 宮崎　恒男
Original assignee: Toshiba Corp
Current assignee: Toshiba Corp
Priority date: 1982-07-27
Filing date: 1982-07-27
Publication date: 1984-02-08

Abstract

(57)【要約】本公報は電子出願前の出願データであるた
め要約のデータは記録されません。(57) [Summary] This bulletin contains application data before electronic filing, so abstract data is not recorded.

Description

[Brief explanation of drawings]

← 第１図は従来の絶縁トランスを用いた信号絶縁回路の回
路図、第２図は従来のフォト・カプラを用いた信号絶縁
回路の回路図、第３図は本考案に係る信号絶縁回路の回
路図、第４図は本考案の他の実施例を示す回路図、第５
図は第３図に示す回路を電気機器の出力端子に構成した
回路図である。１・・・信号源、４・・・電気機器、６・・・ＦＥＴ、
　７・・・演算増幅器、ａ、　　ｂ・・・信号入力端、
ｃ、　　ｄ・・・信号　　　。出力端、Ｒ１・・・第１抵抗、Ｒ２・・・第２抵抗、Ｒ
３・・・第３抵抗、Ｃ・・・コンデンサ、Ｒ４・・・第
４抵抗（ソース抵抗）、Ｒ６・・・第５抵抗（ドレイン
抵抗）、十Ｂ・・・直流電源、Ｇ・・・ゲート、Ｓ・・
・ソース、Ｄ・・・ドレイン。← Figure 1 is a circuit diagram of a signal isolation circuit using a conventional isolation transformer, Figure 2 is a circuit diagram of a signal isolation circuit using a conventional photocoupler, and Figure 3 is a circuit diagram of a signal isolation circuit according to the present invention. Circuit diagram, Fig. 4 is a circuit diagram showing another embodiment of the present invention, Fig. 5 is a circuit diagram showing another embodiment of the present invention.
The figure is a circuit diagram in which the circuit shown in FIG. 3 is configured as an output terminal of an electrical device. 1... Signal source, 4... Electric equipment, 6... FET,
7...Operation amplifier, a, b...Signal input terminal,
c, d...signal. Output end, R1...first resistance, R2...second resistance, R
3...Third resistance, C...Capacitor, R4...Fourth resistance (source resistance), R6...Fifth resistance (drain resistance), 10B...DC power supply, G... Gate, S...
・Source, D...Drain.

Claims

[Scope of utility model registration request]

(1) A first resistor, a second resistor, a parallel circuit consisting of a third resistor, and a capacitor are connected in series to both ends of the signal input terminal, and an amplifier circuit with high input impedance is connected to both ends of the second resistor. A signal isolation circuit characterized by having an output terminal.

(2) In the amplifier circuit, a gate is connected to the connection point of the first resistor and the second resistor, a source is connected to the other end of the second resistor via a fourth resistor, and a drain is connected to the other end of the second resistor via a fifth resistor. It is composed of an FET connected to a DC power supply, one of the signal output terminals is the drain, and the other terminal is a connection point between the second resistor and the fourth resistor, and the resistance value of the first resistor is R1, The second resistor is R2, the third resistor is R3, the fourth resistor is R2, and the fifth resistor is R2.
If the resistor is R6, the input impedance of the FET is ZFl, and the impedance of the capacitor to the input signal is Zc, then under the conditions of ZF>R2, Zc<R1+R2+R3, the relationship ・R2/(Rx + R2) = R4/R5 is established. 2. The signal isolation circuit according to claim 1, wherein the circuit constants are determined so as to satisfy the following conditions.

(3) The signal isolation circuit according to claim 2, wherein the FET is a junction FET, and the resistance value of the second resistor is selected to be approximately 107 to 1060.