JPS59208A - Gain controlling circuit - Google Patents

Gain controlling circuit

Info

Publication number
JPS59208A
JPS59208A JP57109325A JP10932582A JPS59208A JP S59208 A JPS59208 A JP S59208A JP 57109325 A JP57109325 A JP 57109325A JP 10932582 A JP10932582 A JP 10932582A JP S59208 A JPS59208 A JP S59208A
Authority
JP
Japan
Prior art keywords
circuit
mixing
input terminal
gain
transistor
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP57109325A
Other languages
Japanese (ja)
Inventor
Norihiko Ideshita
井手下 憲彦
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
NEC Corp
Original Assignee
NEC Corp
Nippon Electric Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by NEC Corp, Nippon Electric Co Ltd filed Critical NEC Corp
Priority to JP57109325A priority Critical patent/JPS59208A/en
Publication of JPS59208A publication Critical patent/JPS59208A/en
Pending legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04H—BROADCAST COMMUNICATION
    • H04H60/00—Arrangements for broadcast applications with a direct linking to broadcast information or broadcast space-time; Broadcast-related systems
    • H04H60/02—Arrangements for generating broadcast information; Arrangements for generating broadcast-related information with a direct linking to broadcast information or to broadcast space-time; Arrangements for simultaneous generation of broadcast information and broadcast-related information
    • H04H60/04—Studio equipment; Interconnection of studios

Landscapes

  • Engineering & Computer Science (AREA)
  • Signal Processing (AREA)
  • Control Of Amplification And Gain Control (AREA)

Abstract

PURPOSE:To realize satisfactorily both of a dissolving operation and an add- mixing operation, by switching an input signal to an amplifier, at the time of said two operations. CONSTITUTION:In case when dissolve-mixing is executed, (k) and (l) are connected by switching circuits 9, 10. A video signal inputted to a terminal 1 is inputted to an input terminal (a) of a circuit 5. The video signal inputted to a terminal 3 is inputted to an input terminal (b) of a circuit 6. The gain of the circuit 5 is kept constant, and a good dissolving operation can be realized. In case when add-mixing is executed, (k) and (m) are connected by the switching circuits 9, 10. The circuit 5, 6 can amplify the video signal inputted separately to each terminal 1, 3, therefore, the add-mixing can be executed by deciding the gain independently each other.

Description

【発明の詳細な説明】 本発明はテレビシロン伝送系に関し、特にテレビジョン
信号の利得制御回路に関する。
DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a television transmission system, and more particularly to a gain control circuit for television signals.

従来からテレビシロン伝送系では、フェーダ−レバーに
より映像信号を減衰させたり、二づの映像信号を混合さ
せたり、又二つの映像信号の画面転換等を行わせるため
に、フェーダ−レバーからの制御信号により利得を制御
する利得制御回路が用いられている。例えば、二つの映
像画面を同時に互いに逆に増減させて成る画面から別の
画面に時間的な傾斜を持たせて転換させるいわゆるデゾ
ルブ動作を行わせるためには、フェーダ−レバーの制御
信号により一方の映像信号を増大させ、他方の映l信号
を減衰させるように利得制御回路を構成する。デゾルプ
動作の場合、画面転換させる両映像信号が同じ場合が混
合列の入れ換え等において多々あり、このような場合デ
ゾルブ動作により利得制御回路出力レベルか変動する。
Conventionally, in TVSILON transmission systems, control from the fader lever has been used to attenuate the video signal, mix two video signals, or switch the screen between two video signals. A gain control circuit is used that controls the gain using a signal. For example, in order to perform a so-called dissolve operation in which two video screens are simultaneously increased and decreased in opposite directions and changed to another screen with a temporal inclination, one of the video screens can be changed using a control signal from a fader lever. A gain control circuit is configured to increase the video signal and attenuate the other video signal. In the case of the dissolve operation, there are many cases where both video signals to be screen changed are the same, such as when mixing columns are replaced, and in such cases, the output level of the gain control circuit changes due to the dissolve operation.

すなわちいわゆるクロスフェード特性が悪い利得制御回
路があった。又、このような利得制御回路は回路構成に
よっては利得の変動等が生ずる欠点も有していた。これ
らの欠点を解決するため、利得制御回路の出力を利得制
御回路?構成する利得制御増巾器へ負帰還させることに
よりクロスフェード特性が良好でしかも利得変動が少な
い利得制御回路が考案され使用されて釆た。
That is, there were gain control circuits with poor cross-fade characteristics. Furthermore, such gain control circuits also have the disadvantage that gain fluctuations may occur depending on the circuit configuration. In order to solve these drawbacks, is the output of the gain control circuit changed to a gain control circuit? A gain control circuit with good cross-fade characteristics and little gain fluctuation was devised and put into use by providing negative feedback to the constituent gain control amplifiers.

第1図はクロスフェード特性が良好な従来の利得制御回
路の一例を示す回路図であり、入力端子101.102
には各々入力映像信号が供給される。
FIG. 1 is a circuit diagram showing an example of a conventional gain control circuit with good cross-fade characteristics.
are each supplied with an input video signal.

入力端子101はトランジスタ104のベースに、又入
力端子102はトランジスタ115のベースにそれぞれ
接続されている。トランジスタ104゜105と、トラ
ンジスタ108.109と、トランジスタ110,11
1と、トランジスタ114,115と、トランジスタ1
18,119と、トランジスタ120.121とはそれ
ぞれ差動回路を構成しておす、トランジスタ104.1
05のエミッタはトランジスタ106のコレクタに、ト
ランジスタ108゜109のエミッタはトランジスタ1
04のコレクタに、トランジスタ110.111のエミ
ッタはトランジスタ105のコレクタに、トランジスタ
114.115のエミッタはトランジスタ116のコレ
クタに、トランジスタ118,119のエミッタはトラ
ンジスタ114のコレクタに、トランジスタ120.1
21のエミッタはトランジスタ115のコレクタにそれ
ぞれ接続されている。又トランジスタ106のエミッタ
は抵抗器107を介して、トランジスタ116のエミッ
タは抵抗器117を介してそれぞれ負電源に接続される
。トランジスタ106,116のベースは適当なバイア
ス電圧VBに保たれている。又トランジスタ109,1
10゜118.121のコレクタはそれぞれ正電源に接
・続される。一方トランジスタ108,120のコレク
タは抵抗器112?介して、トランジスタ111゜11
9のコレクタは抵抗器113を介してそれぞれ正電源に
接続される。トランジスタ109.110 。
Input terminal 101 is connected to the base of transistor 104, and input terminal 102 is connected to the base of transistor 115. Transistors 104 and 105, transistors 108 and 109, and transistors 110 and 11
1, transistors 114 and 115, and transistor 1
18, 119 and transistors 120 and 121 constitute a differential circuit, respectively. Transistor 104.1
The emitter of transistor 05 is connected to the collector of transistor 106, and the emitter of transistors 108 and 109 is connected to transistor 1.
04, the emitter of transistor 110.111 is connected to the collector of transistor 105, the emitter of transistor 114.115 is connected to the collector of transistor 116, the emitters of transistors 118 and 119 are connected to the collector of transistor 114, and the emitter of transistor 120.1 is connected to the collector of transistor 114.
The emitters of 21 are connected to the collectors of transistors 115, respectively. Further, the emitter of the transistor 106 and the emitter of the transistor 116 are connected to a negative power supply through a resistor 107 and a resistor 117, respectively. The bases of transistors 106 and 116 are held at a suitable bias voltage VB. Also, the transistor 109,1
The collectors of 10°118 and 121 are respectively connected to the positive power supply. On the other hand, the collectors of transistors 108 and 120 are resistors 112? Through the transistor 111゜11
The collectors of 9 are each connected to a positive power supply via a resistor 113. Transistor 109.110.

119.120のベースは各々接続され、適当なバイア
ス覗圧VRFiF に保たれる。一方トランジスタ10
8.111,118.121のベースは各々接続され、
制御電圧入力端子103に接続されている。
The bases of 119 and 120 are each connected and maintained at an appropriate bias viewing pressure VRFiF. On the other hand, transistor 10
The bases of 8.111 and 118.121 are connected respectively,
It is connected to the control voltage input terminal 103.

又トランジスタ108,120のコレクタはトランジス
タ122のベースに、トランジスタ111゜119のコ
レクタはトランジスタ123のベースにそれぞれ接読さ
れている。トランジスタ122゜123tj:差動回路
全構成しており、トランジスタ122.123のエミッ
タは抵抗器124 k介して正電源に接続されている。
The collectors of transistors 108 and 120 are connected to the base of transistor 122, and the collectors of transistors 111 and 119 are connected to the base of transistor 123, respectively. Transistors 122 and 123tj: Completely constitutes a differential circuit, and the emitters of transistors 122 and 123 are connected to the positive power supply via a resistor 124k.

又トランジスタ122゜123のコレクタはそれぞれ抵
抗器125,126を介して負電源に接続される。又ト
ランジスタ122のコレクタはトランジスタ127のベ
ースにも接続されている。トランジスタ127のエミッ
タは抵抗器128を介して正電源に、トランジスタ12
7のコレクタは負電源に接続されている。
Further, the collectors of transistors 122 and 123 are connected to a negative power supply via resistors 125 and 126, respectively. The collector of transistor 122 is also connected to the base of transistor 127. The emitter of transistor 127 is connected to the positive power supply through resistor 128, and
The collector of 7 is connected to the negative power supply.

又トランジスタ127のエミッタは出力端子129とト
ランジスタ105,114のベースにそれぞれ接続され
ている。
Further, the emitter of the transistor 127 is connected to the output terminal 129 and the bases of the transistors 105 and 114, respectively.

本図において、トランジスタ104〜111までか第一
の利得制御部をトランジスタ114〜121か第二の利
得制御部を各々抵抗112.113を共通負荷として構
成し、トランジスタ122,123゜127までか増幅
器を構成している。いま制御電圧入力端子103の入力
電圧かバイアス電1圧VRgFより高いとトランジスタ
108,111,118.1121かそれぞれ導通にな
るから信号入力端子101 より供給された映像信号が
゛、又制御電゛圧入力端子103の入力電圧がバイアス
電圧V RgFより低いとトランジスタ109,110
,119,120がそれぞれ導通となるから信号入力端
子102より供給された映像信号か゛、又制御電圧入力
端子103の入力電圧がバイアス電圧V REF近辺に
なると両映隊信号が混合された形で各々トランジスタ1
08,120及びトランジスタ111,119のコレク
タより取り出され、トランジスタ122,123のベー
スに入力され増幅される。増幅された映像信号はトラン
ジスタ127のエミッタに現れ、出力端子129より出
力されると同時にトランジスタ105,114のベース
に100%負帰還される。
In this figure, transistors 104 to 111 or a first gain control section, transistors 114 to 121, or a second gain control section are each configured with resistors 112 and 113 as a common load, and transistors 122, 123 and 127 are configured as amplifiers. It consists of Now, if the input voltage of the control voltage input terminal 103 is higher than the bias voltage 1 voltage VRgF, each of the transistors 108, 111, 118, and 1121 becomes conductive, so that the video signal supplied from the signal input terminal 101 is When the input voltage of the input terminal 103 is lower than the bias voltage V RgF, the transistors 109 and 110
. transistor 1
The signal is taken out from the collectors of transistors 08 and 120 and transistors 111 and 119, and input to the bases of transistors 122 and 123, where it is amplified. The amplified video signal appears at the emitter of the transistor 127, is output from the output terminal 129, and is simultaneously 100% negatively fed back to the bases of the transistors 105 and 114.

このため、この利得制御回路の利得は、第一の利得制御
部の利得tG1.第1.利得制御部の利得’tG2とす
れば、常に01十02=一定(ioo%)となり、制御
電圧入力端子103の電圧10〜100%変化させたと
きこの制御Iil!圧の比率でGl、G2は決定される
が、総合利得は一定と、なる。従って。
Therefore, the gain of this gain control circuit is equal to the gain tG1. of the first gain control section. 1st. If the gain of the gain control section is 'tG2, it will always be 01-02=constant (ioo%), and when the voltage at the control voltage input terminal 103 is changed by 10 to 100%, this control Iil! Gl and G2 are determined by the pressure ratio, but the overall gain is constant. Therefore.

信号入力端子101及び102に各々同じ映像信号金回
じレベルで加えたときは制御電圧入力端子103の電圧
10〜100%変化させる、即ちゲゾルブ動作をさせて
も出力端子129の映像信号は常に一定レベルに保たれ
良好なりロスフェード苛性及び利得変動特性が得られる
。
When the same video signal signal level is applied to the signal input terminals 101 and 102, the voltage at the control voltage input terminal 103 is changed by 10 to 100%, that is, the video signal at the output terminal 129 is always constant even if the Gesolve operation is performed. Good loss fade causticity and gain fluctuation characteristics are obtained.

かかる利得制御回路においてはクロスフェード特性は良
好となるが、一方総合利得Gt −1−02は常に一定
となるためG1十02を所定値(100%)以上即ち両
映像信号に対する利得を独立に制御して混合させること
ができない欠点を有していた。
In such a gain control circuit, the cross-fade characteristic is good, but on the other hand, the total gain Gt -1-02 is always constant, so G102 must be set at a predetermined value (100%) or higher, that is, the gains for both video signals are independently controlled. It had the disadvantage that it could not be mixed.

放送局等において、両映像信号を混合加算させる効果を
得る場合、両映像信号の和レベルを一定にする混合(ク
ロスフェード特性が良好なデゾルプ混合)だけでなく、
両信号に対応するフェーダ−レノや−に応じてそれぞれ
独立に両信号を増幅し、画壇幅信号をそのまま加算する
方式の混合(以下、加算混合という)がしばしば必要と
され、前述した従来の利得制御回路ではこれらの要求に
対処できない欠点を有していた。
In broadcasting stations, etc., when obtaining the effect of mixing and adding both video signals, it is necessary not only to mix the sum level of both video signals to a constant level (desolp mixing with good cross-fade characteristics), but also to
Mixing (hereinafter referred to as additive mixing) is often required, in which both signals are amplified independently according to the faders corresponding to both signals, and the width signals are added as they are (hereinafter referred to as additive mixing). The control circuit has the drawback of not being able to meet these demands.

本発明の目的は、クロスフェード特性が良好なテゾルプ
混合ができ、しかも必要に応じ加算混合も可能な利得制
御回路の提供にある。
An object of the present invention is to provide a gain control circuit that can perform Tesolp mixing with good cross-fade characteristics and can also perform additive mixing if necessary.

本発明による利得制御回路は、第1及び第2の入力端子
に受けた信号それぞれに対する利得の比が制御電圧に応
じた値にtあようにこれら両信号を増幅する回路と、こ
れら増幅した両信号を混合する回路と この混合回路出
力を前記増幅回路に導くことによりこの増幅回路におけ
る前記利得それぞれの和才一定にする負帰還回路とをそ
れぞれ備える第1及び第2の回路と、この第1の回路の
前記第2の入力端子に加える信号を前記第2の回路の一
方の入力端子に受けた信号又は予め定め危所定電圧のい
ずれかに選択する手段と、この選択手段が前記第2の回
路の前記一方の入力端子に受けた信号全選択していると
きは前記第1の回路の混合回路出力?出力端子に導くと
ともに、その1選択手段が前記予め定めた所定電圧を選
択しているときは前記第1及び第2の回路それぞれの前
記混合回路出力を混合して出力端子に導ズ手段とを有し
て構成される。
The gain control circuit according to the present invention includes a circuit that amplifies the signals received at the first and second input terminals so that the gain ratio t for each signal is a value corresponding to the control voltage, and a circuit that amplifies the signals received at the first and second input terminals. first and second circuits each comprising a circuit for mixing signals and a negative feedback circuit for guiding the output of the mixing circuit to the amplifier circuit to keep the sum of the respective gains in the amplifier circuit constant; means for selecting a signal to be applied to the second input terminal of the circuit from either the signal received at one input terminal of the second circuit or a predetermined critical voltage; When all the signals received at the one input terminal of the circuit are selected, is the mixing circuit output of the first circuit? and conductive means to mix the mixing circuit outputs of the first and second circuits to the output terminal when the one selection means selects the predetermined voltage. It is composed of:

以下図面ヲ診照して本発明の詳細な説明する。The present invention will be described in detail below with reference to the drawings.

第2図は本発明の一実施例を示す構成図であり。FIG. 2 is a configuration diagram showing an embodiment of the present invention.

第一の映像信号入力端子1.第一の制御電圧入力端子2
%第二の映像信号入力端子3.第二の制御電圧入力端子
4.第一の映像信号と第二の映像信号を第一の制御電圧
により利得制御する第一の回路5.第二の映像信号全第
二の制御電圧により利得制御する第二の回路6.第一の
回路5および第一二の回路6の出力を混合する抵抗器7
および8゜混合動作がデゾルグ混合のときは第一の回路
により第−及び第二の映像信号を第一の制御電圧で利は
第−及び第二の映像信号を第−及び第二の制御電圧によ
り第−及び第二の回路5.6で各々利得制御した後混合
するように切替える切替回路9および10、デゾルグ混
合のときに加算混合のときと同じ総合利得?設定する抵
抗器11、出力端子12から構成されている。
First video signal input terminal 1. First control voltage input terminal 2
%Second video signal input terminal3. Second control voltage input terminal 4. 5. A first circuit that controls the gain of the first video signal and the second video signal using the first control voltage. 6. A second circuit that controls the gain of the second video signal using a second control voltage. Resistor 7 for mixing the outputs of the first circuit 5 and the first second circuit 6
When the 8° mixing operation is Desorge mixing, the first circuit controls the second and second video signals at the first control voltage; According to the switching circuits 9 and 10, which switch to mix after each gain control in the first and second circuits 5 and 6, the total gain is the same in the case of Desorge mixing as in the case of additive mixing. It consists of a resistor 11 to be set and an output terminal 12.

第一および第二の回路5,6は例えば第1図の如く、外
部からの制御信号に応じて二つの信号が互いに逆に増減
される如く利得が変る利得制御増幅器とこの利得制御増
幅器の出力を受ける出力増幅器とを具備し、出力増幅器
の出力を利得制御増幅器へ負帰還し、クロスフェード特
性を良好ならしめるように構成される。ここで第1及び
第2の回路5,6のaは第1図の信号入力端子101に
。
The first and second circuits 5 and 6 are, for example, as shown in FIG. 1, a gain control amplifier whose gain changes so that two signals are inversely increased or decreased in response to an external control signal, and an output of this gain control amplifier. The output amplifier is configured to negatively feed back the output of the output amplifier to the gain control amplifier to improve cross-fade characteristics. Here, a of the first and second circuits 5 and 6 are connected to the signal input terminal 101 in FIG.

同じくbは入力端子102に、Cは制611を圧入力端
子103に、dは出力端子129にそれぞれ対応してい
る。切替回路9及び1oは連動動作しデゾルデ混合で各
々に一1間が接続され、加算混合で各々に−m間が接続
される。従って、デゾルグ混合回路5のaおよびbに入
力され、制御電圧入力端子2からの制御電圧でクロスフ
ェード特性の良好な利得制御がなされ、抵抗器7を経て
出力端子12から送出される。ここで抵抗器11はデゾ
ルブ混合のときに出力端子12に接続され、総合利得を
加算混合時の利得に合せるための抵抗器で1片側は第−
及び第2の回路5.6のd端子のDC電位に設定する。
Similarly, b corresponds to the input terminal 102, C corresponds to the pressure input terminal 103 for the control 611, and d corresponds to the output terminal 129. The switching circuits 9 and 1o operate in conjunction, and the terminals 11 and 11 are connected to each other by desolde mixing, and the terminals -m and 10 are connected to each other by addition mixing. Therefore, the signal is input to a and b of the desorge mixing circuit 5, gain control is performed with good cross-fade characteristics using the control voltage from the control voltage input terminal 2, and the signal is sent out from the output terminal 12 via the resistor 7. Here, the resistor 11 is connected to the output terminal 12 during dissolve mixing, and is a resistor for matching the total gain to the gain during additive mixing.
and set to the DC potential of the d terminal of the second circuit 5.6.

又、第二の回路6の入力端子bVi適当なバイアス電圧
VREF  に保たれる。一方加算混合動作のときは第
一の映像信号は第一の回路5のaに、第二の映摩信号は
第二の回路6のaにそれぞれ接続され、制御電圧入力端
子2及び4からの制御電圧により各々独立に利得制御が
なされ、抵抗器7及び8により混合され出力端子12よ
V送出される。このとき第−及び第二の回路5,6の入
力端子すは適当なバイアス電圧VREF Vc保た篩。
Further, the input terminal bVi of the second circuit 6 is maintained at an appropriate bias voltage VREF. On the other hand, during addition and mixing operation, the first video signal is connected to a of the first circuit 5, the second video signal is connected to a of the second circuit 6, and the control voltage input terminals 2 and 4 are connected to each other. The gain is independently controlled by the control voltage, mixed by resistors 7 and 8, and sent to the output terminal 12. At this time, the input terminals of the first and second circuits 5, 6 are kept at a suitable bias voltage VREFVc.

このように構成されているから、フェーダ−レバーによ
る二つの映像信号の混合、画面転換等の際、デゾルブ混
合または加算混合のいずれか一方の選択に応じて切替回
路9および10を切替えることにより、デゾルプ混合の
ときはクロスフェード特性が良好な混合が行え、加算混
合のときは両映像信号をそれぞれ独立に利得制御して両
信号を加算し混合させうる。
With this configuration, when mixing two video signals using the fader lever, switching screens, etc., by switching the switching circuits 9 and 10 according to the selection of either dissolve mixing or addition mixing, In the case of desolp mixing, mixing with good cross-fade characteristics can be performed, and in the case of additive mixing, the gains of both video signals can be controlled independently to add and mix the two signals.

以上詳細に説明したように1本発明によれば、クロスフ
ェード特性が良好なデゾルプ混合ができ。
As described above in detail, according to the present invention, desolp mixing with good cross-fade characteristics can be performed.

しかも必要に応じ加算混合も可能な利得制御回路が得ら
れる。
Moreover, a gain control circuit capable of performing additive mixing as required can be obtained.

【図面の簡単な説明】[Brief explanation of the drawing]

第1図は従来の利得制御回路を示す回路図、第2図は本
発明の一実施例?示す構成図である。 101.102・・・・・・映像信号入力端子、103
・・・・・・制御電圧入力端子、104,105,10
6,108゜109.110,111,114,115
,116゜118.119,120,121,122,
123゜129・・・・・・トランジスタ、107,1
12,113゜117.124,125,126.12
8・・・・・・抵抗器。 129・・・・・・映像信号出力端子、1,3・・・・
・・映像信号入力端子、2,4・・・・・・制御電圧入
力端子、5・・・・・・第1の回路、6・・・・・・第
2の回路、7,8.11・・・・・・抵抗器、9.10
・・・・・・切替回路、12・・・・・・映像信号出力
端子。 代理人 弁理士  内 原   晋
Fig. 1 is a circuit diagram showing a conventional gain control circuit, and Fig. 2 is an embodiment of the present invention. FIG. 101.102...Video signal input terminal, 103
...... Control voltage input terminal, 104, 105, 10
6,108°109.110,111,114,115
,116°118.119,120,121,122,
123°129...transistor, 107,1
12,113°117.124,125,126.12
8...Resistor. 129...Video signal output terminal, 1,3...
...Video signal input terminal, 2, 4... Control voltage input terminal, 5... First circuit, 6... Second circuit, 7, 8.11 ...Resistor, 9.10
......Switching circuit, 12...Video signal output terminal. Agent Patent Attorney Susumu Uchihara

Claims (1)

【特許請求の範囲】[Claims] 第1及び第2の入力端子に受けた信・号それぞれに対す
、ρ利得の比が制御電圧に応じた値になるようにこれら
両信号を増幅する回路と これら増幅した両信号を混合
する回路と、この混合回路出力を前記増幅回路に導くこ
とによりこの増幅回路における前記利得それぞれの和を
一定にする負帰還回路とをそれぞれ備える第1及び第2
の回路と、この第1の回路の前記第2の入力端子に加え
る信号tl−前記第2の回路の一方の入力端子に受けた
信号又は予め定め7cr9r定電圧のいずれかに選択す
る手段と、この選択手段が前記@20回路の前記一方の
入力端子に受けた信号を選択しているときは前記第1の
回路の混合回路出力を出力端子に導くとともに、その選
択手段が前記予め定めた所定電圧全選択しているときは
前記第1及び第2の回路それぞれの前記混合回路出力を
混合して出力端子に導く手段とを有する利得制御回路。
A circuit that amplifies the signals received at the first and second input terminals so that the ratio of ρ gain becomes a value corresponding to the control voltage, and a circuit that mixes these amplified signals. and a negative feedback circuit that leads the output of the mixing circuit to the amplifier circuit to keep the sum of the respective gains in the amplifier circuit constant.
a circuit, and means for selecting either a signal tl applied to the second input terminal of the first circuit, a signal received at one input terminal of the second circuit, or a predetermined 7cr9r constant voltage; When this selection means selects the signal received at the one input terminal of the @20 circuit, the mixing circuit output of the first circuit is guided to the output terminal, and the selection means selects the signal received at the one input terminal of the @20 circuit. a gain control circuit comprising means for mixing the mixing circuit outputs of the first and second circuits and guiding the mixture to an output terminal when all voltages are selected.
JP57109325A 1982-06-25 1982-06-25 Gain controlling circuit Pending JPS59208A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP57109325A JPS59208A (en) 1982-06-25 1982-06-25 Gain controlling circuit

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP57109325A JPS59208A (en) 1982-06-25 1982-06-25 Gain controlling circuit

Publications (1)

Publication Number Publication Date
JPS59208A true JPS59208A (en) 1984-01-05

Family

ID=14507362

Family Applications (1)

Application Number Title Priority Date Filing Date
JP57109325A Pending JPS59208A (en) 1982-06-25 1982-06-25 Gain controlling circuit

Country Status (1)

Country Link
JP (1) JPS59208A (en)

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