JPS5922158A - data processing equipment - Google Patents

Abstract

PURPOSE:To prevent a decrease in the output efficiency of a multi-processor system by dividing the address area of a common memory into plural areas by providing limited lock display signal lines for transmitting signals which indicate lock states of the respective address areas. CONSTITUTION:Plural processors Pi (i=1-n) is accessible to the common memory 3 through a common bus 2 under the control of a deciding circuit for the right of the use of the common bus. The address area in the memory 3 is divided into (m) areas, and signal lines 19-j (j=1-m) for transmitting limited lock display signals BLKj corresponding to the respective address areas and a limited lock generating circuit 18 which transmits and receives the signals BLKj to and from the Pi are provided. The circuit 18 decides on an address area wherein a lock signal 15 and an address signal from the Pi are limited and locked, and sends a request signal 20 for the use of the common bus to the circuit 4 when the bus request signal 9 is received from the Pi and the signal line 19-j corresponding to the determined address area is at a level L. Then when a permit signal 10 for the use of the bus is supplied from the circuit 4, the circuit 18 sets the signal BLKj to a level H to place the signal line 19-j in a locked state.

Description

DETAILED DESCRIPTION OF THE INVENTION Field of the Invention The present invention relates to a multiprocessor type data processing device in which a plurality of processors use a common memory via a common bus.

Structure of Prior Art Conventionally, there has been a device of this type as shown in FIG. In Figure 1, ("-'L("-2L =-(1-n)
are processors p, +P2 +...Pn, respectively.
, +21 is a common bus, (31 is a common memory, and +41 is a common bus usage right determination circuit.
This is a block diagram mainly showing the input/output signals of the internal configuration of the (indicated by i)). The same reference numerals as in Fig.
5) is a CPU, and 61 is an arbiter for acquiring the right to use the common bus.

(7) is a common bus signal connection buffer, (8) is a decoder for generating a start signal for the arbiter (6), (9) is a common path use request signal (hereinafter abbreviated as B REQ), ! In
) is the common bus use permission signal (hereinafter abbreviated as BPRN)
, old] is the common bus busy indication signal (hereinafter abbreviated as BUSY), and 0a is the address signal (hereinafter abbreviated as ADR).
, tl:31 is data partial (hereinafter abbreviated as DATA)
, 0 fathom is a control signal (hereinafter abbreviated as CNTL), ←9 is a lock signal (hereinafter abbreviated as LOCK), OQ is a start signal for the arbiter (6) (hereinafter abbreviated as MRQ)
, (1,7+ is an activation signal (hereinafter abbreviated as BL!) for the buffer (7).

Common bus (21 includes address signal line, data signal line, and control signal line) j! The 1 bus (2) and the common memory (3) are used by each processor in a time-sharing manner, and which processor uses it is determined by the BREQ (9+) from the common bus usage right determination circuit (
41, based on preset priority rules, 1
Only one processor is allowed to be used at a time.

When continuous writing is performed from the processor Pi (1-i) to the address area in the common memo (Jan.
It may be inconvenient for other processors to use the data in the address area, and in such cases, it is necessary to prohibit access from other processors to the address area.

In such a case, LOCK (1cJ is the logic rHJ and below, the active state of all the signals is logic rl (represented by J). Even if the common bus usage right determination circuit (4) Even if (10) is set to logic rLJ, BUSY (11) is kept at logic rH and the arbiter (61) does not give up the right to use the common bus 12+.

Operation of the prior art FIG. 3 is a timing diagram showing the operation of each signal in FIG. 2, the horizontal axis indicates time t, and FIGS.
OCK Q! 1, MRQ Q*, BREQ +
91, BpRN 1101, BUSY(lυ,
BEN (171) shows the logic of each signal AI) R (12, DATAO31, CNTL04).
tD remittance amount indication. The operation of the conventional device will be explained below with reference to FIG. [CPU 151 i'l:
At time t+, access operation to the common memo (January 3) started and ADR (12, DATA (131, CNTL (14)
Output.

ADRQ2 is input to the if decoder 181 and MRQ (
Generate li' and activate Rarevita (6) completely. arbiter(
6) sets BREQ (9) to logic rHJ at time t2, which is input to the judgment circuit (4(), 1 predetermined priority + 11
There is a judgment based on fi logic, and processor pi(1-
If i) is granted the right to use, the judgment time is t3 in 1st round.
BPRN 110) to logical rHJ at time
1, the arbiter (6) is informed. The arbiter (61- is BUSY (IllO logic f, check, and if this is logic "L" (indicating unused state), it is set to logic r HJ at time t4. This causes the processor P
When j (1-i) is able to use the common bus (2)9, the arbiter (6) sets BEN (171 to logic rH) and inputs ADR (12,
DATA Q31, CNTL (1,1,) U
The signal is output from Hough 77 +71 to the common bus, and an access operation to the common memory (3) is performed.

CPU +51 at access request operation start time t1
is LOCK (if lυ is set to logic “■1”,
Arbiter (6) has LOCK (15) input as logic rHj
BUSY1υ is kept at logic "■(") while other higher priority processors request the common bus (2) and the BPRN (10) for the processor Pi (1-i) is maintained as shown at time t5. does not give up the right to use the common bus (2) even if it becomes logical rLJ.As a result, CPU+51
accesses the common memory 131 continuously, and a series of data is accessed midway by another processor and its contents are modified, or the processor Pi(1-i) replaces a series of data with another processor and changes the contents. It is possible to completely prevent accidents in which the processor reads the entire series of data, including data that has been rewritten and data that has not been rewritten. Such a conventional device is well known as a multiprocessor type data processing device.

Disadvantages of the Prior Art However, in such a conventional device, LOCKα9 is set to logic "11" in processor Pi (1-i), for example.
, even if another processor with a higher priority tries to urgently access another area unrelated to the area being accessed by processor pi(1-i), processor Pi(1-i) ) and must wait until LOCK (1!3 becomes logical rLJ. This means that
This is a drawback that reduces the overall processing efficiency of the multiprocessor.

Purpose of the Invention The present invention has been made in order to eliminate the above-mentioned drawbacks of the conventional ones.The present invention divides the address area in a common memory into a plurality of appropriate address areas, and locks only the desired address area. , other address areas can be accessed by other processors with higher priority, and if the lock is continued without finishing processing on a series of data in the locked area, other processors can If the common bus is occupied by the other processor, the multiprocessor The object of the present invention is to provide a data processing device that prevents a decrease in operating efficiency.

Configuration of the present invention The present invention will be described in detail below with reference to the drawings.

FIG. 4 is a block diagram showing an embodiment of the present invention.
The same reference numerals as in the figure indicate the same or equivalent parts or the same or equivalent signals, and the address area of the common memory (3) is Al-
A case is shown in which the area is divided into m address areas of Am. (
The country is a limited lock generation circuit, (19-1), ---(
19-m) are limited lock indication signals (hereinafter BLKI--
--BLKm) and υ) are common bus use request signals (hereinafter abbreviated as BRQC) sent from the limited lock generation circuit decoy to the determination circuit (4). Signal BLKI
(19-1), BLKm (19-m) and f, respectively, limited lock display signal lines are provided in the common bus (2).

Operation of the present invention FIG. 5 is a timing diagram showing the operation of each signal in FIG. 4, and is displayed using the same display method as FIG. 3.

Figures (a) to (h) show each signal LOCK (15),
BLKj (19-j).

MRQ (16), BREQ (9), BRQC (20)
, BPRN (10).

The logic of BUSY(11) and BEN(17) is shown in FIG. 5(i) to (ri).
Shows the remittances of TA (13) and CNTL (14). The operation of the apparatus shown in FIG. 4 will be explained below with reference to FIG.

Processor Pi(1-i) enters a locked common memory (3) access operation at time t7. That is, CPU +
51 is LOCK (15) 'f: Logic r HJ K L
, ADR(ls, DATACI country.

Send CNTL (14). Decoder (8) is M
I7Q (16) is set to logic rHJ, and arbiter (6) is set to B
Setting REQ (9) to logic “H” at time t8 is the second
This is the same as the case shown in the figure. The limited lock generation circuit f181 receives inputs of 1,0CK (15) and ADR (12).
Determine the compensation of j of Kj (19-j). BREQ
(When the input of 91 becomes rHJ, Bl, Kj (19-j)
Examine the logic of At time t8, other processors say no that BE, Kj (19-j) is logical rHJ.

Since the address area of J is locked, processor pi(1-i) is prohibited from accessing it.

BLKj (19-co) becomes logical rLJ at time t7,
Limited lock generation circuit (1, 81 immediately BRQC (20
) to the logic rHJ and requests the determination circuit (41. The arbiter (6) waits for the BPRNllo) to become the logic "14", but during this time, at the time tlO, BLKj (19-j
) becomes logic rHJ, it means that another processor with a higher priority is accessing the address area No.j with a lock, and at this time, the limited lock generation circuit outputs BRQC. Return the logic of (20) to If, J. When the logic of BLKj (19-j) returns to rLJ at time t1□, if BREQ +91 is logic "■(", BRQC (20) becomes logic rHJ again and the common bus (
2) Request. tl. As a special feature, BPRN (10) becomes logic rHJ, and processor Pi (1-i) uses the common bus (
2), the limited lock generation circuit α seconds is B
LKj (19-j) is set to logic "H". B.P.
Since it is also input to the RN[01 arbiter (6), the operation similar to that of the circuit shown in FIG. 2 is performed immediately thereafter.

That is, the arbiter waits for BUSY (11) to become logic rLj, and at time t13, BUSY (11) and BEN (
17) to logic "IJ" and ADR (IJ.

DATA (13) and CNTL (14) are output, a common memory (3) access operation is performed, and ends at time t14.

Effects of the Present Invention As described above, according to the present invention, the lock function for accessing the common memory (3) is limited to a desired specific address area, and other processors cannot access other address areas. This makes it possible to improve the data processing efficiency of the entire device.

[Brief explanation of drawings]

Fig. 1 is a block diagram of a conventional device, Fig. 2 is a block diagram showing the internal configuration of any one processor in Fig. 1, and Fig. 3 is a timing diagram showing the operation of each signal in Fig. 2. , FIG. 4 is a block diagram showing an embodiment of the present invention,
FIG. 5 is a timing diagram showing the operation of each signal in FIG. 4. (1-i)...Processor pi, i21...Common bus, (3j...Common memory, (4)...Common bus usage right determination circuit, (9)...BREQ,
(10)...BPRN, (11n...BU
SY, (12)...ADR, (15)
...LOCK, (19-1)...BLKI. (20)-BRQC. Note that the same reference numerals in the figures indicate the same or equivalent parts. Agent Shin Kuzuno −

Claims (1)

[Claims] In a data processing device in which a plurality of processors access a common memory via a common bus under the control of a common bus usage right determining circuit, provided as part of the common bus,
The address area in the common memory is divided into a plurality of address areas, each corresponding to each limited lock display signal that transmits a key signal indicating relocking of each address area, and each processor of the plurality of 70 setsa mentioned above. means for connecting each limited lock display signal line to all the limited lock generation circuits in parallel, and a lock signal and address signal from the corresponding processor in each limited lock generation circuit. means for determining an address area to be limitedly locked by inputting a common bus use request signal from the corresponding processor, and a signal on a limited lock display signal line for the address area to be limitedly locked indicates a locked state. means for outputting a common bus use request signal from the limited lock generation circuit to the common bus use right determining circuit by fully operating the common bus only when the limited lock generation circuit does not have a common bus, and a common bus use permission signal is provided via the common bus. and means for setting a signal on a limited lock display signal line for the address area to be limited locked to 5 in the limited lock generating circuit to indicate a locked state.