JPS59229663A - Parallel processing multi-cpu system - Google Patents

Abstract

PURPOSE:To attain parallel processing of respective CPUs and to improve the efficiency of the titled system by forming a read/write conversion circuit in each CPU module and transferring data in one CPU module to all other CPUs simultaneously. CONSTITUTION:When a direct memory access request signal -DMARQ is inputted from a multi-CPU controller, a CPU7 makes bus floating status. A data bus 9 and an address bus 10 in the module are connected to an external bus 6 through a bi-directional bus buffer 11 and a unilateral bus buffer 12. When a memory enable signal -ME is inputted, a -RD/-WR conversion circuit 13 compares the module number of the self-CPU with the upper bit of an external address bus 62 by its comparator and sends a read signal RD at the time of coincidence and a write signal -WR in other cases to an RAM16 through a unilateral buffer 15.

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a multi-CPU system, and particularly to a parallel processing multi-CPU system in which each OPU simultaneously shares a memo Vt.

Currently, as a multi-CPU system, there is a system in which the OPU and memory systems, each operating independently, are connected to a common bus, and all common memos on this path are mutually accessed and data exchanged. Most commonly used.

Note that this memory is called a dual port or multiport RAM.

The problem with this system is that as the number of connected CPU modules increases, efficiency decreases as each OPU has access, and furthermore, each OPU transfers all data sequentially, making it difficult to synchronize data. The shortcomings become obvious.

The present invention was made with the aim of solving the above-mentioned drawbacks, and includes a read/Write conversion circuit provided in the CPU module, converts a predetermined input signal sound to a read signal for only one CPU module, The other system converts the data into a write signal and transfers the data in the memory of one CPU module to the memories of all other CPU modules at once.

An embodiment in which the present invention is applied to a system provided with four 0PUfils will be described below with reference to the drawings.

FIG. 1 is a schematic diagram of an embodiment of the invention, showing how CPU modules 1-1 are connected to an external path 6 to which a multi-CPU controller 5 is attached.

FIG. 2 shows the internal configuration of the CPU module, and the portion surrounded by broken lines is the CPU module.

The CPU module normally operates within its own module, but when the direct memory access request signal DMARQ comes from the multi-CPU controller 5, the 0PU 7 puts the path 8 in the 70-ting state and connects the data bus 9 and address bus inside the module. 10 is an external path 6 that runs through the bidirectional path buffer 11 and the unidirectional path buffer 12.
1C connected.

Furthermore, when the memory enable signal ME'lH is input, the conversion/WR conversion circuit 13 compares the number of its own CPU module (assumed to have been set in advance with the switch 14) and the upper bits of the external address bus 62. 13
1 and when they match, T5t is applied to the read signal'.
-1 Otherwise write signal WR gold unidirectional buffer 15
The data is then sent to the RAM 16.

FIG. 3 shows a specific circuit example of the WR/WR conversion circuit 13. In FIG.

The RAM 16 has data areas equal to the number of CPU modules. In the example explained here, there are 4 areas (
A-D) will have. The RAM 16 in FIG. 2 conceptually shows this.

Area A is the data area of the OPU of the CPU module 1, and contains the OPU status. Similarly, area B
O and D correspond to CPU module 2.3.4, respectively.

Configured as described above, the present invention operates as follows.

Usually each OPU module has an RA in the same module.
It is assumed that all calculations are performed using data of M. At this time, the status of other CPU modules can be determined by reading the internal sound of its own RAM. This is because the multi-CPU controller 5 exchanges data with each other. This data transfer is carried out at regular intervals.

The multi-CPU controller sends each OPUK at regular intervals.
It requests DMA'e and issues an address and ME signal.

The operation order will be explained below with reference to the operation diagrams shown in FIGS. 4 to 8.

First, as shown in FIG. 4, the multi-CPU controller 5 sends a direct memory access request signal DMARQi to each CPU module at a period T, and all modules output a direct memory access MEt-.

Next, as shown in FIG. 5, the CPU module 1 reads out the memory at address ○○○ in its own internal data area 61 when the upper address matches its own address.
Send to. All other CPU modules write this data into their own internal RAM using the ``1'' signal. In this case, the address is incremented and is not replaced after this cycle.

Thereafter, by incrementing the address, the module whose upper address matches becomes 2, jD, and the CPU module 1 takes in the data, and the CPU module 2 becomes the sending side (FIG. 6).

When this cycle completes, the RAM 11C in each OPU module will contain common data, and the multi-OPU controller 5 will drop the direct memory access request signal DMARQi, allowing each OPU module to operate in parallel. and perform processing on the data. (7th
．． (Fig. 8) The case in which there are four OPUs has been described above, but it goes without saying that it can also be used with more than four OPUs.

As described above, according to the present invention, each CPU can perform processing in parallel, so a multi-OPU system with high effective efficiency can be realized.

[Brief explanation of drawings]

FIG. 1 is a schematic diagram of an embodiment of the present invention, FIG. 2 is a block diagram of an OPU module according to the present invention, FIG. 83 is a specific circuit diagram of an RD/WR switching circuit according to the present invention, and FIGS. The figure is a diagram illustrating the specific operation of the present invention. 1 to 4...OPU module, 5...Multi OPU
Control μm2.6...External path, Patent applicant: Yaskawa Electric dIA Manufacturing Co., Ltd. Question 6, Gate 7, Gate 4, Gate 5''

Claims (3)

[Claims] (1) In a multi-CPU system connected to a common external path, each of the CPU modules is connected to a common external path.
All the read/write conversion circuits in the PU module input all the memory enable signals issued by the multi-OPU controller, and compare the OFυ module number set in advance with a predetermined part of the address data issued by the multi-OPU controller. When they match, the memory enable signal is converted into a read signal, and when they do not match, it is converted into a write signal and sent to each memory, thereby transferring the memory data of one CPU module to the memory of another CPU module. A parallel processing multi-CPU system that is characterized by simultaneous transfer. (2) The parallel processing multi-CPU system according to claim 1, wherein the CPU module number is set by a setting switch. (3) The parallel processing multi-CPU system according to claim 1, characterized in that address data provided above the bit tl expressing the number of CPU modules is used.